Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 1 | /* |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 2 | * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Stefan Roese | 4d991cb | 2015-06-29 14:58:13 +0200 | [diff] [blame] | 8 | #include <ahci.h> |
| 9 | #include <linux/mbus.h> |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
Stefan Roese | 5730360 | 2015-05-18 16:09:43 +0000 | [diff] [blame] | 11 | #include <asm/pl310.h> |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 12 | #include <asm/arch/cpu.h> |
| 13 | #include <asm/arch/soc.h> |
Stefan Roese | 7f1adcd | 2015-06-29 14:58:10 +0200 | [diff] [blame] | 14 | #include <sdhci.h> |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 15 | |
| 16 | #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) |
| 17 | #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) |
| 18 | |
| 19 | static struct mbus_win windows[] = { |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 20 | /* SPI */ |
Stefan Roese | 8ed20d6 | 2015-07-01 12:55:07 +0200 | [diff] [blame] | 21 | { MBUS_SPI_BASE, MBUS_SPI_SIZE, |
| 22 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 23 | |
| 24 | /* NOR */ |
Stefan Roese | 8ed20d6 | 2015-07-01 12:55:07 +0200 | [diff] [blame] | 25 | { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, |
| 26 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 27 | }; |
| 28 | |
Stefan Roese | 42cc034 | 2015-08-25 14:09:12 +0200 | [diff] [blame] | 29 | void lowlevel_init(void) |
| 30 | { |
| 31 | /* |
| 32 | * Dummy implementation, we only need LOWLEVEL_INIT |
| 33 | * on Armada to configure CP15 in start.S / cpu_init_cp15() |
| 34 | */ |
| 35 | } |
| 36 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 37 | void reset_cpu(unsigned long ignored) |
| 38 | { |
| 39 | struct mvebu_system_registers *reg = |
| 40 | (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; |
| 41 | |
| 42 | writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); |
| 43 | writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); |
| 44 | while (1) |
| 45 | ; |
| 46 | } |
| 47 | |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 48 | int mvebu_soc_family(void) |
| 49 | { |
| 50 | u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; |
| 51 | |
Stefan Roese | bf0db8b | 2015-12-09 11:00:51 +0100 | [diff] [blame] | 52 | if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID)) |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 53 | return MVEBU_SOC_AXP; |
| 54 | |
| 55 | if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || |
| 56 | devid == SOC_88F6828_ID) |
| 57 | return MVEBU_SOC_A38X; |
| 58 | |
| 59 | return MVEBU_SOC_UNKNOWN; |
| 60 | } |
| 61 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 62 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 63 | int print_cpuinfo(void) |
| 64 | { |
| 65 | u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; |
| 66 | u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; |
| 67 | |
| 68 | puts("SoC: "); |
| 69 | |
| 70 | switch (devid) { |
Stefan Roese | bf0db8b | 2015-12-09 11:00:51 +0100 | [diff] [blame] | 71 | case SOC_MV78260_ID: |
| 72 | puts("MV78260-"); |
| 73 | break; |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 74 | case SOC_MV78460_ID: |
| 75 | puts("MV78460-"); |
| 76 | break; |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 77 | case SOC_88F6810_ID: |
| 78 | puts("MV88F6810-"); |
| 79 | break; |
| 80 | case SOC_88F6820_ID: |
| 81 | puts("MV88F6820-"); |
| 82 | break; |
| 83 | case SOC_88F6828_ID: |
| 84 | puts("MV88F6828-"); |
| 85 | break; |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 86 | default: |
| 87 | puts("Unknown-"); |
| 88 | break; |
| 89 | } |
| 90 | |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 91 | if (mvebu_soc_family() == MVEBU_SOC_AXP) { |
| 92 | switch (revid) { |
| 93 | case 1: |
| 94 | puts("A0\n"); |
| 95 | break; |
| 96 | case 2: |
| 97 | puts("B0\n"); |
| 98 | break; |
| 99 | default: |
| 100 | printf("?? (%x)\n", revid); |
| 101 | break; |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | if (mvebu_soc_family() == MVEBU_SOC_A38X) { |
| 106 | switch (revid) { |
| 107 | case MV_88F68XX_Z1_ID: |
| 108 | puts("Z1\n"); |
| 109 | break; |
| 110 | case MV_88F68XX_A0_ID: |
| 111 | puts("A0\n"); |
| 112 | break; |
| 113 | default: |
| 114 | printf("?? (%x)\n", revid); |
| 115 | break; |
| 116 | } |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | #endif /* CONFIG_DISPLAY_CPUINFO */ |
| 122 | |
| 123 | /* |
| 124 | * This function initialize Controller DRAM Fastpath windows. |
| 125 | * It takes the CS size information from the 0x1500 scratch registers |
| 126 | * and sets the correct windows sizes and base addresses accordingly. |
| 127 | * |
| 128 | * These values are set in the scratch registers by the Marvell |
| 129 | * DDR3 training code, which is executed by the BootROM before the |
| 130 | * main payload (U-Boot) is executed. This training code is currently |
| 131 | * only available in the Marvell U-Boot version. It needs to be |
| 132 | * ported to mainline U-Boot SPL at some point. |
| 133 | */ |
| 134 | static void update_sdram_window_sizes(void) |
| 135 | { |
| 136 | u64 base = 0; |
| 137 | u32 size, temp; |
| 138 | int i; |
| 139 | |
| 140 | for (i = 0; i < SDRAM_MAX_CS; i++) { |
| 141 | size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; |
| 142 | if (size != 0) { |
| 143 | size |= ~(SDRAM_ADDR_MASK); |
| 144 | |
| 145 | /* Set Base Address */ |
| 146 | temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); |
| 147 | writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); |
| 148 | |
| 149 | /* |
| 150 | * Check if out of max window size and resize |
| 151 | * the window |
| 152 | */ |
| 153 | temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & |
| 154 | ~(SDRAM_ADDR_MASK)) | 1; |
| 155 | temp |= (size & SDRAM_ADDR_MASK); |
| 156 | writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); |
| 157 | |
| 158 | base += ((u64)size + 1); |
| 159 | } else { |
| 160 | /* |
| 161 | * Disable window if not used, otherwise this |
| 162 | * leads to overlapping enabled windows with |
| 163 | * pretty strange results |
| 164 | */ |
| 165 | clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); |
| 166 | } |
| 167 | } |
| 168 | } |
| 169 | |
Stefan Roese | 9f62b44 | 2015-04-24 10:49:11 +0200 | [diff] [blame] | 170 | void mmu_disable(void) |
| 171 | { |
| 172 | asm volatile( |
| 173 | "mrc p15, 0, r0, c1, c0, 0\n" |
| 174 | "bic r0, #1\n" |
| 175 | "mcr p15, 0, r0, c1, c0, 0\n"); |
| 176 | } |
| 177 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 178 | #ifdef CONFIG_ARCH_CPU_INIT |
Kevin Smith | e1b078e | 2015-05-18 16:09:44 +0000 | [diff] [blame] | 179 | static void set_cbar(u32 addr) |
| 180 | { |
| 181 | asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); |
| 182 | } |
| 183 | |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 184 | #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) |
| 185 | #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) |
| 186 | #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ |
| 187 | (((addr) & 0xF) << 6)) |
| 188 | #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ |
| 189 | (((reg) & 0xF) << 2)) |
| 190 | |
| 191 | static void setup_usb_phys(void) |
| 192 | { |
| 193 | int dev; |
| 194 | |
| 195 | /* |
| 196 | * USB PLL init |
| 197 | */ |
| 198 | |
| 199 | /* Setup PLL frequency */ |
| 200 | /* USB REF frequency = 25 MHz */ |
| 201 | clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); |
| 202 | |
| 203 | /* Power up PLL and PHY channel */ |
Stefan Roese | ab8a4c6 | 2015-12-04 13:08:34 +0100 | [diff] [blame] | 204 | setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 205 | |
| 206 | /* Assert VCOCAL_START */ |
Stefan Roese | ab8a4c6 | 2015-12-04 13:08:34 +0100 | [diff] [blame] | 207 | setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 208 | |
| 209 | mdelay(1); |
| 210 | |
| 211 | /* |
| 212 | * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) |
| 213 | */ |
| 214 | |
| 215 | for (dev = 0; dev < 3; dev++) { |
Stefan Roese | ab8a4c6 | 2015-12-04 13:08:34 +0100 | [diff] [blame] | 216 | setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 217 | |
| 218 | /* Assert REG_RCAL_START in channel REG 1 */ |
Stefan Roese | ab8a4c6 | 2015-12-04 13:08:34 +0100 | [diff] [blame] | 219 | setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 220 | udelay(40); |
Stefan Roese | ab8a4c6 | 2015-12-04 13:08:34 +0100 | [diff] [blame] | 221 | clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 222 | } |
| 223 | } |
Kevin Smith | e1b078e | 2015-05-18 16:09:44 +0000 | [diff] [blame] | 224 | |
Stefan Roese | f4e6ec7 | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 225 | /* |
| 226 | * This function is not called from the SPL U-Boot version |
| 227 | */ |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 228 | int arch_cpu_init(void) |
| 229 | { |
Stefan Roese | 42cc034 | 2015-08-25 14:09:12 +0200 | [diff] [blame] | 230 | struct pl310_regs *const pl310 = |
| 231 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; |
| 232 | |
Stefan Roese | cefd764 | 2015-08-24 11:03:50 +0200 | [diff] [blame] | 233 | /* |
| 234 | * Only with disabled MMU its possible to switch the base |
| 235 | * register address on Armada 38x. Without this the SDRAM |
| 236 | * located at >= 0x4000.0000 is also not accessible, as its |
| 237 | * still locked to cache. |
| 238 | */ |
| 239 | mmu_disable(); |
Stefan Roese | 9f62b44 | 2015-04-24 10:49:11 +0200 | [diff] [blame] | 240 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 241 | /* Linux expects the internal registers to be at 0xf1000000 */ |
| 242 | writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); |
Kevin Smith | e1b078e | 2015-05-18 16:09:44 +0000 | [diff] [blame] | 243 | set_cbar(SOC_REGS_PHY_BASE + 0xC000); |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 244 | |
Stefan Roese | cefd764 | 2015-08-24 11:03:50 +0200 | [diff] [blame] | 245 | /* |
| 246 | * From this stage on, the SoC detection is working. As we have |
| 247 | * configured the internal register base to the value used |
| 248 | * in the macros / defines in the U-Boot header (soc.h). |
| 249 | */ |
Stefan Roese | cefd764 | 2015-08-24 11:03:50 +0200 | [diff] [blame] | 250 | |
Stefan Roese | c86d53f | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 251 | if (mvebu_soc_family() == MVEBU_SOC_A38X) { |
| 252 | /* |
| 253 | * To fully release / unlock this area from cache, we need |
| 254 | * to flush all caches and disable the L2 cache. |
| 255 | */ |
| 256 | icache_disable(); |
| 257 | dcache_disable(); |
| 258 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 259 | } |
Stefan Roese | cefd764 | 2015-08-24 11:03:50 +0200 | [diff] [blame] | 260 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 261 | /* |
| 262 | * We need to call mvebu_mbus_probe() before calling |
| 263 | * update_sdram_window_sizes() as it disables all previously |
| 264 | * configured mbus windows and then configures them as |
| 265 | * required for U-Boot. Calling update_sdram_window_sizes() |
| 266 | * without this configuration will not work, as the internal |
| 267 | * registers can't be accessed reliably because of potenial |
| 268 | * double mapping. |
| 269 | * After updating the SDRAM access windows we need to call |
| 270 | * mvebu_mbus_probe() again, as this now correctly configures |
| 271 | * the SDRAM areas that are later used by the MVEBU drivers |
| 272 | * (e.g. USB, NETA). |
| 273 | */ |
| 274 | |
| 275 | /* |
| 276 | * First disable all windows |
| 277 | */ |
| 278 | mvebu_mbus_probe(NULL, 0); |
| 279 | |
Stefan Roese | 9c6d3b7 | 2015-04-25 06:29:51 +0200 | [diff] [blame] | 280 | if (mvebu_soc_family() == MVEBU_SOC_AXP) { |
| 281 | /* |
| 282 | * Now the SDRAM access windows can be reconfigured using |
| 283 | * the information in the SDRAM scratch pad registers |
| 284 | */ |
| 285 | update_sdram_window_sizes(); |
| 286 | } |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 287 | |
| 288 | /* |
| 289 | * Finally the mbus windows can be configured with the |
| 290 | * updated SDRAM sizes |
| 291 | */ |
| 292 | mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); |
| 293 | |
Stefan Roese | 2a0b7dc | 2015-07-16 10:40:05 +0200 | [diff] [blame] | 294 | if (mvebu_soc_family() == MVEBU_SOC_AXP) { |
| 295 | /* Enable GBE0, GBE1, LCD and NFC PUP */ |
| 296 | clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, |
| 297 | GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | |
| 298 | NAND_PUP_EN | SPI_PUP_EN); |
Stefan Roese | dee40d2 | 2015-07-22 18:26:13 +0200 | [diff] [blame] | 299 | |
| 300 | /* Configure USB PLL and PHYs on AXP */ |
| 301 | setup_usb_phys(); |
Stefan Roese | 2a0b7dc | 2015-07-16 10:40:05 +0200 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | /* Enable NAND and NAND arbiter */ |
| 305 | clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); |
| 306 | |
Stefan Roese | 501c098 | 2015-07-01 13:28:39 +0200 | [diff] [blame] | 307 | /* Disable MBUS error propagation */ |
| 308 | clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); |
| 309 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 310 | return 0; |
| 311 | } |
| 312 | #endif /* CONFIG_ARCH_CPU_INIT */ |
| 313 | |
Stefan Roese | 2a0b7dc | 2015-07-16 10:40:05 +0200 | [diff] [blame] | 314 | u32 mvebu_get_nand_clock(void) |
| 315 | { |
| 316 | return CONFIG_SYS_MVEBU_PLL_CLOCK / |
| 317 | ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & |
| 318 | NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); |
| 319 | } |
| 320 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 321 | /* |
| 322 | * SOC specific misc init |
| 323 | */ |
| 324 | #if defined(CONFIG_ARCH_MISC_INIT) |
| 325 | int arch_misc_init(void) |
| 326 | { |
| 327 | /* Nothing yet, perhaps we need something here later */ |
| 328 | return 0; |
| 329 | } |
| 330 | #endif /* CONFIG_ARCH_MISC_INIT */ |
| 331 | |
Stefan Roese | 7f1adcd | 2015-06-29 14:58:10 +0200 | [diff] [blame] | 332 | #ifdef CONFIG_MV_SDHCI |
| 333 | int board_mmc_init(bd_t *bis) |
| 334 | { |
| 335 | mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, |
| 336 | SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); |
| 337 | |
| 338 | return 0; |
| 339 | } |
| 340 | #endif |
| 341 | |
Stefan Roese | 4d991cb | 2015-06-29 14:58:13 +0200 | [diff] [blame] | 342 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 343 | #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 |
| 344 | #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 |
| 345 | |
| 346 | #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) |
| 347 | #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) |
| 348 | #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) |
| 349 | |
| 350 | static void ahci_mvebu_mbus_config(void __iomem *base) |
| 351 | { |
| 352 | const struct mbus_dram_target_info *dram; |
| 353 | int i; |
| 354 | |
| 355 | dram = mvebu_mbus_dram_info(); |
| 356 | |
| 357 | for (i = 0; i < 4; i++) { |
| 358 | writel(0, base + AHCI_WINDOW_CTRL(i)); |
| 359 | writel(0, base + AHCI_WINDOW_BASE(i)); |
| 360 | writel(0, base + AHCI_WINDOW_SIZE(i)); |
| 361 | } |
| 362 | |
| 363 | for (i = 0; i < dram->num_cs; i++) { |
| 364 | const struct mbus_dram_window *cs = dram->cs + i; |
| 365 | |
| 366 | writel((cs->mbus_attr << 8) | |
| 367 | (dram->mbus_dram_target_id << 4) | 1, |
| 368 | base + AHCI_WINDOW_CTRL(i)); |
| 369 | writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); |
| 370 | writel(((cs->size - 1) & 0xffff0000), |
| 371 | base + AHCI_WINDOW_SIZE(i)); |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | static void ahci_mvebu_regret_option(void __iomem *base) |
| 376 | { |
| 377 | /* |
| 378 | * Enable the regret bit to allow the SATA unit to regret a |
| 379 | * request that didn't receive an acknowlegde and avoid a |
| 380 | * deadlock |
| 381 | */ |
| 382 | writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); |
| 383 | writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); |
| 384 | } |
| 385 | |
| 386 | void scsi_init(void) |
| 387 | { |
| 388 | printf("MVEBU SATA INIT\n"); |
| 389 | ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); |
| 390 | ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); |
| 391 | ahci_init((void __iomem *)MVEBU_SATA0_BASE); |
| 392 | } |
| 393 | #endif |
| 394 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 395 | void enable_caches(void) |
| 396 | { |
Stefan Roese | 60b7532 | 2015-04-25 06:29:55 +0200 | [diff] [blame] | 397 | /* Avoid problem with e.g. neta ethernet driver */ |
| 398 | invalidate_dcache_all(); |
| 399 | |
Stefan Roese | 41e5ee5 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 400 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 401 | dcache_enable(); |
| 402 | } |
Stefan Roese | 3e5ce7c | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 403 | |
| 404 | void v7_outer_cache_enable(void) |
| 405 | { |
Stefan Roese | 3e5ce7c | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 406 | if (mvebu_soc_family() == MVEBU_SOC_AXP) { |
Stefan Roese | c86d53f | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 407 | struct pl310_regs *const pl310 = |
| 408 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; |
Stefan Roese | 3e5ce7c | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 409 | u32 u; |
| 410 | |
Stefan Roese | c86d53f | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 411 | /* The L2 cache is already disabled at this point */ |
| 412 | |
Stefan Roese | 3e5ce7c | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 413 | /* |
| 414 | * For Aurora cache in no outer mode, enable via the CP15 |
| 415 | * coprocessor broadcasting of cache commands to L2. |
| 416 | */ |
| 417 | asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); |
| 418 | u |= BIT(8); /* Set the FW bit */ |
| 419 | asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); |
| 420 | |
| 421 | isb(); |
| 422 | |
| 423 | /* Enable the L2 cache */ |
| 424 | setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 425 | } |
| 426 | } |
Stefan Roese | f0e8173 | 2015-12-14 12:31:48 +0100 | [diff] [blame] | 427 | |
| 428 | void v7_outer_cache_disable(void) |
| 429 | { |
| 430 | struct pl310_regs *const pl310 = |
| 431 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; |
| 432 | |
| 433 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 434 | } |