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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek38b343d2012-09-13 20:23:35 +00002/*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
Michal Simek38b343d2012-09-13 20:23:35 +00005 */
6#include <common.h>
Simon Glass9edefc22019-11-14 12:57:37 -07007#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -06008#include <init.h>
Michal Simek4aba5fb2018-01-17 10:56:22 -03009#include <zynqpl.h>
Simon Glass90526e92020-05-10 11:39:56 -060010#include <asm/cache.h>
Michal Simek00ed3452013-02-04 12:42:25 +010011#include <asm/io.h>
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080012#include <asm/arch/clk.h>
Michal Simek00ed3452013-02-04 12:42:25 +010013#include <asm/arch/hardware.h>
Michal Simek4aba5fb2018-01-17 10:56:22 -030014#include <asm/arch/ps7_init_gpl.h>
15#include <asm/arch/sys_proto.h>
Michal Simek38b343d2012-09-13 20:23:35 +000016
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053017#define ZYNQ_SILICON_VER_MASK 0xF0000000
18#define ZYNQ_SILICON_VER_SHIFT 28
19
Michal Simek29bd8ad2020-09-09 14:41:56 +020020#if CONFIG_IS_ENABLED(FPGA)
Michal Simek4aba5fb2018-01-17 10:56:22 -030021xilinx_desc fpga = {
22 .family = xilinx_zynq,
23 .iface = devcfg,
24 .operations = &zynq_op,
25};
26#endif
27
28static const struct {
29 u8 idcode;
30#if defined(CONFIG_FPGA)
31 u32 fpga_size;
32#endif
33 char *devicename;
34} zynq_fpga_descs[] = {
35 ZYNQ_DESC(7Z007S),
36 ZYNQ_DESC(7Z010),
37 ZYNQ_DESC(7Z012S),
38 ZYNQ_DESC(7Z014S),
39 ZYNQ_DESC(7Z015),
40 ZYNQ_DESC(7Z020),
41 ZYNQ_DESC(7Z030),
42 ZYNQ_DESC(7Z035),
43 ZYNQ_DESC(7Z045),
44 ZYNQ_DESC(7Z100),
45 { /* Sentinel */ },
46};
47
Michal Simek262f08d2013-08-22 14:52:02 +020048int arch_cpu_init(void)
49{
Michal Simek00ed3452013-02-04 12:42:25 +010050 zynq_slcr_unlock();
Michal Simekd7e269c2014-01-14 14:21:52 +010051#ifndef CONFIG_SPL_BUILD
Michal Simek00ed3452013-02-04 12:42:25 +010052 /* Device config APB, unlock the PCAP */
53 writel(0x757BDF0D, &devcfg_base->unlock);
54 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
55
Michal Simekc1824ea2013-08-28 08:26:41 +020056#if (CONFIG_SYS_SDRAM_BASE == 0)
57 /* remap DDR to zero, FILTERSTART */
58 writel(0, &scu_base->filter_start);
59
Michal Simek00ed3452013-02-04 12:42:25 +010060 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
61 writel(0x1F, &slcr_base->ocm_cfg);
62 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
63 writel(0x0, &slcr_base->fpga_rst_ctrl);
Michal Simek00ed3452013-02-04 12:42:25 +010064 /* Set urgent bits with register */
65 writel(0x0, &slcr_base->ddr_urgent_sel);
66 /* Urgent write, ports S2/S3 */
67 writel(0xC, &slcr_base->ddr_urgent);
Michal Simekc1824ea2013-08-28 08:26:41 +020068#endif
Michal Simekd7e269c2014-01-14 14:21:52 +010069#endif
Michal Simek00ed3452013-02-04 12:42:25 +010070 zynq_slcr_lock();
Michal Simek262f08d2013-08-22 14:52:02 +020071
72 return 0;
Michal Simek00ed3452013-02-04 12:42:25 +010073}
Michal Simek38b343d2012-09-13 20:23:35 +000074
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053075unsigned int zynq_get_silicon_version(void)
76{
Masahiro Yamada63a75782016-09-06 22:17:38 +090077 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
78 >> ZYNQ_SILICON_VER_SHIFT;
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053079}
80
Harald Seiler35b65dd2020-12-15 16:47:52 +010081void reset_cpu(void)
Michal Simek38b343d2012-09-13 20:23:35 +000082{
Michal Simek59c651f2013-02-04 12:38:59 +010083 zynq_slcr_cpu_reset();
Michal Simek38b343d2012-09-13 20:23:35 +000084 while (1)
85 ;
86}
Michal Simek673ba272014-01-03 09:32:35 +010087
Trevor Woerner10015022019-05-03 09:41:00 -040088#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Michal Simek673ba272014-01-03 09:32:35 +010089void enable_caches(void)
90{
91 /* Enable D-cache. I-cache is already enabled in start.S */
92 dcache_enable();
93}
94#endif
Michal Simek4aba5fb2018-01-17 10:56:22 -030095
96static int __maybe_unused cpu_desc_id(void)
97{
98 u32 idcode;
99 u8 i;
100
101 idcode = zynq_slcr_get_idcode();
102 for (i = 0; zynq_fpga_descs[i].idcode; i++) {
103 if (zynq_fpga_descs[i].idcode == idcode)
104 return i;
105 }
106
107 return -ENODEV;
108}
109
110#if defined(CONFIG_ARCH_EARLY_INIT_R)
111int arch_early_init_r(void)
112{
Michal Simek29bd8ad2020-09-09 14:41:56 +0200113#if CONFIG_IS_ENABLED(FPGA)
Michal Simek4aba5fb2018-01-17 10:56:22 -0300114 int cpu_id = cpu_desc_id();
115
116 if (cpu_id < 0)
117 return 0;
118
119 fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
120 fpga.name = zynq_fpga_descs[cpu_id].devicename;
121 fpga_init();
122 fpga_add(fpga_xilinx, &fpga);
123#endif
124 return 0;
125}
126#endif
Michal Simek0b4b82a2018-02-28 09:50:07 +0100127
128#ifdef CONFIG_DISPLAY_CPUINFO
129int print_cpuinfo(void)
130{
131 u32 version;
132 int cpu_id = cpu_desc_id();
133
134 if (cpu_id < 0)
135 return 0;
136
137 version = zynq_get_silicon_version() << 1;
138 if (version > (PCW_SILICON_VERSION_3 << 1))
139 version += 1;
140
141 printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
142 printf("Silicon: v%d.%d\n", version >> 1, version & 1);
143 return 0;
144}
145#endif