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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roese51321062009-04-08 10:36:22 +02002 * (C) Copyright 2006-2009
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
Wolfgang Denk865f0f92008-01-23 14:31:17 +01007 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
Stefan Roese887e2ec2006-09-07 11:51:23 +02008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stefan Roese13628882007-12-13 14:52:53 +010026#include <libfdt.h>
27#include <fdt_support.h>
Stefan Roese4fb25a32008-06-25 10:59:22 +020028#include <ppc4xx.h>
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -050029#include <asm/gpio.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020030#include <asm/processor.h>
Stefan Roese5a5958b2007-10-15 11:29:33 +020031#include <asm/io.h>
Matthias Fuchs83a49c82008-01-16 10:33:46 +010032#include <asm/bitops.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020033
34DECLARE_GLOBAL_DATA_PTR;
35
Stefan Roesed8731332009-05-11 13:46:14 +020036#if !defined(CONFIG_SYS_NO_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roesed8731332009-05-11 13:46:14 +020038#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +020039
Stefan Roese51321062009-04-08 10:36:22 +020040extern void __ft_board_setup(void *blob, bd_t *bd);
41ulong flash_get_size(ulong base, int banknum);
Stefan Roese1b3c3602006-12-22 14:29:40 +010042
Stefan Roese887e2ec2006-09-07 11:51:23 +020043int board_early_init_f(void)
44{
Stefan Roesea78bc442007-01-05 10:40:36 +010045 u32 sdr0_cust0;
46 u32 sdr0_pfc1, sdr0_pfc2;
47 u32 reg;
Stefan Roese887e2ec2006-09-07 11:51:23 +020048
49 mtdcr(ebccfga, xbcfg);
50 mtdcr(ebccfgd, 0xb8400000);
51
Matthias Fuchs83a49c82008-01-16 10:33:46 +010052 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +020053 * Setup the interrupt controller polarities, triggers, etc.
Matthias Fuchs83a49c82008-01-16 10:33:46 +010054 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020055 mtdcr(uic0sr, 0xffffffff); /* clear all */
56 mtdcr(uic0er, 0x00000000); /* disable all */
57 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
58 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
59 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
60 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
61 mtdcr(uic0sr, 0xffffffff); /* clear all */
62
63 mtdcr(uic1sr, 0xffffffff); /* clear all */
64 mtdcr(uic1er, 0x00000000); /* disable all */
65 mtdcr(uic1cr, 0x00000000); /* all non-critical */
66 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
67 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
68 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
69 mtdcr(uic1sr, 0xffffffff); /* clear all */
70
71 mtdcr(uic2sr, 0xffffffff); /* clear all */
72 mtdcr(uic2er, 0x00000000); /* disable all */
73 mtdcr(uic2cr, 0x00000000); /* all non-critical */
74 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
75 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
76 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
77 mtdcr(uic2sr, 0xffffffff); /* clear all */
78
79 /* 50MHz tmrclk */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020081
82 /* clear write protects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020084
85 /* enable Ethernet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020087
88 /* enable USB device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
Stefan Roese887e2ec2006-09-07 11:51:23 +020090
Mike Nussb7386542008-02-06 11:10:11 -050091 /* select Ethernet (and optionally IIC1) pins */
Stefan Roese887e2ec2006-09-07 11:51:23 +020092 mfsdr(SDR0_PFC1, sdr0_pfc1);
Matthias Fuchs83a49c82008-01-16 10:33:46 +010093 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
94 SDR0_PFC1_SELECT_CONFIG_4;
Mike Nussb7386542008-02-06 11:10:11 -050095#ifdef CONFIG_I2C_MULTI_BUS
96 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
97#endif
Steven A. Falcoeab10072008-08-06 15:42:52 -040098 /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
99 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
100 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
101 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
102
Stefan Roese887e2ec2006-09-07 11:51:23 +0200103 mfsdr(SDR0_PFC2, sdr0_pfc2);
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100104 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
105 SDR0_PFC2_SELECT_CONFIG_4;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200106 mtsdr(SDR0_PFC2, sdr0_pfc2);
107 mtsdr(SDR0_PFC1, sdr0_pfc1);
108
109 /* PCI arbiter enabled */
110 mfsdr(sdr_pci0, reg);
111 mtsdr(sdr_pci0, 0x80000000 | reg);
112
113 /* setup NAND FLASH */
114 mfsdr(SDR0_CUST0, sdr0_cust0);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200115 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
Stefan Roese887e2ec2006-09-07 11:51:23 +0200116 SDR0_CUST0_NDFC_ENABLE |
117 SDR0_CUST0_NDFC_BW_8_BIT |
118 SDR0_CUST0_NDFC_ARE_MASK |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200120 mtsdr(SDR0_CUST0, sdr0_cust0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200121
122 return 0;
123}
124
Stefan Roese887e2ec2006-09-07 11:51:23 +0200125int misc_init_r(void)
126{
Stefan Roesed8731332009-05-11 13:46:14 +0200127#if !defined(CONFIG_SYS_NO_FLASH)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200128 uint pbcr;
129 int size_val = 0;
Stefan Roesed8731332009-05-11 13:46:14 +0200130#endif
Stefan Roese854bc8d2006-09-13 13:51:58 +0200131#ifdef CONFIG_440EPX
Stefan Roese887e2ec2006-09-07 11:51:23 +0200132 unsigned long usb2d0cr = 0;
133 unsigned long usb2phy0cr, usb2h0cr = 0;
134 unsigned long sdr0_pfc1;
135 char *act = getenv("usbact");
Stefan Roese854bc8d2006-09-13 13:51:58 +0200136#endif
Stefan Roesed8731332009-05-11 13:46:14 +0200137 u32 reg;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200138
Stefan Roesed8731332009-05-11 13:46:14 +0200139#if !defined(CONFIG_SYS_NO_FLASH)
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100140 /* Re-do flash sizing to get full correct info */
Stefan Roese1b3c3602006-12-22 14:29:40 +0100141
142 /* adjust flash start and offset */
143 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
144 gd->bd->bi_flashoffset = 0;
145
Stefan Roese887e2ec2006-09-07 11:51:23 +0200146#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
147 mtdcr(ebccfga, pb3cr);
148#else
149 mtdcr(ebccfga, pb0cr);
150#endif
151 pbcr = mfdcr(ebccfgd);
Wolfgang Denk865f0f92008-01-23 14:31:17 +0100152 size_val = ffs(gd->bd->bi_flashsize) - 21;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200153 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
154#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
155 mtdcr(ebccfga, pb3cr);
156#else
157 mtdcr(ebccfga, pb0cr);
158#endif
159 mtdcr(ebccfgd, pbcr);
160
Stefan Roese1b3c3602006-12-22 14:29:40 +0100161 /*
162 * Re-check to get correct base address
163 */
164 flash_get_size(gd->bd->bi_flashstart, 0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200165
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200166#ifdef CONFIG_ENV_IS_IN_FLASH
Stefan Roese887e2ec2006-09-07 11:51:23 +0200167 /* Monitor protection ON by default */
168 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese887e2ec2006-09-07 11:51:23 +0200170 0xffffffff,
171 &flash_info[0]);
172
173 /* Env protection ON by default */
174 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200175 CONFIG_ENV_ADDR_REDUND,
176 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
Stefan Roese887e2ec2006-09-07 11:51:23 +0200177 &flash_info[0]);
178#endif
Stefan Roesed8731332009-05-11 13:46:14 +0200179#endif /* CONFIG_SYS_NO_FLASH */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200180
181 /*
182 * USB suff...
183 */
Stefan Roese854bc8d2006-09-13 13:51:58 +0200184#ifdef CONFIG_440EPX
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100185 if (act == NULL || strcmp(act, "hostdev") == 0) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200186 /* SDR Setting */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200187 mfsdr(SDR0_PFC1, sdr0_pfc1);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200188 mfsdr(SDR0_USB2D0CR, usb2d0cr);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200189 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
190 mfsdr(SDR0_USB2H0CR, usb2h0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200191
192 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100193 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200194 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100195 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200196 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100197 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200198 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100199 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200202
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100203 /*
204 * An 8-bit/60MHz interface is the only possible alternative
205 * when connecting the Device to the PHY
206 */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200207 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100208 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200209
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100210 /*
211 * To enable the USB 2.0 Device function
212 * through the UTMI interface
213 */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200214 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100215 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200216
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200217 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100218 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200219
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200220 mtsdr(SDR0_PFC1, sdr0_pfc1);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200221 mtsdr(SDR0_USB2D0CR, usb2d0cr);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200222 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
223 mtsdr(SDR0_USB2H0CR, usb2h0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200224
225 /*clear resets*/
226 udelay (1000);
227 mtsdr(SDR0_SRST1, 0x00000000);
228 udelay (1000);
229 mtsdr(SDR0_SRST0, 0x00000000);
230
231 printf("USB: Host(int phy) Device(ext phy)\n");
232
233 } else if (strcmp(act, "dev") == 0) {
234 /*-------------------PATCH-------------------------------*/
235 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
236
237 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100238 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200239 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100240 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200241 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100242 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200243 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100244 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200245 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
246
247 udelay (1000);
248 mtsdr(SDR0_SRST1, 0x672c6000);
249
250 udelay (1000);
251 mtsdr(SDR0_SRST0, 0x00000080);
252
253 udelay (1000);
254 mtsdr(SDR0_SRST1, 0x60206000);
255
256 *(unsigned int *)(0xe0000350) = 0x00000001;
257
258 udelay (1000);
259 mtsdr(SDR0_SRST1, 0x60306000);
260 /*-------------------PATCH-------------------------------*/
261
262 /* SDR Setting */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200263 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200264 mfsdr(SDR0_USB2H0CR, usb2h0cr);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200265 mfsdr(SDR0_USB2D0CR, usb2d0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200266 mfsdr(SDR0_PFC1, sdr0_pfc1);
267
268 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100269 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200270 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100271 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200272 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100273 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200274 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100275 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200276 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100277 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200278
279 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100280 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200281
282 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100283 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200284
285 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100286 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200287
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200288 mtsdr(SDR0_USB2H0CR, usb2h0cr);
289 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200290 mtsdr(SDR0_USB2D0CR, usb2d0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200291 mtsdr(SDR0_PFC1, sdr0_pfc1);
292
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100293 /* clear resets */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200294 udelay (1000);
295 mtsdr(SDR0_SRST1, 0x00000000);
296 udelay (1000);
297 mtsdr(SDR0_SRST0, 0x00000000);
298
299 printf("USB: Device(int phy)\n");
300 }
Stefan Roese854bc8d2006-09-13 13:51:58 +0200301#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200302
John Otken john@softadvances.com8ce16f52007-03-08 09:39:48 -0600303 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
304 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
305 mtsdr(SDR0_SRST1, reg);
306
Stefan Roesea78bc442007-01-05 10:40:36 +0100307 /*
308 * Clear PLB4A0_ACR[WRP]
309 * This fix will make the MAL burst disabling patch for the Linux
310 * EMAC driver obsolete.
311 */
312 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
313 mtdcr(plb4_acr, reg);
314
Stefan Roese887e2ec2006-09-07 11:51:23 +0200315 return 0;
316}
317
318int checkboard(void)
319{
320 char *s = getenv("serial#");
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100321 u8 rev;
322 u8 val;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200323
Stefan Roese854bc8d2006-09-13 13:51:58 +0200324#ifdef CONFIG_440EPX
Stefan Roese887e2ec2006-09-07 11:51:23 +0200325 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
Stefan Roese854bc8d2006-09-13 13:51:58 +0200326#else
327 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
328#endif
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
331 val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100332 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
333
Stefan Roese887e2ec2006-09-07 11:51:23 +0200334 if (s != NULL) {
335 puts(", serial# ");
336 puts(s);
337 }
338 putc('\n');
339
340 return (0);
341}
342
Matthias Fuchs1f840212008-01-08 15:40:09 +0100343#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
344/*
345 * Assign interrupts to PCI devices.
346 */
347void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
348{
Stefan Roesed1631fe2008-06-26 13:40:57 +0200349 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
Matthias Fuchs1f840212008-01-08 15:40:09 +0100350}
351#endif
352
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100353/*
354 * pci_pre_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200355 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100356 * This routine is called just prior to registering the hose and gives
357 * the board the opportunity to check things. Returning a value of zero
358 * indicates that things are bad & PCI initialization should be aborted.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200359 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100360 * Different boards may wish to customize the pci controller structure
361 * (add regions, override default access routines, etc) or perform
362 * certain pre-initialization actions.
363 */
Stefan Roese466fff12007-06-25 15:57:39 +0200364#if defined(CONFIG_PCI)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200365int pci_pre_init(struct pci_controller *hose)
366{
367 unsigned long addr;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200368
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100369 /*
370 * Set priority for all PLB3 devices to 0.
371 * Set PLB3 arbiter to fair mode.
372 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200373 mfsdr(sdr_amp1, addr);
374 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
375 addr = mfdcr(plb3_acr);
376 mtdcr(plb3_acr, addr | 0x80000000);
377
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100378 /*
379 * Set priority for all PLB4 devices to 0.
380 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200381 mfsdr(sdr_amp0, addr);
382 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
383 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
384 mtdcr(plb4_acr, addr);
385
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100386 /*
387 * Set Nebula PLB4 arbiter to fair mode.
388 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200389 /* Segment0 */
390 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
391 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
392 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
393 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
394 mtdcr(plb0_acr, addr);
395
396 /* Segment1 */
397 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
398 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
399 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
400 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
401 mtdcr(plb1_acr, addr);
402
Matthias Fuchs1f840212008-01-08 15:40:09 +0100403#ifdef CONFIG_PCI_PNP
404 hose->fixup_irq = sequoia_pci_fixup_irq;
405#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200406 return 1;
407}
Stefan Roese466fff12007-06-25 15:57:39 +0200408#endif /* defined(CONFIG_PCI) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200409
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100410/*
411 * pci_target_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200412 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100413 * The bootstrap configuration provides default settings for the pci
414 * inbound map (PIM). But the bootstrap config choices are limited and
415 * may not be sufficient for a given board.
416 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200418void pci_target_init(struct pci_controller *hose)
419{
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100420 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200421 * Set up Direct MMIO registers
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100422 */
423 /*
424 * PowerPC440EPX PCI Master configuration.
425 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
426 * PLB address 0xA0000000-0xDFFFFFFF
427 * ==> PCI address 0xA0000000-0xDFFFFFFF
428 * Use byte reversed out routines to handle endianess.
429 * Make this region non-prefetchable.
430 */
431 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
432 /* - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
434 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200435 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100436 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
437 /* and enable region */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200438
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100439 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
440 /* - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
442 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200443 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100444 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
445 /* and enable region */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200446
447 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100448 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
449 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
450 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200451
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100452 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200453 * Set up Configuration registers
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100454 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200455
456 /* Program the board's subsystem id/vendor id */
457 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 CONFIG_SYS_PCI_SUBSYS_VENDORID);
459 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200460
461 /* Configure command register as bus master */
462 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
463
464 /* 240nS PCI clock */
465 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
466
467 /* No error reporting */
468 pci_write_config_word(0, PCI_ERREN, 0);
469
470 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
471
472}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200476void pci_master_init(struct pci_controller *hose)
477{
478 unsigned short temp_short;
479
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100480 /*
481 * Write the PowerPC440 EP PCI Configuration regs.
482 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
483 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
484 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200485 pci_read_config_word(0, PCI_COMMAND, &temp_short);
486 pci_write_config_word(0, PCI_COMMAND,
487 temp_short | PCI_COMMAND_MASTER |
488 PCI_COMMAND_MEMORY);
489}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200491
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100492/*
493 * is_pci_host
Stefan Roese887e2ec2006-09-07 11:51:23 +0200494 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100495 * This routine is called to determine if a pci scan should be
496 * performed. With various hardware environments (especially cPCI and
497 * PPMC) it's insufficient to depend on the state of the arbiter enable
498 * bit in the strap register, or generic host/adapter assumptions.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200499 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100500 * Rather than hard-code a bad assumption in the general 440 code, the
501 * 440 pci code requires the board to decide at runtime.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200502 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100503 * Return 0 for adapter mode, non-zero for host (monarch) mode.
504 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200505#if defined(CONFIG_PCI)
506int is_pci_host(struct pci_controller *hose)
507{
508 /* Cactus is always configured as host. */
509 return (1);
510}
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100511#endif /* defined(CONFIG_PCI) */
512
Igor Lisitsina11e0692007-03-28 19:06:19 +0400513#if defined(CONFIG_POST)
514/*
515 * Returns 1 if keys pressed to start the power-on long-running tests
516 * Called from board_init_f().
517 */
518int post_hotkeys_pressed(void)
519{
520 return 0; /* No hotkeys supported */
521}
522#endif /* CONFIG_POST */
Stefan Roese51321062009-04-08 10:36:22 +0200523
Stefan Roesed8731332009-05-11 13:46:14 +0200524#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
Stefan Roese51321062009-04-08 10:36:22 +0200525/*
526 * On NAND-booting sequoia, we need to patch the chips select numbers
527 * in the dtb (CS0 - NAND, CS3 - NOR)
528 */
529void ft_board_setup(void *blob, bd_t *bd)
530{
531 int rc;
532 int len;
533 int nodeoffset;
534 struct fdt_property *prop;
535 u32 *reg;
536 char path[32];
537
538 /* First do common fdt setup */
539 __ft_board_setup(blob, bd);
540
541 /* And now configure NOR chip select to 3 instead of 0 */
542 strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
543 nodeoffset = fdt_path_offset(blob, path);
544 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
545 if (prop == NULL) {
546 printf("Unable to update NOR chip select for NAND booting\n");
547 return;
548 }
549 reg = (u32 *)&prop->data[0];
550 reg[0] = 3;
551 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
552 if (rc) {
553 printf("Unable to update property NOR mappings, err=%s\n",
554 fdt_strerror(rc));
555 return;
556 }
557
558 /* And now configure NAND chip select to 0 instead of 3 */
559 strcpy(path, "/plb/opb/ebc/ndfc@3,0");
560 nodeoffset = fdt_path_offset(blob, path);
561 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
562 if (prop == NULL) {
563 printf("Unable to update NDFC chip select for NAND booting\n");
564 return;
565 }
566 reg = (u32 *)&prop->data[0];
567 reg[0] = 0;
568 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
569 if (rc) {
570 printf("Unable to update property NDFC mappings, err=%s\n",
571 fdt_strerror(rc));
572 return;
573 }
574}
575#endif /* CONFIG_NAND_U_BOOT */