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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d94f92cbd7f4a4d3bf0d5d963b709c686e8f6633 / . / include / mpc5xxx.h
blob: 4218b050fc739326f000109adb4088583115aba4 [file] [log] [blame]
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
42
43/* Internal memory map */
44
45#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
46#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
47#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
48#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
49#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
50#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
51#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
52#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
53#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
54#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
55#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
56#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
57#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
58#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
59#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
60
61#if defined(CONFIG_MGT5100)
62#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
63#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame]64#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
65#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
66#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
67#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]68#elif defined(CONFIG_MPC5200)
69#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
70#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
71#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
72#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
73#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
74#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
75#endif
76
77#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
78#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
79#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
80#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
wdenkd94f92c2003-08-28 09:41:22 +0000[diff] [blame^]81#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]82#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame]83#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]84#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
85#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
86
87#if defined(CONFIG_MGT5100)
88#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
89#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
90#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
91#elif defined(CONFIG_MPC5200)
92#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
93#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
94#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
95#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
96#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
97#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
98#endif
99
100#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
101
102#if defined(CONFIG_MGT5100)
103#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
104#define MPC5XXX_SRAM_SIZE (8*1024)
105#elif defined(CONFIG_MPC5200)
106#define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
107#define MPC5XXX_SRAM_SIZE (16*1024)
108#endif
109
110/* SDRAM Controller */
111#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
112#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
113#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
114#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
115#if defined(CONFIG_MGT5100)
116#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
117#endif
118
119/* Clock Distribution Module */
120#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
121#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
122#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
123#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
124
125/* Local Plus Bus interface */
126#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
127#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
128#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
129#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
130#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
131#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
132#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
133#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
134#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
135#if defined(CONFIG_MPC5200)
136#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
137#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
138#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
139#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
140#endif
141
142/* GPIO registers */
143#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
144
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame]145/* PCI registers */
146#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
147#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
148#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
149#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
150#if defined(CONFIG_MGT5100)
151#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
152#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
153#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
154#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
155#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
156#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
157#elif defined(CONFIG_MPC5200)
158#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
159#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
160#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
161#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
162#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
163#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
164#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
165#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
166#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
167#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
168#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
169#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
170#endif
171
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]172/* Interrupt Controller registers */
173#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
174#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
175#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
176#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
177#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
178#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
179#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
180#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
181#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
182#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
183#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
184#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
185#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
186
wdenkd94f92c2003-08-28 09:41:22 +0000[diff] [blame^]187/* General Purpose Timers registers */
188#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
189#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
190
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]191/* Programmable Serial Controller (PSC) status register bits */
192#define PSC_SR_CDE 0x0080
193#define PSC_SR_RXRDY 0x0100
194#define PSC_SR_RXFULL 0x0200
195#define PSC_SR_TXRDY 0x0400
196#define PSC_SR_TXEMP 0x0800
197#define PSC_SR_OE 0x1000
198#define PSC_SR_PE 0x2000
199#define PSC_SR_FE 0x4000
200#define PSC_SR_RB 0x8000
201
202/* PSC Command values */
203#define PSC_RX_ENABLE 0x0001
204#define PSC_RX_DISABLE 0x0002
205#define PSC_TX_ENABLE 0x0004
206#define PSC_TX_DISABLE 0x0008
207#define PSC_SEL_MODE_REG_1 0x0010
208#define PSC_RST_RX 0x0020
209#define PSC_RST_TX 0x0030
210#define PSC_RST_ERR_STAT 0x0040
211#define PSC_RST_BRK_CHG_INT 0x0050
212#define PSC_START_BRK 0x0060
213#define PSC_STOP_BRK 0x0070
214
215/* PSC Rx FIFO status bits */
216#define PSC_RX_FIFO_ERR 0x0040
217#define PSC_RX_FIFO_UF 0x0020
218#define PSC_RX_FIFO_OF 0x0010
219#define PSC_RX_FIFO_FR 0x0008
220#define PSC_RX_FIFO_FULL 0x0004
221#define PSC_RX_FIFO_ALARM 0x0002
222#define PSC_RX_FIFO_EMPTY 0x0001
223
224/* PSC interrupt mask bits */
225#define PSC_IMR_TXRDY 0x0100
226#define PSC_IMR_RXRDY 0x0200
227#define PSC_IMR_DB 0x0400
228#define PSC_IMR_IPC 0x8000
229
230/* PSC input port change bits */
231#define PSC_IPCR_CTS 0x01
232#define PSC_IPCR_DCD 0x02
233
234/* PSC mode fields */
235#define PSC_MODE_5_BITS 0x00
236#define PSC_MODE_6_BITS 0x01
237#define PSC_MODE_7_BITS 0x02
238#define PSC_MODE_8_BITS 0x03
239#define PSC_MODE_PAREVEN 0x00
240#define PSC_MODE_PARODD 0x04
241#define PSC_MODE_PARFORCE 0x08
242#define PSC_MODE_PARNONE 0x10
243#define PSC_MODE_ERR 0x20
244#define PSC_MODE_FFULL 0x40
245#define PSC_MODE_RXRTS 0x80
246
247#define PSC_MODE_ONE_STOP_5_BITS 0x00
248#define PSC_MODE_ONE_STOP 0x07
249#define PSC_MODE_TWO_STOP 0x0f
250
251#ifndef __ASSEMBLY__
252struct mpc5xxx_psc {
253 volatile u8 mode; /* PSC + 0x00 */
254 volatile u8 reserved0[3];
255 union { /* PSC + 0x04 */
256 volatile u16 status;
257 volatile u16 clock_select;
258 } sr_csr;
259#define psc_status sr_csr.status
260#define psc_clock_select sr_csr.clock_select
261 volatile u16 reserved1;
262 volatile u8 command; /* PSC + 0x08 */
263 volatile u8 reserved2[3];
264 union { /* PSC + 0x0c */
265 volatile u8 buffer_8;
266 volatile u16 buffer_16;
267 volatile u32 buffer_32;
268 } buffer;
269#define psc_buffer_8 buffer.buffer_8
270#define psc_buffer_16 buffer.buffer_16
271#define psc_buffer_32 buffer.buffer_32
272 union { /* PSC + 0x10 */
273 volatile u8 ipcr;
274 volatile u8 acr;
275 } ipcr_acr;
276#define psc_ipcr ipcr_acr.ipcr
277#define psc_acr ipcr_acr.acr
278 volatile u8 reserved3[3];
279 union { /* PSC + 0x14 */
280 volatile u16 isr;
281 volatile u16 imr;
282 } isr_imr;
283#define psc_isr isr_imr.isr
284#define psc_imr isr_imr.imr
285 volatile u16 reserved4;
286 volatile u8 ctur; /* PSC + 0x18 */
287 volatile u8 reserved5[3];
288 volatile u8 ctlr; /* PSC + 0x1c */
289 volatile u8 reserved6[19];
290 volatile u8 ivr; /* PSC + 0x30 */
291 volatile u8 reserved7[3];
292 volatile u8 ip; /* PSC + 0x34 */
293 volatile u8 reserved8[3];
294 volatile u8 op1; /* PSC + 0x38 */
295 volatile u8 reserved9[3];
296 volatile u8 op0; /* PSC + 0x3c */
297 volatile u8 reserved10[3];
298 volatile u8 sicr; /* PSC + 0x40 */
299 volatile u8 reserved11[3];
300 volatile u8 ircr1; /* PSC + 0x44 */
301 volatile u8 reserved12[3];
302 volatile u8 ircr2; /* PSC + 0x44 */
303 volatile u8 reserved13[3];
304 volatile u8 irsdr; /* PSC + 0x4c */
305 volatile u8 reserved14[3];
306 volatile u8 irmdr; /* PSC + 0x50 */
307 volatile u8 reserved15[3];
308 volatile u8 irfdr; /* PSC + 0x54 */
309 volatile u8 reserved16[3];
310 volatile u16 rfnum; /* PSC + 0x58 */
311 volatile u16 reserved17;
312 volatile u16 tfnum; /* PSC + 0x5c */
313 volatile u16 reserved18;
314 volatile u32 rfdata; /* PSC + 0x60 */
315 volatile u16 rfstat; /* PSC + 0x64 */
316 volatile u16 reserved20;
317 volatile u8 rfcntl; /* PSC + 0x68 */
318 volatile u8 reserved21[5];
319 volatile u16 rfalarm; /* PSC + 0x6e */
320 volatile u16 reserved22;
321 volatile u16 rfrptr; /* PSC + 0x72 */
322 volatile u16 reserved23;
323 volatile u16 rfwptr; /* PSC + 0x76 */
324 volatile u16 reserved24;
325 volatile u16 rflrfptr; /* PSC + 0x7a */
326 volatile u16 reserved25;
327 volatile u16 rflwfptr; /* PSC + 0x7e */
328 volatile u32 tfdata; /* PSC + 0x80 */
329 volatile u16 tfstat; /* PSC + 0x84 */
330 volatile u16 reserved26;
331 volatile u8 tfcntl; /* PSC + 0x88 */
332 volatile u8 reserved27[5];
333 volatile u16 tfalarm; /* PSC + 0x8e */
334 volatile u16 reserved28;
335 volatile u16 tfrptr; /* PSC + 0x92 */
336 volatile u16 reserved29;
337 volatile u16 tfwptr; /* PSC + 0x96 */
338 volatile u16 reserved30;
339 volatile u16 tflrfptr; /* PSC + 0x9a */
340 volatile u16 reserved31;
341 volatile u16 tflwfptr; /* PSC + 0x9e */
342};
343
344struct mpc5xxx_intr {
345 volatile u32 per_mask; /* INTR + 0x00 */
346 volatile u32 per_pri1; /* INTR + 0x04 */
347 volatile u32 per_pri2; /* INTR + 0x08 */
348 volatile u32 per_pri3; /* INTR + 0x0c */
349 volatile u32 ctrl; /* INTR + 0x10 */
350 volatile u32 main_mask; /* INTR + 0x14 */
351 volatile u32 main_pri1; /* INTR + 0x18 */
352 volatile u32 main_pri2; /* INTR + 0x1c */
353 volatile u32 reserved1; /* INTR + 0x20 */
354 volatile u32 enc_status; /* INTR + 0x24 */
355 volatile u32 crit_status; /* INTR + 0x28 */
356 volatile u32 main_status; /* INTR + 0x2c */
357 volatile u32 per_status; /* INTR + 0x30 */
358 volatile u32 reserved2; /* INTR + 0x34 */
359 volatile u32 per_error; /* INTR + 0x38 */
360};
361
362struct mpc5xxx_gpio {
363 volatile u32 port_config; /* GPIO + 0x00 */
364 volatile u32 simple_gpioe; /* GPIO + 0x04 */
365 volatile u32 simple_ode; /* GPIO + 0x08 */
366 volatile u32 simple_ddr; /* GPIO + 0x0c */
367 volatile u32 simple_dvo; /* GPIO + 0x10 */
368 volatile u32 simple_ival; /* GPIO + 0x14 */
369 volatile u8 outo_gpioe; /* GPIO + 0x18 */
370 volatile u8 reserved1[3]; /* GPIO + 0x19 */
371 volatile u8 outo_dvo; /* GPIO + 0x1c */
372 volatile u8 reserved2[3]; /* GPIO + 0x1d */
373 volatile u8 sint_gpioe; /* GPIO + 0x20 */
374 volatile u8 reserved3[3]; /* GPIO + 0x21 */
375 volatile u8 sint_ode; /* GPIO + 0x24 */
376 volatile u8 reserved4[3]; /* GPIO + 0x25 */
377 volatile u8 sint_ddr; /* GPIO + 0x28 */
378 volatile u8 reserved5[3]; /* GPIO + 0x29 */
379 volatile u8 sint_dvo; /* GPIO + 0x2c */
380 volatile u8 reserved6[3]; /* GPIO + 0x2d */
381 volatile u8 sint_inten; /* GPIO + 0x30 */
382 volatile u8 reserved7[3]; /* GPIO + 0x31 */
383 volatile u16 sint_itype; /* GPIO + 0x34 */
384 volatile u16 reserved8; /* GPIO + 0x36 */
385 volatile u8 gpio_control; /* GPIO + 0x38 */
386 volatile u8 reserved9[3]; /* GPIO + 0x39 */
387 volatile u8 sint_istat; /* GPIO + 0x3c */
388 volatile u8 sint_ival; /* GPIO + 0x3d */
389 volatile u8 bus_errs; /* GPIO + 0x3e */
390 volatile u8 reserved10; /* GPIO + 0x3f */
391};
392
393struct mpc5xxx_sdma {
394 volatile u32 taskBar; /* SDMA + 0x00 */
395 volatile u32 currentPointer; /* SDMA + 0x04 */
396 volatile u32 endPointer; /* SDMA + 0x08 */
397 volatile u32 variablePointer; /* SDMA + 0x0c */
398
399 volatile u8 IntVect1; /* SDMA + 0x10 */
400 volatile u8 IntVect2; /* SDMA + 0x11 */
401 volatile u16 PtdCntrl; /* SDMA + 0x12 */
402
403 volatile u32 IntPend; /* SDMA + 0x14 */
404 volatile u32 IntMask; /* SDMA + 0x18 */
405
406 volatile u16 tcr_0; /* SDMA + 0x1c */
407 volatile u16 tcr_1; /* SDMA + 0x1e */
408 volatile u16 tcr_2; /* SDMA + 0x20 */
409 volatile u16 tcr_3; /* SDMA + 0x22 */
410 volatile u16 tcr_4; /* SDMA + 0x24 */
411 volatile u16 tcr_5; /* SDMA + 0x26 */
412 volatile u16 tcr_6; /* SDMA + 0x28 */
413 volatile u16 tcr_7; /* SDMA + 0x2a */
414 volatile u16 tcr_8; /* SDMA + 0x2c */
415 volatile u16 tcr_9; /* SDMA + 0x2e */
416 volatile u16 tcr_a; /* SDMA + 0x30 */
417 volatile u16 tcr_b; /* SDMA + 0x32 */
418 volatile u16 tcr_c; /* SDMA + 0x34 */
419 volatile u16 tcr_d; /* SDMA + 0x36 */
420 volatile u16 tcr_e; /* SDMA + 0x38 */
421 volatile u16 tcr_f; /* SDMA + 0x3a */
422
423 volatile u8 IPR0; /* SDMA + 0x3c */
424 volatile u8 IPR1; /* SDMA + 0x3d */
425 volatile u8 IPR2; /* SDMA + 0x3e */
426 volatile u8 IPR3; /* SDMA + 0x3f */
427 volatile u8 IPR4; /* SDMA + 0x40 */
428 volatile u8 IPR5; /* SDMA + 0x41 */
429 volatile u8 IPR6; /* SDMA + 0x42 */
430 volatile u8 IPR7; /* SDMA + 0x43 */
431 volatile u8 IPR8; /* SDMA + 0x44 */
432 volatile u8 IPR9; /* SDMA + 0x45 */
433 volatile u8 IPR10; /* SDMA + 0x46 */
434 volatile u8 IPR11; /* SDMA + 0x47 */
435 volatile u8 IPR12; /* SDMA + 0x48 */
436 volatile u8 IPR13; /* SDMA + 0x49 */
437 volatile u8 IPR14; /* SDMA + 0x4a */
438 volatile u8 IPR15; /* SDMA + 0x4b */
439 volatile u8 IPR16; /* SDMA + 0x4c */
440 volatile u8 IPR17; /* SDMA + 0x4d */
441 volatile u8 IPR18; /* SDMA + 0x4e */
442 volatile u8 IPR19; /* SDMA + 0x4f */
443 volatile u8 IPR20; /* SDMA + 0x50 */
444 volatile u8 IPR21; /* SDMA + 0x51 */
445 volatile u8 IPR22; /* SDMA + 0x52 */
446 volatile u8 IPR23; /* SDMA + 0x53 */
447 volatile u8 IPR24; /* SDMA + 0x54 */
448 volatile u8 IPR25; /* SDMA + 0x55 */
449 volatile u8 IPR26; /* SDMA + 0x56 */
450 volatile u8 IPR27; /* SDMA + 0x57 */
451 volatile u8 IPR28; /* SDMA + 0x58 */
452 volatile u8 IPR29; /* SDMA + 0x59 */
453 volatile u8 IPR30; /* SDMA + 0x5a */
454 volatile u8 IPR31; /* SDMA + 0x5b */
455
456 volatile u32 res1; /* SDMA + 0x5c */
457 volatile u32 res2; /* SDMA + 0x60 */
458 volatile u32 res3; /* SDMA + 0x64 */
459 volatile u32 MDEDebug; /* SDMA + 0x68 */
460 volatile u32 ADSDebug; /* SDMA + 0x6c */
461 volatile u32 Value1; /* SDMA + 0x70 */
462 volatile u32 Value2; /* SDMA + 0x74 */
463 volatile u32 Control; /* SDMA + 0x78 */
464 volatile u32 Status; /* SDMA + 0x7c */
465 volatile u32 EU00; /* SDMA + 0x80 */
466 volatile u32 EU01; /* SDMA + 0x84 */
467 volatile u32 EU02; /* SDMA + 0x88 */
468 volatile u32 EU03; /* SDMA + 0x8c */
469 volatile u32 EU04; /* SDMA + 0x90 */
470 volatile u32 EU05; /* SDMA + 0x94 */
471 volatile u32 EU06; /* SDMA + 0x98 */
472 volatile u32 EU07; /* SDMA + 0x9c */
473 volatile u32 EU10; /* SDMA + 0xa0 */
474 volatile u32 EU11; /* SDMA + 0xa4 */
475 volatile u32 EU12; /* SDMA + 0xa8 */
476 volatile u32 EU13; /* SDMA + 0xac */
477 volatile u32 EU14; /* SDMA + 0xb0 */
478 volatile u32 EU15; /* SDMA + 0xb4 */
479 volatile u32 EU16; /* SDMA + 0xb8 */
480 volatile u32 EU17; /* SDMA + 0xbc */
481 volatile u32 EU20; /* SDMA + 0xc0 */
482 volatile u32 EU21; /* SDMA + 0xc4 */
483 volatile u32 EU22; /* SDMA + 0xc8 */
484 volatile u32 EU23; /* SDMA + 0xcc */
485 volatile u32 EU24; /* SDMA + 0xd0 */
486 volatile u32 EU25; /* SDMA + 0xd4 */
487 volatile u32 EU26; /* SDMA + 0xd8 */
488 volatile u32 EU27; /* SDMA + 0xdc */
489 volatile u32 EU30; /* SDMA + 0xe0 */
490 volatile u32 EU31; /* SDMA + 0xe4 */
491 volatile u32 EU32; /* SDMA + 0xe8 */
492 volatile u32 EU33; /* SDMA + 0xec */
493 volatile u32 EU34; /* SDMA + 0xf0 */
494 volatile u32 EU35; /* SDMA + 0xf4 */
495 volatile u32 EU36; /* SDMA + 0xf8 */
496 volatile u32 EU37; /* SDMA + 0xfc */
497};
498
499/* function prototypes */
500void loadtask(int basetask, int tasks);
501
502#endif /* __ASSEMBLY__ */
503
504#endif /* __ASMPPC_MPC5XXX_H */