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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d9b94f28a442b0013caef99de084d7b72e2d4607 / . / cpu / mips / start.S
blob: ff105a418401c953cd817ef8b1e42eeec30c7d23 [file] [log] [blame]
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]1/*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25
26#include <config.h>
27#include <version.h>
28#include <asm/regdef.h>
29#include <asm/mipsregs.h>
30
31
32#define RVECENT(f,n) \
33 b f; nop
34#define XVECENT(f,bev) \
35 b f ; \
36 li k0,bev
37
38 .set noreorder
39
40 .globl _start
41 .text
42_start:
43 RVECENT(reset,0) /* U-boot entry point */
44 RVECENT(reset,1) /* software reboot */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]45#if defined(CONFIG_INCA_IP)
46 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
47 .word 0x00000000 /* phase of the flash */
48#elif defined(CONFIG_PURPLE)
49 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
50 .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]51#else
52 RVECENT(romReserved,2)
53#endif
54 RVECENT(romReserved,3)
55 RVECENT(romReserved,4)
56 RVECENT(romReserved,5)
57 RVECENT(romReserved,6)
58 RVECENT(romReserved,7)
59 RVECENT(romReserved,8)
60 RVECENT(romReserved,9)
61 RVECENT(romReserved,10)
62 RVECENT(romReserved,11)
63 RVECENT(romReserved,12)
64 RVECENT(romReserved,13)
65 RVECENT(romReserved,14)
66 RVECENT(romReserved,15)
67 RVECENT(romReserved,16)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]68 RVECENT(romReserved,17)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]69 RVECENT(romReserved,18)
70 RVECENT(romReserved,19)
71 RVECENT(romReserved,20)
72 RVECENT(romReserved,21)
73 RVECENT(romReserved,22)
74 RVECENT(romReserved,23)
75 RVECENT(romReserved,24)
76 RVECENT(romReserved,25)
77 RVECENT(romReserved,26)
78 RVECENT(romReserved,27)
79 RVECENT(romReserved,28)
80 RVECENT(romReserved,29)
81 RVECENT(romReserved,30)
82 RVECENT(romReserved,31)
83 RVECENT(romReserved,32)
84 RVECENT(romReserved,33)
85 RVECENT(romReserved,34)
86 RVECENT(romReserved,35)
87 RVECENT(romReserved,36)
88 RVECENT(romReserved,37)
89 RVECENT(romReserved,38)
90 RVECENT(romReserved,39)
91 RVECENT(romReserved,40)
92 RVECENT(romReserved,41)
93 RVECENT(romReserved,42)
94 RVECENT(romReserved,43)
95 RVECENT(romReserved,44)
96 RVECENT(romReserved,45)
97 RVECENT(romReserved,46)
98 RVECENT(romReserved,47)
99 RVECENT(romReserved,48)
100 RVECENT(romReserved,49)
101 RVECENT(romReserved,50)
102 RVECENT(romReserved,51)
103 RVECENT(romReserved,52)
104 RVECENT(romReserved,53)
105 RVECENT(romReserved,54)
106 RVECENT(romReserved,55)
107 RVECENT(romReserved,56)
108 RVECENT(romReserved,57)
109 RVECENT(romReserved,58)
110 RVECENT(romReserved,59)
111 RVECENT(romReserved,60)
112 RVECENT(romReserved,61)
113 RVECENT(romReserved,62)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]114 RVECENT(romReserved,63)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]115 XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
116 RVECENT(romReserved,65)
117 RVECENT(romReserved,66)
118 RVECENT(romReserved,67)
119 RVECENT(romReserved,68)
120 RVECENT(romReserved,69)
121 RVECENT(romReserved,70)
122 RVECENT(romReserved,71)
123 RVECENT(romReserved,72)
124 RVECENT(romReserved,73)
125 RVECENT(romReserved,74)
126 RVECENT(romReserved,75)
127 RVECENT(romReserved,76)
128 RVECENT(romReserved,77)
129 RVECENT(romReserved,78)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]130 RVECENT(romReserved,79)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]131 XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
132 RVECENT(romReserved,81)
133 RVECENT(romReserved,82)
134 RVECENT(romReserved,83)
135 RVECENT(romReserved,84)
136 RVECENT(romReserved,85)
137 RVECENT(romReserved,86)
138 RVECENT(romReserved,87)
139 RVECENT(romReserved,88)
140 RVECENT(romReserved,89)
141 RVECENT(romReserved,90)
142 RVECENT(romReserved,91)
143 RVECENT(romReserved,92)
144 RVECENT(romReserved,93)
145 RVECENT(romReserved,94)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]146 RVECENT(romReserved,95)
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]147 XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
148 RVECENT(romReserved,97)
149 RVECENT(romReserved,98)
150 RVECENT(romReserved,99)
151 RVECENT(romReserved,100)
152 RVECENT(romReserved,101)
153 RVECENT(romReserved,102)
154 RVECENT(romReserved,103)
155 RVECENT(romReserved,104)
156 RVECENT(romReserved,105)
157 RVECENT(romReserved,106)
158 RVECENT(romReserved,107)
159 RVECENT(romReserved,108)
160 RVECENT(romReserved,109)
161 RVECENT(romReserved,110)
162 RVECENT(romReserved,111)
163 XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
164 RVECENT(romReserved,113)
165 RVECENT(romReserved,114)
166 RVECENT(romReserved,115)
167 RVECENT(romReserved,116)
168 RVECENT(romReserved,116)
169 RVECENT(romReserved,118)
170 RVECENT(romReserved,119)
171 RVECENT(romReserved,120)
172 RVECENT(romReserved,121)
173 RVECENT(romReserved,122)
174 RVECENT(romReserved,123)
175 RVECENT(romReserved,124)
176 RVECENT(romReserved,125)
177 RVECENT(romReserved,126)
178 RVECENT(romReserved,127)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]179
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]180 /* We hope there are no more reserved vectors!
181 * 128 * 8 == 1024 == 0x400
182 * so this is address R_VEC+0x400 == 0xbfc00400
183 */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]184#ifdef CONFIG_PURPLE
185/* 0xbfc00400 */
186 .word 0xdc870000
187 .word 0xfca70000
188 .word 0x20840008
189 .word 0x20a50008
190 .word 0x20c6ffff
191 .word 0x14c0fffa
192 .word 0x00000000
193 .word 0x03e00008
194 .word 0x00000000
195 .word 0x00000000
196/* 0xbfc00428 */
197 .word 0xdc870000
198 .word 0xfca70000
199 .word 0x20840008
200 .word 0x20a50008
201 .word 0x20c6ffff
202 .word 0x14c0fffa
203 .word 0x00000000
204 .word 0x03e00008
205 .word 0x00000000
206 .word 0x00000000
207#endif /* CONFIG_PURPLE */
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]208 .align 4
209reset:
210
211 /* Clear watch registers.
212 */
213 mtc0 zero, CP0_WATCHLO
214 mtc0 zero, CP0_WATCHHI
215
216 /* STATUS register */
wdenkf4863a72004-02-07 01:27:10 +0000[diff] [blame]217#ifdef CONFIG_TB0229
218 li k0, ST0_CU0
219#else
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]220 mfc0 k0, CP0_STATUS
wdenkf4863a72004-02-07 01:27:10 +0000[diff] [blame]221#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]222 li k1, ~ST0_IE
223 and k0, k1
224 mtc0 k0, CP0_STATUS
225
226 /* CAUSE register */
227 mtc0 zero, CP0_CAUSE
228
229 /* Init Timer */
230 mtc0 zero, CP0_COUNT
231 mtc0 zero, CP0_COMPARE
232
233 /* CONFIG0 register */
234 li t0, CONF_CM_UNCACHED
235 mtc0 t0, CP0_CONFIG
236
237#ifdef CONFIG_INCA_IP
238 /* Disable INCA-IP Watchdog.
239 */
240 bal disable_incaip_wdt
241 nop
242#endif
243
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]244 /* Initialize any external memory.
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]245 */
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]246 bal lowlevel_init
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]247 nop
248
249 /* Initialize caches...
250 */
251 bal mips_cache_reset
252 nop
253
254 /* ... and enable them.
255 */
256 li t0, CONF_CM_CACHABLE_NONCOHERENT
257 mtc0 t0, CP0_CONFIG
258
259
260 /* Set up temporary stack.
261 */
262 li a0, CFG_INIT_SP_OFFSET
263 bal mips_cache_lock
264 nop
265
266 li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
267 la sp, 0(t0)
268
269 /* Initialize GOT pointer.
270 */
271 bal 1f
272 nop
273 .word _GLOBAL_OFFSET_TABLE_ - 1f + 4
2741:
275 move gp, ra
276 lw t1, 0(ra)
277 add gp, t1
278 la t9, board_init_f
279 j t9
280 nop
281
282
283/*
284 * void relocate_code (addr_sp, gd, addr_moni)
285 *
286 * This "function" does not return, instead it continues in RAM
287 * after relocating the monitor code.
288 *
289 * a0 = addr_sp
290 * a1 = gd
291 * a2 = destination address
292 */
293 .globl relocate_code
294 .ent relocate_code
295relocate_code:
296 move sp, a0 /* Set new stack pointer */
297
wdenk27b207f2003-07-24 23:38:38 +0000[diff] [blame]298 li t0, CFG_MONITOR_BASE
299 la t3, in_ram
300 lw t2, -12(t3) /* t2 <-- uboot_end_data */
301 move t1, a2
302
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]303 /*
304 * Fix GOT pointer:
305 *
306 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
307 */
308 move t6, gp
309 sub gp, CFG_MONITOR_BASE
310 add gp, a2 /* gp now adjusted */
311 sub t6, gp, t6 /* t6 <-- relocation offset */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]312
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]313 /*
314 * t0 = source address
315 * t1 = target address
316 * t2 = source end address
317 */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]318 /* On the purple board we copy the code earlier in a special way
319 * in order to solve flash problems
320 */
321#ifndef CONFIG_PURPLE
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]3221:
323 lw t3, 0(t0)
324 sw t3, 0(t1)
325 addu t0, 4
326 ble t0, t2, 1b
327 addu t1, 4 /* delay slot */
wdenk3e386912003-04-05 00:53:31 +0000[diff] [blame]328#endif
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]329
330 /* If caches were enabled, we would have to flush them here.
331 */
332
333 /* Jump to where we've relocated ourselves.
334 */
335 addi t0, a2, in_ram - _start
336 j t0
337 nop
338
339 .word uboot_end_data
340 .word uboot_end
341 .word num_got_entries
342
343in_ram:
344 /* Now we want to update GOT.
345 */
346 lw t3, -4(t0) /* t3 <-- num_got_entries */
347 addi t4, gp, 8 /* Skipping first two entries. */
348 li t2, 2
3491:
350 lw t1, 0(t4)
351 beqz t1, 2f
352 add t1, t6
353 sw t1, 0(t4)
3542:
355 addi t2, 1
356 blt t2, t3, 1b
357 addi t4, 4 /* delay slot */
358
359 /* Clear BSS.
360 */
361 lw t1, -12(t0) /* t1 <-- uboot_end_data */
362 lw t2, -8(t0) /* t2 <-- uboot_end */
363 add t1, t6 /* adjust pointers */
364 add t2, t6
365
366 sub t1, 4
3671: addi t1, 4
368 bltl t1, t2, 1b
369 sw zero, 0(t1) /* delay slot */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]370
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]371 move a0, a1
372 la t9, board_init_r
373 j t9
374 move a1, a2 /* delay slot */
375
376 .end relocate_code
wdenkc0218802003-03-27 12:09:35 +0000[diff] [blame]377
378
379 /* Exception handlers.
380 */
381romReserved:
382 b romReserved
383
384romExcHandle:
385 b romExcHandle