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Macpaul Linf8ef0d42011-07-20 21:29:58 +00001/*
2 * Faraday FTSDC010 Secure Digital Memory Card Host Controller
3 *
4 * Copyright (C) 2011 Andes Technology Corporation
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Macpaul Linf8ef0d42011-07-20 21:29:58 +00008 */
9
10#ifndef __FTSDC010_H
11#define __FTSDC010_H
12
13#ifndef __ASSEMBLY__
Kuo-Jung Suf6c3b342013-05-06 20:32:51 +000014
Macpaul Linf8ef0d42011-07-20 21:29:58 +000015/* sd controller register */
16struct ftsdc010_mmc {
17 unsigned int cmd; /* 0x00 - command reg */
18 unsigned int argu; /* 0x04 - argument reg */
19 unsigned int rsp0; /* 0x08 - response reg0 */
20 unsigned int rsp1; /* 0x0c - response reg1 */
21 unsigned int rsp2; /* 0x10 - response reg2 */
22 unsigned int rsp3; /* 0x14 - response reg3 */
23 unsigned int rsp_cmd; /* 0x18 - responded cmd reg */
24 unsigned int dcr; /* 0x1c - data control reg */
25 unsigned int dtr; /* 0x20 - data timer reg */
26 unsigned int dlr; /* 0x24 - data length reg */
27 unsigned int status; /* 0x28 - status reg */
28 unsigned int clr; /* 0x2c - clear reg */
29 unsigned int int_mask; /* 0x30 - intrrupt mask reg */
30 unsigned int pcr; /* 0x34 - power control reg */
31 unsigned int ccr; /* 0x38 - clock contorl reg */
32 unsigned int bwr; /* 0x3c - bus width reg */
33 unsigned int dwr; /* 0x40 - data window reg */
34#ifndef CONFIG_FTSDC010_SDIO
35 unsigned int feature; /* 0x44 - feature reg */
36 unsigned int rev; /* 0x48 - revision reg */
37#else
38 unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */
39 unsigned int gpo; /* 0x48 - gerenal purpose output */
40 unsigned int reserved[8]; /* 0x50 - 0x68 reserved */
41 unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */
42 unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */
43 unsigned int sdio_status; /* 0x74 - SDIO status regi */
44 unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */
45 unsigned int feature; /* 0x9c - feature reg */
46 unsigned int rev; /* 0xa0 - revision reg */
47#endif /* CONFIG_FTSDC010_SDIO */
48};
49
50struct mmc_host {
51 struct ftsdc010_mmc *reg;
52 unsigned int version; /* SDHCI spec. version */
53 unsigned int clock; /* Current clock (MHz) */
54 unsigned int fifo_len; /* bytes */
55 unsigned int last_opcode; /* Last OP Code */
56 unsigned int card_type; /* Card type */
57};
58
59/* functions */
60int ftsdc010_mmc_init(int dev_index);
61
62#endif /* __ASSEMBLY__ */
63
64/* global defines */
65#define FTSDC010_CMD_RETRY 0x100000
66#define FTSDC010_PIO_RETRY 100 /* pio retry times */
67#define FTSDC010_DELAY_UNIT 100 /* 100 us */
68
69/* define from Linux kernel - include/linux/mmc/card.h */
70#define MMC_TYPE_SDIO 2 /* SDIO card */
71
72/* define for mmc layer */
73#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
74
75/* this part is strange */
76#define FTSDC010_SDIO_CTRL1_REG 0x0000006C
77#define FTSDC010_SDIO_CTRL2_REG 0x0000006C
78#define FTSDC010_SDIO_STATUS_REG 0x00000070
79
80/* 0x00 - command register */
81#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0)
82#define FTSDC010_CMD_NEED_RSP (1 << 6)
83#define FTSDC010_CMD_LONG_RSP (1 << 7)
84#define FTSDC010_CMD_APP_CMD (1 << 8)
85#define FTSDC010_CMD_CMD_EN (1 << 9)
86#define FTSDC010_CMD_SDC_RST (1 << 10)
87#define FTSDC010_CMD_MMC_INT_STOP (1 << 11)
88
89/* 0x18 - responded command register */
90#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f)
91#define FTSDC010_RSP_CMD_APP (1 << 6)
92
93/* 0x1c - data control register */
94#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0)
95#define FTSDC010_DCR_DATA_WRITE (1 << 4)
96#define FTSDC010_DCR_DMA_EN (1 << 5)
97#define FTSDC010_DCR_DATA_EN (1 << 6)
98#ifdef CONFIG_FTSDC010_SDIO
99#define FTSDC010_DCR_FIFOTH (1 << 7)
100#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8)
101#define FTSDC010_DCR_FIFO_RST (1 << 10)
102#endif /* CONFIG_FTSDC010_SDIO */
103
104#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */
105#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */
106#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */
107
108#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */
109
110/* CPRM related define */
111#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008
112#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010
113
114/* 0x28 - status register */
115#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0)
116#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1)
117#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2)
118#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3)
119#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4)
120#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5)
121#define FTSDC010_STATUS_CMD_SEND (1 << 6)
122#define FTSDC010_STATUS_DATA_END (1 << 7)
123#define FTSDC010_STATUS_FIFO_URUN (1 << 8)
124#define FTSDC010_STATUS_FIFO_ORUN (1 << 9)
125#define FTSDC010_STATUS_CARD_CHANGE (1 << 10)
126#define FTSDC010_STATUS_CARD_DETECT (1 << 11)
127#define FTSDC010_STATUS_WRITE_PROT (1 << 12)
128#ifdef CONFIG_FTSDC010_SDIO
129#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */
130#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */
131#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */
132#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */
133#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
134#endif /* CONFIG_FTSDC010_SDIO */
Kuo-Jung Suf6c3b342013-05-06 20:32:51 +0000135#define FTSDC010_STATUS_RSP_ERROR \
136 (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
137#define FTSDC010_STATUS_RSP_MASK \
138 (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
139#define FTSDC010_STATUS_DATA_ERROR \
140 (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
141#define FTSDC010_STATUS_DATA_MASK \
142 (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
143 | FTSDC010_STATUS_DATA_END)
Macpaul Linf8ef0d42011-07-20 21:29:58 +0000144
145/* 0x2c - clear register */
146#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0)
147#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1)
148#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2)
149#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3)
150#define FTSDC010_CLR_RSP_CRC_OK (1 << 4)
151#define FTSDC010_CLR_DATA_CRC_OK (1 << 5)
152#define FTSDC010_CLR_CMD_SEND (1 << 6)
153#define FTSDC010_CLR_DATA_END (1 << 7)
154#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */
155#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */
156#define FTSDC010_CLR_CARD_CHANGE (1 << 10)
157#ifdef CONFIG_FTSDC010_SDIO
158#define FTSDC010_CLR_SDIO_IRPT (1 << 16)
159#endif /* CONFIG_FTSDC010_SDIO */
160
161/* 0x30 - interrupt mask register */
162#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0)
163#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1)
164#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2)
165#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3)
166#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4)
167#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5)
168#define FTSDC010_INT_MASK_CMD_SEND (1 << 6)
169#define FTSDC010_INT_MASK_DATA_END (1 << 7)
170#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8)
171#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9)
172#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10)
173#ifdef CONFIG_FTSDC010_SDIO
174#define FTSDC010_INT_MASK_CP_READY (1 << 13)
175#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14)
176#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15)
177#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16)
178#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
179#endif /* CONFIG_FTSDC010_SDIO */
180
181/* ? */
182#define FTSDC010_CARD_INSERT 0x0
183#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT
184
185/* 0x34 - power control register */
186#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0)
187#define FTSDC010_PCR_POWER_ON (1 << 4)
188
189/* 0x38 - clock control register */
190#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0)
191#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */
192#define FTSDC010_CCR_CLK_DIS (1 << 8)
Kuo-Jung Suf6c3b342013-05-06 20:32:51 +0000193#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */
Macpaul Linf8ef0d42011-07-20 21:29:58 +0000194
195/* card type */
196#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE
197#define FTSDC010_CARD_TYPE_MMC 0x0
198
199/* 0x3c - bus width register */
Kuo-Jung Suf6c3b342013-05-06 20:32:51 +0000200#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */
201#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */
202#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */
203#define FTSDC010_BWR_MODE_MASK (7 << 0)
204#define FTSDC010_BWR_MODE_SHIFT (0)
205#define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */
206#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */
207#define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */
208#define FTSDC010_BWR_CAPS_MASK (3 << 3)
209#define FTSDC010_BWR_CAPS_SHIFT (3)
210#define FTSDC010_BWR_CARD_DETECT (1 << 5)
Macpaul Linf8ef0d42011-07-20 21:29:58 +0000211
212/* 0x44 or 0x9c - feature register */
213#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff)
214#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8)
215
216#define FTSDC010_FIFO_DEPTH_4 0x04
217#define FTSDC010_FIFO_DEPTH_8 0x08
218#define FTSDC010_FIFO_DEPTH_16 0x10
219
220/* 0x48 or 0xa0 - revision register */
221#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0)
222#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8)
223#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16)
224
225#ifdef CONFIG_FTSDC010_SDIO
226/* 0x44 - general purpose output */
227#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0)
228
229/* 0x6c - sdio control register 1 */
230#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0)
231#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12)
232#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13)
233#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14)
234#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15)
235
236/* 0x70 - sdio control register 2 */
237#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0)
238#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1)
239
240/* 0x74 - sdio status register */
241#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff)
242#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef)
243
244#endif /* CONFIG_FTSDC010_SDIO */
245
246#endif /* __FTSDC010_H */