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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
Jon Loeligerbaa26db2007-07-08 17:51:39 -050030#if defined(CONFIG_CMD_NET)
wdenk4a9cbbe2002-08-27 09:48:53 +000031#include <net.h>
32#endif
wdenk8bde7f72003-06-27 21:31:46 +000033#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000034#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36#if 0
37#define FPGA_DEBUG
38#endif
39
40#ifdef FPGA_DEBUG
41#define PRINTF(fmt,args...) printf (fmt ,##args)
42#else
43#define PRINTF(fmt,args...)
44#endif
45
wdenk4a9cbbe2002-08-27 09:48:53 +000046/* Local functions */
wdenkd4ca31c2004-01-02 14:00:00 +000047static int fpga_get_op (char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000048
49/* Local defines */
50#define FPGA_NONE -1
51#define FPGA_INFO 0
52#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000053#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000054#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020055#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000056
wdenk30ce5ab2005-01-09 18:12:51 +000057/* Convert bitstream data and load into the fpga */
58int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
59{
Matthias Fuchs01335022007-12-27 17:12:34 +010060#if defined(CONFIG_FPGA_XILINX)
Wolfgang Denk8b019da2005-08-08 00:14:41 +020061 unsigned int length;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020062 unsigned int swapsize;
wdenk30ce5ab2005-01-09 18:12:51 +000063 char buffer[80];
Wolfgang Denk8b019da2005-08-08 00:14:41 +020064 unsigned char *dataptr;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020065 unsigned int i;
wdenk30ce5ab2005-01-09 18:12:51 +000066 int rc;
67
Wolfgang Denk77ddac92005-10-13 16:45:02 +020068 dataptr = (unsigned char *)fpgadata;
wdenk30ce5ab2005-01-09 18:12:51 +000069
Wolfgang Denk8b019da2005-08-08 00:14:41 +020070 /* skip the first bytes of the bitsteam, their meaning is unknown */
71 length = (*dataptr << 8) + *(dataptr+1);
72 dataptr+=2;
73 dataptr+=length;
wdenk30ce5ab2005-01-09 18:12:51 +000074
75 /* get design name (identifier, length, string) */
Wolfgang Denk8b019da2005-08-08 00:14:41 +020076 length = (*dataptr << 8) + *(dataptr+1);
77 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +000078 if (*dataptr++ != 0x61) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020079 PRINTF ("%s: Design name identifier not recognized in bitstream\n",
80 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000081 return FPGA_FAIL;
82 }
83
wdenka562e1b2005-01-09 18:21:42 +000084 length = (*dataptr << 8) + *(dataptr+1);
wdenk30ce5ab2005-01-09 18:12:51 +000085 dataptr+=2;
86 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +020087 buffer[i] = *dataptr++;
wdenka562e1b2005-01-09 18:21:42 +000088
Wolfgang Denk8b019da2005-08-08 00:14:41 +020089 printf(" design filename = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +000090
91 /* get part number (identifier, length, string) */
92 if (*dataptr++ != 0x62) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020093 printf("%s: Part number identifier not recognized in bitstream\n",
94 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000095 return FPGA_FAIL;
96 }
wdenka562e1b2005-01-09 18:21:42 +000097
Wolfgang Denk8b019da2005-08-08 00:14:41 +020098 length = (*dataptr << 8) + *(dataptr+1);
99 dataptr+=2;
wdenka562e1b2005-01-09 18:21:42 +0000100 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200101 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200102 printf(" part number = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000103
wdenk30ce5ab2005-01-09 18:12:51 +0000104 /* get date (identifier, length, string) */
105 if (*dataptr++ != 0x63) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200106 printf("%s: Date identifier not recognized in bitstream\n",
107 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000108 return FPGA_FAIL;
109 }
wdenka562e1b2005-01-09 18:21:42 +0000110
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200111 length = (*dataptr << 8) + *(dataptr+1);
112 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000113 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200114 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200115 printf(" date = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +0000116
117 /* get time (identifier, length, string) */
118 if (*dataptr++ != 0x64) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200119 printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000120 return FPGA_FAIL;
121 }
wdenka562e1b2005-01-09 18:21:42 +0000122
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200123 length = (*dataptr << 8) + *(dataptr+1);
124 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000125 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200126 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200127 printf(" time = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000128
wdenk30ce5ab2005-01-09 18:12:51 +0000129 /* get fpga data length (identifier, length) */
130 if (*dataptr++ != 0x65) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200131 printf("%s: Data length identifier not recognized in bitstream\n",
132 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000133 return FPGA_FAIL;
134 }
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200135 swapsize = ((unsigned int) *dataptr <<24) +
136 ((unsigned int) *(dataptr+1) <<16) +
137 ((unsigned int) *(dataptr+2) <<8 ) +
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200138 ((unsigned int) *(dataptr+3) ) ;
wdenk30ce5ab2005-01-09 18:12:51 +0000139 dataptr+=4;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200140 printf(" bytes in bitstream = %d\n", swapsize);
wdenka562e1b2005-01-09 18:21:42 +0000141
Matthias Fuchsc26acc12007-12-27 17:13:11 +0100142 rc = fpga_load(dev, dataptr, swapsize);
wdenk30ce5ab2005-01-09 18:12:51 +0000143 return rc;
144#else
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200145 printf("Bitstream support only for Xilinx devices\n");
wdenk30ce5ab2005-01-09 18:12:51 +0000146 return FPGA_FAIL;
147#endif
148}
149
wdenk4a9cbbe2002-08-27 09:48:53 +0000150/* ------------------------------------------------------------------------- */
151/* command form:
152 * fpga <op> <device number> <data addr> <datasize>
153 * where op is 'load', 'dump', or 'info'
154 * If there is no device number field, the fpga environment variable is used.
155 * If there is no data addr field, the fpgadata environment variable is used.
156 * The info command requires no data address field.
157 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200158int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000159{
wdenkd4ca31c2004-01-02 14:00:00 +0000160 int op, dev = FPGA_INVALID_DEVICE;
161 size_t data_size = 0;
162 void *fpga_data = NULL;
163 char *devstr = getenv ("fpga");
164 char *datastr = getenv ("fpgadata");
165 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +0200166 int wrong_parms = 0;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100167#if defined (CONFIG_FIT)
168 const char *fit_uname = NULL;
169 ulong fit_addr;
170#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000171
wdenkd4ca31c2004-01-02 14:00:00 +0000172 if (devstr)
173 dev = (int) simple_strtoul (devstr, NULL, 16);
174 if (datastr)
175 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000176
wdenkd4ca31c2004-01-02 14:00:00 +0000177 switch (argc) {
178 case 5: /* fpga <op> <dev> <data> <datasize> */
179 data_size = simple_strtoul (argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100180
wdenkd4ca31c2004-01-02 14:00:00 +0000181 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100182#if defined(CONFIG_FIT)
183 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
184 &fit_addr, &fit_uname)) {
185 fpga_data = (void *)fit_addr;
186 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
187 fit_uname, fit_addr);
188 } else
189#endif
190 {
191 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
192 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
193 }
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200194 PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100195
wdenkd4ca31c2004-01-02 14:00:00 +0000196 case 3: /* fpga <op> <dev | data addr> */
197 dev = (int) simple_strtoul (argv[2], NULL, 16);
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200198 PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000199 /* FIXME - this is a really weak test */
200 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200201 PRINTF ("%s: Assuming buffer pointer in arg 3\n",
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200202 __FUNCTION__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100203
204#if defined(CONFIG_FIT)
205 if (fit_parse_subimage (argv[2], (ulong)fpga_data,
206 &fit_addr, &fit_uname)) {
207 fpga_data = (void *)fit_addr;
208 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
209 fit_uname, fit_addr);
210 } else
211#endif
212 {
213 fpga_data = (void *) dev;
214 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
215 }
216
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200217 PRINTF ("%s: fpga_data = 0x%x\n",
218 __FUNCTION__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000219 dev = FPGA_INVALID_DEVICE; /* reset device num */
220 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100221
wdenkd4ca31c2004-01-02 14:00:00 +0000222 case 2: /* fpga <op> */
223 op = (int) fpga_get_op (argv[1]);
224 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100225
wdenkd4ca31c2004-01-02 14:00:00 +0000226 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200227 PRINTF ("%s: Too many or too few args (%d)\n",
228 __FUNCTION__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000229 op = FPGA_NONE; /* force usage display */
230 break;
231 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000232
Stefano Babica790b5b2010-10-19 09:22:52 +0200233 if (dev == FPGA_INVALID_DEVICE) {
234 puts("FPGA device not specified\n");
235 op = FPGA_NONE;
236 }
237
238 switch (op) {
239 case FPGA_NONE:
240 case FPGA_INFO:
241 break;
242 case FPGA_LOAD:
243 case FPGA_LOADB:
244 case FPGA_DUMP:
245 if (!fpga_data || !data_size)
246 wrong_parms = 1;
247 break;
248 case FPGA_LOADMK:
249 if (!fpga_data)
250 wrong_parms = 1;
251 break;
252 }
253
254 if (wrong_parms) {
255 puts("Wrong parameters for FPGA request\n");
256 op = FPGA_NONE;
257 }
258
wdenkd4ca31c2004-01-02 14:00:00 +0000259 switch (op) {
260 case FPGA_NONE:
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200261 return cmd_usage(cmdtp);
wdenk4a9cbbe2002-08-27 09:48:53 +0000262
wdenkd4ca31c2004-01-02 14:00:00 +0000263 case FPGA_INFO:
264 rc = fpga_info (dev);
265 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000266
wdenkd4ca31c2004-01-02 14:00:00 +0000267 case FPGA_LOAD:
268 rc = fpga_load (dev, fpga_data, data_size);
269 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000270
wdenk30ce5ab2005-01-09 18:12:51 +0000271 case FPGA_LOADB:
272 rc = fpga_loadbitstream(dev, fpga_data, data_size);
273 break;
274
Stefan Roesef0ff4692006-08-15 14:15:51 +0200275 case FPGA_LOADMK:
Marian Balakowicz9a4daad2008-02-29 14:58:34 +0100276 switch (genimg_get_format (fpga_data)) {
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100277 case IMAGE_FORMAT_LEGACY:
278 {
279 image_header_t *hdr = (image_header_t *)fpga_data;
280 ulong data;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200281
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100282 data = (ulong)image_get_data (hdr);
283 data_size = image_get_data_size (hdr);
284 rc = fpga_load (dev, (void *)data, data_size);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200285 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100286 break;
287#if defined(CONFIG_FIT)
288 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100289 {
290 const void *fit_hdr = (const void *)fpga_data;
291 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000292 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100293
294 if (fit_uname == NULL) {
295 puts ("No FIT subimage unit name\n");
296 return 1;
297 }
298
299 if (!fit_check_format (fit_hdr)) {
300 puts ("Bad FIT image format\n");
301 return 1;
302 }
303
304 /* get fpga component image node offset */
305 noffset = fit_image_get_node (fit_hdr, fit_uname);
306 if (noffset < 0) {
307 printf ("Can't find '%s' FIT subimage\n", fit_uname);
308 return 1;
309 }
310
311 /* verify integrity */
312 if (!fit_image_check_hashes (fit_hdr, noffset)) {
313 puts ("Bad Data Hash\n");
314 return 1;
315 }
316
317 /* get fpga subimage data address and length */
318 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
319 puts ("Could not find fpga subimage data\n");
320 return 1;
321 }
322
323 rc = fpga_load (dev, fit_data, data_size);
324 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100325 break;
326#endif
327 default:
328 puts ("** Unknown image type\n");
329 rc = FPGA_FAIL;
330 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200331 }
332 break;
333
wdenkd4ca31c2004-01-02 14:00:00 +0000334 case FPGA_DUMP:
335 rc = fpga_dump (dev, fpga_data, data_size);
336 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000337
wdenkd4ca31c2004-01-02 14:00:00 +0000338 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200339 printf ("Unknown operation\n");
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200340 return cmd_usage(cmdtp);
wdenkd4ca31c2004-01-02 14:00:00 +0000341 }
342 return (rc);
wdenk4a9cbbe2002-08-27 09:48:53 +0000343}
344
wdenk4a9cbbe2002-08-27 09:48:53 +0000345/*
346 * Map op to supported operations. We don't use a table since we
347 * would just have to relocate it from flash anyway.
348 */
wdenkd4ca31c2004-01-02 14:00:00 +0000349static int fpga_get_op (char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000350{
351 int op = FPGA_NONE;
352
353 if (!strcmp ("info", opstr)) {
354 op = FPGA_INFO;
wdenk30ce5ab2005-01-09 18:12:51 +0000355 } else if (!strcmp ("loadb", opstr)) {
356 op = FPGA_LOADB;
wdenkd4ca31c2004-01-02 14:00:00 +0000357 } else if (!strcmp ("load", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000358 op = FPGA_LOAD;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200359 } else if (!strcmp ("loadmk", opstr)) {
360 op = FPGA_LOADMK;
wdenkd4ca31c2004-01-02 14:00:00 +0000361 } else if (!strcmp ("dump", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000362 op = FPGA_DUMP;
363 }
364
wdenkd4ca31c2004-01-02 14:00:00 +0000365 if (op == FPGA_NONE) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000366 printf ("Unknown fpga operation \"%s\"\n", opstr);
367 }
368 return op;
369}
370
wdenkd4ca31c2004-01-02 14:00:00 +0000371U_BOOT_CMD (fpga, 6, 1, do_fpga,
Stefano Babica790b5b2010-10-19 09:22:52 +0200372 "loadable FPGA image support",
373 "[operation type] [device number] [image address] [image size]\n"
374 "fpga operations:\n"
375 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
376 " info\t[dev]\t\t\tlist known device information\n"
377 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
378 " loadb\t[dev] [address] [size]\t"
379 "Load device from bitstream buffer (Xilinx only)\n"
380 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100381#if defined(CONFIG_FIT)
Stefano Babica790b5b2010-10-19 09:22:52 +0200382 "\n"
383 "\tFor loadmk operating on FIT format uImage address must include\n"
384 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100385#endif
386);