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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Dave Liu03051c32007-09-18 12:36:11 +08005 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050024 */
25
26#include <common.h>
27#include <mpc83xx.h>
Kim Phillips54b2d432007-04-30 15:26:21 -050028#include <command.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050029#include <asm/processor.h>
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
32
Eran Libertyf046ccd2005-07-28 10:08:46 -050033/* ----------------------------------------------------------------- */
34
35typedef enum {
36 _unk,
37 _off,
38 _byp,
39 _x8,
40 _x4,
41 _x2,
42 _x1,
43 _1x,
44 _1_5x,
45 _2x,
46 _2_5x,
47 _3x
48} mult_t;
49
50typedef struct {
51 mult_t core_csb_ratio;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060052 mult_t vco_divider;
Eran Libertyf046ccd2005-07-28 10:08:46 -050053} corecnf_t;
54
Kim Phillipsa2873bd2012-10-29 13:34:39 +000055static corecnf_t corecnf_tab[] = {
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060056 {_byp, _byp}, /* 0x00 */
57 {_byp, _byp}, /* 0x01 */
58 {_byp, _byp}, /* 0x02 */
59 {_byp, _byp}, /* 0x03 */
60 {_byp, _byp}, /* 0x04 */
61 {_byp, _byp}, /* 0x05 */
62 {_byp, _byp}, /* 0x06 */
63 {_byp, _byp}, /* 0x07 */
64 {_1x, _x2}, /* 0x08 */
65 {_1x, _x4}, /* 0x09 */
66 {_1x, _x8}, /* 0x0A */
67 {_1x, _x8}, /* 0x0B */
68 {_1_5x, _x2}, /* 0x0C */
69 {_1_5x, _x4}, /* 0x0D */
70 {_1_5x, _x8}, /* 0x0E */
71 {_1_5x, _x8}, /* 0x0F */
72 {_2x, _x2}, /* 0x10 */
73 {_2x, _x4}, /* 0x11 */
74 {_2x, _x8}, /* 0x12 */
75 {_2x, _x8}, /* 0x13 */
76 {_2_5x, _x2}, /* 0x14 */
77 {_2_5x, _x4}, /* 0x15 */
78 {_2_5x, _x8}, /* 0x16 */
79 {_2_5x, _x8}, /* 0x17 */
80 {_3x, _x2}, /* 0x18 */
81 {_3x, _x4}, /* 0x19 */
82 {_3x, _x8}, /* 0x1A */
83 {_3x, _x8}, /* 0x1B */
Eran Libertyf046ccd2005-07-28 10:08:46 -050084};
85
86/* ----------------------------------------------------------------- */
87
88/*
89 *
90 */
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060091int get_clocks(void)
Eran Libertyf046ccd2005-07-28 10:08:46 -050092{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Eran Libertyf046ccd2005-07-28 10:08:46 -050094 u32 pci_sync_in;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060095 u8 spmf;
96 u8 clkin_div;
Eran Libertyf046ccd2005-07-28 10:08:46 -050097 u32 sccr;
98 u32 corecnf_tab_index;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -060099 u8 corepll;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500100 u32 lcrr;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500101
Eran Libertyf046ccd2005-07-28 10:08:46 -0500102 u32 csb_clk;
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400103#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500105 u32 tsec1_clk;
106 u32 tsec2_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500107 u32 usbdr_clk;
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000108#elif defined(CONFIG_MPC8309)
109 u32 usbdr_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600110#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500111#ifdef CONFIG_MPC834x
Scott Wood7c98e512007-04-16 14:34:19 -0500112 u32 usbmph_clk;
113#endif
Dave Liu5f820432006-11-03 19:33:44 -0600114 u32 core_clk;
115 u32 i2c1_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -0500116#if !defined(CONFIG_MPC832x)
Dave Liu5f820432006-11-03 19:33:44 -0600117 u32 i2c2_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800118#endif
Dave Liu555da612007-09-18 12:36:58 +0800119#if defined(CONFIG_MPC8315)
120 u32 tdm_clk;
121#endif
Rini van Zetten27ef5782010-04-15 16:03:05 +0200122#if defined(CONFIG_FSL_ESDHC)
Dave Liu03051c32007-09-18 12:36:11 +0800123 u32 sdhc_clk;
124#endif
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000125#if !defined(CONFIG_MPC8309)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500126 u32 enc_clk;
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000127#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500128 u32 lbiu_clk;
129 u32 lclk_clk;
Kim Phillips35cf1552008-03-28 10:18:40 -0500130 u32 mem_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800131#if defined(CONFIG_MPC8360)
Kim Phillips35cf1552008-03-28 10:18:40 -0500132 u32 mem_sec_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800133#endif
Gerlando Falauto4b5282d2012-10-10 22:13:06 +0000134#if defined(CONFIG_QE)
Dave Liu5f820432006-11-03 19:33:44 -0600135 u32 qepmf;
136 u32 qepdf;
Dave Liu5f820432006-11-03 19:33:44 -0600137 u32 qe_clk;
138 u32 brg_clk;
139#endif
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400140#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
141 defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800142 u32 pciexp1_clk;
143 u32 pciexp2_clk;
Dave Liu555da612007-09-18 12:36:58 +0800144#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500145#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Dave Liu03051c32007-09-18 12:36:11 +0800146 u32 sata_clk;
147#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500148
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600149 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500150 return -1;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500151
Eran Libertyf046ccd2005-07-28 10:08:46 -0500152 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500153
Dave Liu5f820432006-11-03 19:33:44 -0600154 if (im->reset.rcwh & HRCWH_PCI_HOST) {
155#if defined(CONFIG_83XX_CLKIN)
156 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
157#else
158 pci_sync_in = 0xDEADBEEF;
159#endif
160 } else {
161#if defined(CONFIG_83XX_PCICLK)
162 pci_sync_in = CONFIG_83XX_PCICLK;
163#else
164 pci_sync_in = 0xDEADBEEF;
165#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500166 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500167
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100168 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
Dave Liu5f820432006-11-03 19:33:44 -0600169 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
170
Eran Libertyf046ccd2005-07-28 10:08:46 -0500171 sccr = im->clk.sccr;
Dave Liu5f820432006-11-03 19:33:44 -0600172
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400173#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
174 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500175 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
176 case 0:
177 tsec1_clk = 0;
178 break;
179 case 1:
180 tsec1_clk = csb_clk;
181 break;
182 case 2:
183 tsec1_clk = csb_clk / 2;
184 break;
185 case 3:
186 tsec1_clk = csb_clk / 3;
187 break;
188 default:
189 /* unkown SCCR_TSEC1CM value */
Dave Liu03051c32007-09-18 12:36:11 +0800190 return -2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500191 }
Gerlando Falauto8afad912012-10-10 22:13:07 +0000192#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500193
Gerlando Falauto8afad912012-10-10 22:13:07 +0000194#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
195 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Scott Wood7c98e512007-04-16 14:34:19 -0500196 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
197 case 0:
198 usbdr_clk = 0;
199 break;
200 case 1:
201 usbdr_clk = csb_clk;
202 break;
203 case 2:
204 usbdr_clk = csb_clk / 2;
205 break;
206 case 3:
207 usbdr_clk = csb_clk / 3;
208 break;
209 default:
210 /* unkown SCCR_USBDRCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800211 return -3;
Scott Wood7c98e512007-04-16 14:34:19 -0500212 }
213#endif
214
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400215#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
216 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500217 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
218 case 0:
219 tsec2_clk = 0;
220 break;
221 case 1:
222 tsec2_clk = csb_clk;
223 break;
224 case 2:
225 tsec2_clk = csb_clk / 2;
226 break;
227 case 3:
228 tsec2_clk = csb_clk / 3;
229 break;
230 default:
231 /* unkown SCCR_TSEC2CM value */
Dave Liu03051c32007-09-18 12:36:11 +0800232 return -4;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500233 }
Dave Liu555da612007-09-18 12:36:58 +0800234#elif defined(CONFIG_MPC8313)
Dave Liu03051c32007-09-18 12:36:11 +0800235 tsec2_clk = tsec1_clk;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500236
Dave Liu03051c32007-09-18 12:36:11 +0800237 if (!(sccr & SCCR_TSEC1ON))
238 tsec1_clk = 0;
239 if (!(sccr & SCCR_TSEC2ON))
240 tsec2_clk = 0;
241#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500242
Peter Tyser2c7920a2009-05-22 17:23:25 -0500243#if defined(CONFIG_MPC834x)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500244 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
245 case 0:
246 usbmph_clk = 0;
247 break;
248 case 1:
249 usbmph_clk = csb_clk;
250 break;
251 case 2:
252 usbmph_clk = csb_clk / 2;
253 break;
254 case 3:
255 usbmph_clk = csb_clk / 3;
256 break;
257 default:
258 /* unkown SCCR_USBMPHCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800259 return -5;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500260 }
261
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600262 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
263 /* if USB MPH clock is not disabled and
264 * USB DR clock is not disabled then
265 * USB MPH & USB DR must have the same rate
266 */
Dave Liu03051c32007-09-18 12:36:11 +0800267 return -6;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500268 }
Dave Liu5f820432006-11-03 19:33:44 -0600269#endif
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000270#if !defined(CONFIG_MPC8309)
Dave Liu5f820432006-11-03 19:33:44 -0600271 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
272 case 0:
273 enc_clk = 0;
274 break;
275 case 1:
276 enc_clk = csb_clk;
277 break;
278 case 2:
279 enc_clk = csb_clk / 2;
280 break;
281 case 3:
282 enc_clk = csb_clk / 3;
283 break;
284 default:
285 /* unkown SCCR_ENCCM value */
Dave Liu03051c32007-09-18 12:36:11 +0800286 return -7;
Dave Liu5f820432006-11-03 19:33:44 -0600287 }
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000288#endif
Dave Liu24c3aca2006-12-07 21:13:15 +0800289
Rini van Zetten27ef5782010-04-15 16:03:05 +0200290#if defined(CONFIG_FSL_ESDHC)
Dave Liu03051c32007-09-18 12:36:11 +0800291 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
292 case 0:
293 sdhc_clk = 0;
294 break;
295 case 1:
296 sdhc_clk = csb_clk;
297 break;
298 case 2:
299 sdhc_clk = csb_clk / 2;
300 break;
301 case 3:
302 sdhc_clk = csb_clk / 3;
303 break;
304 default:
305 /* unkown SCCR_SDHCCM value */
306 return -8;
307 }
308#endif
Dave Liu555da612007-09-18 12:36:58 +0800309#if defined(CONFIG_MPC8315)
310 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
311 case 0:
312 tdm_clk = 0;
313 break;
314 case 1:
315 tdm_clk = csb_clk;
316 break;
317 case 2:
318 tdm_clk = csb_clk / 2;
319 break;
320 case 3:
321 tdm_clk = csb_clk / 3;
322 break;
323 default:
324 /* unkown SCCR_TDMCM value */
325 return -8;
326 }
327#endif
Dave Liu03051c32007-09-18 12:36:11 +0800328
Peter Tyser2c7920a2009-05-22 17:23:25 -0500329#if defined(CONFIG_MPC834x)
Dave Liu03051c32007-09-18 12:36:11 +0800330 i2c1_clk = tsec2_clk;
331#elif defined(CONFIG_MPC8360)
332 i2c1_clk = csb_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -0500333#elif defined(CONFIG_MPC832x)
Dave Liu03051c32007-09-18 12:36:11 +0800334 i2c1_clk = enc_clk;
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400335#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
Dave Liu03051c32007-09-18 12:36:11 +0800336 i2c1_clk = enc_clk;
Rini van Zetten27ef5782010-04-15 16:03:05 +0200337#elif defined(CONFIG_FSL_ESDHC)
Dave Liu03051c32007-09-18 12:36:11 +0800338 i2c1_clk = sdhc_clk;
Andre Schwarz1bda1622011-04-14 14:57:40 +0200339#elif defined(CONFIG_MPC837x)
340 i2c1_clk = enc_clk;
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000341#elif defined(CONFIG_MPC8309)
342 i2c1_clk = csb_clk;
Dave Liu03051c32007-09-18 12:36:11 +0800343#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500344#if !defined(CONFIG_MPC832x)
Dave Liu03051c32007-09-18 12:36:11 +0800345 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
346#endif
347
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400348#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
349 defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800350 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
351 case 0:
352 pciexp1_clk = 0;
353 break;
354 case 1:
355 pciexp1_clk = csb_clk;
356 break;
357 case 2:
358 pciexp1_clk = csb_clk / 2;
359 break;
360 case 3:
361 pciexp1_clk = csb_clk / 3;
362 break;
363 default:
364 /* unkown SCCR_PCIEXP1CM value */
365 return -9;
366 }
367
368 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
369 case 0:
370 pciexp2_clk = 0;
371 break;
372 case 1:
373 pciexp2_clk = csb_clk;
374 break;
375 case 2:
376 pciexp2_clk = csb_clk / 2;
377 break;
378 case 3:
379 pciexp2_clk = csb_clk / 3;
380 break;
381 default:
382 /* unkown SCCR_PCIEXP2CM value */
383 return -10;
384 }
385#endif
386
Peter Tyser2c7920a2009-05-22 17:23:25 -0500387#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Dave Liua8cb43a2008-01-17 18:23:19 +0800388 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
389 case 0:
Dave Liu03051c32007-09-18 12:36:11 +0800390 sata_clk = 0;
391 break;
Dave Liua8cb43a2008-01-17 18:23:19 +0800392 case 1:
Dave Liu03051c32007-09-18 12:36:11 +0800393 sata_clk = csb_clk;
394 break;
Dave Liua8cb43a2008-01-17 18:23:19 +0800395 case 2:
Dave Liu03051c32007-09-18 12:36:11 +0800396 sata_clk = csb_clk / 2;
397 break;
Dave Liua8cb43a2008-01-17 18:23:19 +0800398 case 3:
Dave Liu03051c32007-09-18 12:36:11 +0800399 sata_clk = csb_clk / 3;
400 break;
401 default:
Kim Phillips9e896472008-01-16 12:06:16 -0600402 /* unkown SCCR_SATACM value */
Dave Liu03051c32007-09-18 12:36:11 +0800403 return -11;
404 }
405#endif
406
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600407 lbiu_clk = csb_clk *
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100408 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
Becky Brucef51cdaf2010-06-17 11:37:20 -0500409 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500410 switch (lcrr) {
411 case 2:
412 case 4:
413 case 8:
414 lclk_clk = lbiu_clk / lcrr;
415 break;
416 default:
417 /* unknown lcrr */
Dave Liu03051c32007-09-18 12:36:11 +0800418 return -12;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500419 }
Dave Liu24c3aca2006-12-07 21:13:15 +0800420
Kim Phillips35cf1552008-03-28 10:18:40 -0500421 mem_clk = csb_clk *
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100422 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
423 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
424
Dave Liu24c3aca2006-12-07 21:13:15 +0800425#if defined(CONFIG_MPC8360)
Kim Phillips35cf1552008-03-28 10:18:40 -0500426 mem_sec_clk = csb_clk * (1 +
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100427 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
Dave Liu5f820432006-11-03 19:33:44 -0600428#endif
Dave Liu5f820432006-11-03 19:33:44 -0600429
Eran Libertyf046ccd2005-07-28 10:08:46 -0500430 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600431 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500432 /* corecnf_tab_index is too high, possibly worng value */
433 return -11;
434 }
435 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
436 case _byp:
437 case _x1:
438 case _1x:
439 core_clk = csb_clk;
440 break;
441 case _1_5x:
442 core_clk = (3 * csb_clk) / 2;
443 break;
444 case _2x:
445 core_clk = 2 * csb_clk;
446 break;
447 case _2_5x:
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600448 core_clk = (5 * csb_clk) / 2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500449 break;
450 case _3x:
451 core_clk = 3 * csb_clk;
452 break;
453 default:
454 /* unkown core to csb ratio */
Dave Liu03051c32007-09-18 12:36:11 +0800455 return -13;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500456 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500457
Gerlando Falauto4b5282d2012-10-10 22:13:06 +0000458#if defined(CONFIG_QE)
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100459 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
460 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600461 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
Dave Liu5f820432006-11-03 19:33:44 -0600462 brg_clk = qe_clk / 2;
463#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500464
Simon Glassc6731fe2012-12-13 20:48:47 +0000465 gd->arch.csb_clk = csb_clk;
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400466#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
467 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000468 gd->arch.tsec1_clk = tsec1_clk;
469 gd->arch.tsec2_clk = tsec2_clk;
470 gd->arch.usbdr_clk = usbdr_clk;
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000471#elif defined(CONFIG_MPC8309)
Simon Glassc6731fe2012-12-13 20:48:47 +0000472 gd->arch.usbdr_clk = usbdr_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600473#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500474#if defined(CONFIG_MPC834x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000475 gd->arch.usbmph_clk = usbmph_clk;
Scott Wood7c98e512007-04-16 14:34:19 -0500476#endif
Dave Liu555da612007-09-18 12:36:58 +0800477#if defined(CONFIG_MPC8315)
Simon Glassc6731fe2012-12-13 20:48:47 +0000478 gd->arch.tdm_clk = tdm_clk;
Dave Liu555da612007-09-18 12:36:58 +0800479#endif
Rini van Zetten27ef5782010-04-15 16:03:05 +0200480#if defined(CONFIG_FSL_ESDHC)
Simon Glasse9adeca2012-12-13 20:49:05 +0000481 gd->arch.sdhc_clk = sdhc_clk;
Dave Liu03051c32007-09-18 12:36:11 +0800482#endif
Simon Glassc6731fe2012-12-13 20:48:47 +0000483 gd->arch.core_clk = core_clk;
Simon Glass609e6ec2012-12-13 20:48:49 +0000484 gd->arch.i2c1_clk = i2c1_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -0500485#if !defined(CONFIG_MPC832x)
Simon Glass609e6ec2012-12-13 20:48:49 +0000486 gd->arch.i2c2_clk = i2c2_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800487#endif
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000488#if !defined(CONFIG_MPC8309)
Simon Glassc6731fe2012-12-13 20:48:47 +0000489 gd->arch.enc_clk = enc_clk;
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000490#endif
Simon Glassc6731fe2012-12-13 20:48:47 +0000491 gd->arch.lbiu_clk = lbiu_clk;
492 gd->arch.lclk_clk = lclk_clk;
Kim Phillips35cf1552008-03-28 10:18:40 -0500493 gd->mem_clk = mem_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800494#if defined(CONFIG_MPC8360)
Simon Glassc6731fe2012-12-13 20:48:47 +0000495 gd->arch.mem_sec_clk = mem_sec_clk;
Dave Liu24c3aca2006-12-07 21:13:15 +0800496#endif
Gerlando Falauto4b5282d2012-10-10 22:13:06 +0000497#if defined(CONFIG_QE)
Simon Glass45bae2e2012-12-13 20:48:50 +0000498 gd->arch.qe_clk = qe_clk;
Simon Glass1206c182012-12-13 20:48:44 +0000499 gd->arch.brg_clk = brg_clk;
Dave Liu5f820432006-11-03 19:33:44 -0600500#endif
Bill Cook810cb192011-05-25 15:51:07 -0400501#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
502 defined(CONFIG_MPC837x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000503 gd->arch.pciexp1_clk = pciexp1_clk;
504 gd->arch.pciexp2_clk = pciexp2_clk;
Dave Liu555da612007-09-18 12:36:58 +0800505#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500506#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Simon Glassc6731fe2012-12-13 20:48:47 +0000507 gd->arch.sata_clk = sata_clk;
Dave Liu03051c32007-09-18 12:36:11 +0800508#endif
Kim Phillips8f9e0e92007-08-15 22:30:19 -0500509 gd->pci_clk = pci_sync_in;
Simon Glassc6731fe2012-12-13 20:48:47 +0000510 gd->cpu_clk = gd->arch.core_clk;
511 gd->bus_clk = gd->arch.csb_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500512 return 0;
Dave Liu5f820432006-11-03 19:33:44 -0600513
Eran Libertyf046ccd2005-07-28 10:08:46 -0500514}
515
516/********************************************
517 * get_bus_freq
518 * return system bus freq in Hz
519 *********************************************/
Kim Phillipsf7fb2e72006-11-02 19:47:11 -0600520ulong get_bus_freq(ulong dummy)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500521{
Simon Glassc6731fe2012-12-13 20:48:47 +0000522 return gd->arch.csb_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500523}
524
York Sund29d17d2011-08-26 11:32:44 -0700525/********************************************
526 * get_ddr_freq
527 * return ddr bus freq in Hz
528 *********************************************/
529ulong get_ddr_freq(ulong dummy)
530{
531 return gd->mem_clk;
532}
533
Kim Phillipsa2873bd2012-10-29 13:34:39 +0000534static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Eran Libertyf046ccd2005-07-28 10:08:46 -0500535{
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200536 char buf[32];
537
Eran Libertyf046ccd2005-07-28 10:08:46 -0500538 printf("Clock configuration:\n");
Simon Glassc6731fe2012-12-13 20:48:47 +0000539 printf(" Core: %-4s MHz\n",
540 strmhz(buf, gd->arch.core_clk));
541 printf(" Coherent System Bus: %-4s MHz\n",
542 strmhz(buf, gd->arch.csb_clk));
Gerlando Falauto4b5282d2012-10-10 22:13:06 +0000543#if defined(CONFIG_QE)
Simon Glass45bae2e2012-12-13 20:48:50 +0000544 printf(" QE: %-4s MHz\n",
545 strmhz(buf, gd->arch.qe_clk));
Simon Glass1206c182012-12-13 20:48:44 +0000546 printf(" BRG: %-4s MHz\n",
547 strmhz(buf, gd->arch.brg_clk));
Dave Liu5f820432006-11-03 19:33:44 -0600548#endif
Simon Glassc6731fe2012-12-13 20:48:47 +0000549 printf(" Local Bus Controller:%-4s MHz\n",
550 strmhz(buf, gd->arch.lbiu_clk));
551 printf(" Local Bus: %-4s MHz\n",
552 strmhz(buf, gd->arch.lclk_clk));
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200553 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
Dave Liu24c3aca2006-12-07 21:13:15 +0800554#if defined(CONFIG_MPC8360)
Simon Glassc6731fe2012-12-13 20:48:47 +0000555 printf(" DDR Secondary: %-4s MHz\n",
556 strmhz(buf, gd->arch.mem_sec_clk));
Dave Liu5f820432006-11-03 19:33:44 -0600557#endif
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000558#if !defined(CONFIG_MPC8309)
Simon Glassc6731fe2012-12-13 20:48:47 +0000559 printf(" SEC: %-4s MHz\n",
560 strmhz(buf, gd->arch.enc_clk));
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000561#endif
Simon Glass609e6ec2012-12-13 20:48:49 +0000562 printf(" I2C1: %-4s MHz\n",
563 strmhz(buf, gd->arch.i2c1_clk));
Peter Tyser2c7920a2009-05-22 17:23:25 -0500564#if !defined(CONFIG_MPC832x)
Simon Glass609e6ec2012-12-13 20:48:49 +0000565 printf(" I2C2: %-4s MHz\n",
566 strmhz(buf, gd->arch.i2c2_clk));
Dave Liu24c3aca2006-12-07 21:13:15 +0800567#endif
Dave Liu555da612007-09-18 12:36:58 +0800568#if defined(CONFIG_MPC8315)
Simon Glassc6731fe2012-12-13 20:48:47 +0000569 printf(" TDM: %-4s MHz\n",
570 strmhz(buf, gd->arch.tdm_clk));
Dave Liu555da612007-09-18 12:36:58 +0800571#endif
Rini van Zetten27ef5782010-04-15 16:03:05 +0200572#if defined(CONFIG_FSL_ESDHC)
Simon Glasse9adeca2012-12-13 20:49:05 +0000573 printf(" SDHC: %-4s MHz\n",
574 strmhz(buf, gd->arch.sdhc_clk));
Dave Liu03051c32007-09-18 12:36:11 +0800575#endif
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400576#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
577 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000578 printf(" TSEC1: %-4s MHz\n",
579 strmhz(buf, gd->arch.tsec1_clk));
580 printf(" TSEC2: %-4s MHz\n",
581 strmhz(buf, gd->arch.tsec2_clk));
582 printf(" USB DR: %-4s MHz\n",
583 strmhz(buf, gd->arch.usbdr_clk));
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000584#elif defined(CONFIG_MPC8309)
Simon Glassc6731fe2012-12-13 20:48:47 +0000585 printf(" USB DR: %-4s MHz\n",
586 strmhz(buf, gd->arch.usbdr_clk));
Dave Liu5f820432006-11-03 19:33:44 -0600587#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500588#if defined(CONFIG_MPC834x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000589 printf(" USB MPH: %-4s MHz\n",
590 strmhz(buf, gd->arch.usbmph_clk));
Scott Wood7c98e512007-04-16 14:34:19 -0500591#endif
Bill Cook810cb192011-05-25 15:51:07 -0400592#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
593 defined(CONFIG_MPC837x)
Simon Glassc6731fe2012-12-13 20:48:47 +0000594 printf(" PCIEXP1: %-4s MHz\n",
595 strmhz(buf, gd->arch.pciexp1_clk));
596 printf(" PCIEXP2: %-4s MHz\n",
597 strmhz(buf, gd->arch.pciexp2_clk));
Dave Liu555da612007-09-18 12:36:58 +0800598#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -0500599#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Simon Glassc6731fe2012-12-13 20:48:47 +0000600 printf(" SATA: %-4s MHz\n",
601 strmhz(buf, gd->arch.sata_clk));
Dave Liu03051c32007-09-18 12:36:11 +0800602#endif
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500603 return 0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500604}
Kim Phillips54b2d432007-04-30 15:26:21 -0500605
606U_BOOT_CMD(clocks, 1, 0, do_clocks,
Peter Tyser2fb26042009-01-27 18:03:12 -0600607 "print clock configuration",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200608 " clocks"
Kim Phillips54b2d432007-04-30 15:26:21 -0500609);