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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / dfbdc69c5d8c8b7ddd467191317d19c8bc038676 / . / arch / arm / dts / imx8mm-kontron-sl.dtsi
blob: 11a50cffc8c4c01663efe019b743a5c1e05e9585 [file] [log] [blame]
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm.dtsi"
7
8/ {
Frieder Schrempfdfbdc692022-08-24 15:59:15 +0200[diff] [blame^]9 model = "Kontron SL i.MX8MM (N801X SOM)";
10 compatible = "kontron,imx8mm-sl", "fsl,imx8mm";
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]11
12 memory@40000000 {
13 device_type = "memory";
14 /*
15 * There are multiple SoM flavors with different DDR sizes.
16 * The smallest is 1GB. For larger sizes the bootloader will
17 * update the reg property.
18 */
19 reg = <0x0 0x40000000 0 0x80000000>;
20 };
21
22 chosen {
23 stdout-path = &uart3;
24 };
25};
26
27&A53_0 {
28 cpu-supply = <&reg_vdd_arm>;
29};
30
31&A53_1 {
32 cpu-supply = <&reg_vdd_arm>;
33};
34
35&A53_2 {
36 cpu-supply = <&reg_vdd_arm>;
37};
38
39&A53_3 {
40 cpu-supply = <&reg_vdd_arm>;
41};
42
43&ddrc {
44 operating-points-v2 = <&ddrc_opp_table>;
45
46 ddrc_opp_table: opp-table {
47 compatible = "operating-points-v2";
48
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]49 opp-100M {
50 opp-hz = /bits/ 64 <100000000>;
51 };
52
53 opp-750M {
54 opp-hz = /bits/ 64 <750000000>;
55 };
56 };
57};
58
59&ecspi1 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_ecspi1>;
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]62 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]63 status = "okay";
64
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]65 flash@0 {
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]66 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
67 spi-max-frequency = <80000000>;
68 reg = <0>;
Frieder Schrempf2a6f0232022-08-24 15:59:07 +0200[diff] [blame]69
70 partitions {
71 compatible = "fixed-partitions";
72 #address-cells = <1>;
73 #size-cells = <1>;
74
75 partition@0 {
76 label = "u-boot";
77 reg = <0x0 0x1e0000>;
78 };
79
80 partition@1e0000 {
81 label = "env";
82 reg = <0x1e0000 0x10000>;
83 };
84
85 partition@1f0000 {
86 label = "env_redundant";
87 reg = <0x1f0000 0x10000>;
88 };
89 };
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]90 };
91};
92
93&i2c1 {
94 clock-frequency = <400000>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_i2c1>;
97 status = "okay";
98
99 pca9450: pmic@25 {
100 compatible = "nxp,pca9450a";
101 reg = <0x25>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_pmic>;
104 interrupt-parent = <&gpio1>;
105 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
106 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
107
108 regulators {
109 reg_vdd_soc: BUCK1 {
110 regulator-name = "buck1";
111 regulator-min-microvolt = <800000>;
112 regulator-max-microvolt = <850000>;
113 regulator-boot-on;
114 regulator-always-on;
115 regulator-ramp-delay = <3125>;
116 nxp,dvs-run-voltage = <850000>;
117 nxp,dvs-standby-voltage = <800000>;
118 };
119
120 reg_vdd_arm: BUCK2 {
121 regulator-name = "buck2";
122 regulator-min-microvolt = <850000>;
123 regulator-max-microvolt = <950000>;
124 regulator-boot-on;
125 regulator-always-on;
126 regulator-ramp-delay = <3125>;
127 nxp,dvs-run-voltage = <950000>;
128 nxp,dvs-standby-voltage = <850000>;
129 };
130
131 reg_vdd_dram: BUCK3 {
132 regulator-name = "buck3";
133 regulator-min-microvolt = <850000>;
134 regulator-max-microvolt = <950000>;
135 regulator-boot-on;
136 regulator-always-on;
137 };
138
139 reg_vdd_3v3: BUCK4 {
140 regulator-name = "buck4";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 reg_vdd_1v8: BUCK5 {
148 regulator-name = "buck5";
149 regulator-min-microvolt = <1800000>;
150 regulator-max-microvolt = <1800000>;
151 regulator-boot-on;
152 regulator-always-on;
153 };
154
155 reg_nvcc_dram: BUCK6 {
156 regulator-name = "buck6";
157 regulator-min-microvolt = <1100000>;
158 regulator-max-microvolt = <1100000>;
159 regulator-boot-on;
160 regulator-always-on;
161 };
162
163 reg_nvcc_snvs: LDO1 {
164 regulator-name = "ldo1";
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
167 regulator-boot-on;
168 regulator-always-on;
169 };
170
171 reg_vdd_snvs: LDO2 {
172 regulator-name = "ldo2";
173 regulator-min-microvolt = <800000>;
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]174 regulator-max-microvolt = <900000>;
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 reg_vdda: LDO3 {
180 regulator-name = "ldo3";
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <1800000>;
183 regulator-boot-on;
184 regulator-always-on;
185 };
186
187 reg_vdd_phy: LDO4 {
188 regulator-name = "ldo4";
189 regulator-min-microvolt = <900000>;
190 regulator-max-microvolt = <900000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 reg_nvcc_sd: LDO5 {
196 regulator-name = "ldo5";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <3300000>;
199 };
200 };
201 };
202};
203
204&uart3 { /* console */
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart3>;
207 status = "okay";
208};
209
210&usdhc1 {
211 pinctrl-names = "default", "state_100mhz", "state_200mhz";
212 pinctrl-0 = <&pinctrl_usdhc1>;
213 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
214 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
215 vmmc-supply = <&reg_vdd_3v3>;
216 vqmmc-supply = <&reg_vdd_1v8>;
217 bus-width = <8>;
218 non-removable;
219 status = "okay";
220};
221
222&wdog1 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_wdog>;
225 fsl,ext-reset-output;
226 status = "okay";
227};
228
229&iomuxc {
230 pinctrl_ecspi1: ecspi1grp {
231 fsl,pins = <
232 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
233 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
234 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
235 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
236 >;
237 };
238
239 pinctrl_i2c1: i2c1grp {
240 fsl,pins = <
241 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
242 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
243 >;
244 };
245
246 pinctrl_pmic: pmicgrp {
247 fsl,pins = <
248 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
249 MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
250 >;
251 };
252
253 pinctrl_uart3: uart3grp {
254 fsl,pins = <
255 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
256 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
257 >;
258 };
259
260 pinctrl_usdhc1: usdhc1grp {
261 fsl,pins = <
262 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
263 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
264 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
265 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
266 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
267 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
268 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
269 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
270 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
271 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
272 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
273 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
274 >;
275 };
276
277 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
278 fsl,pins = <
279 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
280 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
281 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
282 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
283 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
284 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
285 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
286 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
287 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
288 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
289 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
290 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
291 >;
292 };
293
294 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
295 fsl,pins = <
296 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
297 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
298 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
299 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
300 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
301 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
302 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
303 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
304 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
305 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
306 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
307 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
308 >;
309 };
310
311 pinctrl_wdog: wdoggrp {
312 fsl,pins = <
313 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
314 >;
315 };
316};