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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek293eb332013-04-22 14:56:49 +02002/*
Michal Simekd9ae52c2015-11-30 16:13:03 +01003 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek293eb332013-04-22 14:56:49 +02004 *
5 * Xilinx Zynq SD Host Controller Interface
Michal Simek293eb332013-04-22 14:56:49 +02006 */
7
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +01008#include <clk.h>
Michal Simek293eb332013-04-22 14:56:49 +02009#include <common.h>
Michal Simekd9ae52c2015-11-30 16:13:03 +010010#include <dm.h>
Michal Simek345d3c02014-02-24 11:16:31 +010011#include <fdtdec.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090012#include <linux/libfdt.h>
Michal Simek293eb332013-04-22 14:56:49 +020013#include <malloc.h>
14#include <sdhci.h>
Michal Simek293eb332013-04-22 14:56:49 +020015
Stefan Herbrechtsmeier61e745d2017-01-17 16:27:33 +010016DECLARE_GLOBAL_DATA_PTR;
17
Simon Glass329a4492016-07-05 17:10:15 -060018struct arasan_sdhci_plat {
19 struct mmc_config cfg;
20 struct mmc mmc;
Stefan Herbrechtsmeier61e745d2017-01-17 16:27:33 +010021 unsigned int f_max;
Simon Glass329a4492016-07-05 17:10:15 -060022};
23
Michal Simekd9ae52c2015-11-30 16:13:03 +010024static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek293eb332013-04-22 14:56:49 +020025{
Simon Glass329a4492016-07-05 17:10:15 -060026 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simekd9ae52c2015-11-30 16:13:03 +010027 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
28 struct sdhci_host *host = dev_get_priv(dev);
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010029 struct clk clk;
30 unsigned long clock;
Simon Glass329a4492016-07-05 17:10:15 -060031 int ret;
Michal Simek293eb332013-04-22 14:56:49 +020032
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010033 ret = clk_get_by_index(dev, 0, &clk);
34 if (ret < 0) {
35 dev_err(dev, "failed to get clock\n");
36 return ret;
37 }
38
39 clock = clk_get_rate(&clk);
40 if (IS_ERR_VALUE(clock)) {
41 dev_err(dev, "failed to get rate\n");
42 return clock;
43 }
44 debug("%s: CLK %ld\n", __func__, clock);
45
46 ret = clk_enable(&clk);
47 if (ret && ret != -ENOSYS) {
48 dev_err(dev, "failed to enable clock\n");
49 return ret;
50 }
51
Siva Durga Prasad Paladugueddabd12014-07-08 15:31:04 +053052 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladuguf9ec45d2014-01-22 09:17:09 +010053 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugub2156142016-01-12 15:12:16 +053054
55#ifdef CONFIG_ZYNQ_HISPD_BROKEN
Hannes Schmelzer47819212018-03-07 08:00:57 +010056 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
Siva Durga Prasad Paladugub2156142016-01-12 15:12:16 +053057#endif
58
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010059 host->max_clk = clock;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +010060
Stefan Herbrechtsmeier61e745d2017-01-17 16:27:33 +010061 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
Jaehoon Chung14bed522016-07-26 19:06:24 +090062 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass329a4492016-07-05 17:10:15 -060063 host->mmc = &plat->mmc;
64 if (ret)
65 return ret;
66 host->mmc->priv = host;
Simon Glasscffe5d82016-05-01 13:52:34 -060067 host->mmc->dev = dev;
Simon Glass329a4492016-07-05 17:10:15 -060068 upriv->mmc = host->mmc;
Michal Simekd9ae52c2015-11-30 16:13:03 +010069
Simon Glass329a4492016-07-05 17:10:15 -060070 return sdhci_probe(dev);
Michal Simek293eb332013-04-22 14:56:49 +020071}
Michal Simekd9ae52c2015-11-30 16:13:03 +010072
73static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
74{
Stefan Herbrechtsmeier61e745d2017-01-17 16:27:33 +010075 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simekd9ae52c2015-11-30 16:13:03 +010076 struct sdhci_host *host = dev_get_priv(dev);
77
Masahiro Yamadacacd1d22016-04-22 20:59:31 +090078 host->name = dev->name;
Simon Glassa821c4a2017-05-17 17:18:05 -060079 host->ioaddr = (void *)devfdt_get_addr(dev);
Michal Simekd9ae52c2015-11-30 16:13:03 +010080
Simon Glassda409cc2017-05-17 17:18:09 -060081 plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Stefan Herbrechtsmeier61e745d2017-01-17 16:27:33 +010082 "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
83
Michal Simekd9ae52c2015-11-30 16:13:03 +010084 return 0;
85}
86
Simon Glass329a4492016-07-05 17:10:15 -060087static int arasan_sdhci_bind(struct udevice *dev)
88{
89 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass329a4492016-07-05 17:10:15 -060090
Masahiro Yamada24f5aec2016-09-06 22:17:32 +090091 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass329a4492016-07-05 17:10:15 -060092}
93
Michal Simekd9ae52c2015-11-30 16:13:03 +010094static const struct udevice_id arasan_sdhci_ids[] = {
95 { .compatible = "arasan,sdhci-8.9a" },
96 { }
97};
98
99U_BOOT_DRIVER(arasan_sdhci_drv) = {
100 .name = "arasan_sdhci",
101 .id = UCLASS_MMC,
102 .of_match = arasan_sdhci_ids,
103 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass329a4492016-07-05 17:10:15 -0600104 .ops = &sdhci_ops,
105 .bind = arasan_sdhci_bind,
Michal Simekd9ae52c2015-11-30 16:13:03 +0100106 .probe = arasan_sdhci_probe,
107 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass329a4492016-07-05 17:10:15 -0600108 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simekd9ae52c2015-11-30 16:13:03 +0100109};