blob: eb07d253011d4f0959d9714da5f9a4da79425b1b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassff3e0772015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassff3e0772015-03-05 12:25:25 -07005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <malloc.h>
Simon Glassff3e0772015-03-05 12:25:25 -070013#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070014#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070015#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060016#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070017#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
Simon Glass07f2f582019-08-24 14:19:05 -060018#include <asm/fsp/fsp_support.h>
Bin Meng348b7442015-08-20 06:40:23 -070019#endif
Simon Glassc05ed002020-05-10 11:40:11 -060020#include <linux/delay.h>
Simon Glass5e23b8b2015-11-29 13:17:49 -070021#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070022
23DECLARE_GLOBAL_DATA_PTR;
24
Simon Glassa6eb93b2016-01-18 20:19:14 -070025int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060026{
27 int ret;
28
29 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
30
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
32 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070033 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060034 if (ret)
35 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060036 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
37 }
38
39 return ret;
40}
41
Simon Glass9f60fb02015-11-19 20:27:00 -070042struct udevice *pci_get_controller(struct udevice *dev)
43{
44 while (device_is_on_pci_bus(dev))
45 dev = dev->parent;
46
47 return dev;
48}
49
Simon Glass194fca92020-01-27 08:49:38 -070050pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060051{
52 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
53 struct udevice *bus = dev->parent;
54
Simon Glass48862872019-12-29 21:19:14 -070055 /*
56 * This error indicates that @dev is a device on an unprobed PCI bus.
57 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
58 * will produce a bad BDF>
59 *
60 * A common cause of this problem is that this function is called in the
61 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
62 * method is not allowed, since it has not yet been probed. To fix this,
63 * move that access to the probe() method of @dev instead.
64 */
65 if (!device_active(bus))
66 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
67 bus->name);
Simon Glass4b515e42015-07-06 16:47:46 -060068 return PCI_ADD_BUS(bus->seq, pplat->devfn);
69}
70
Simon Glassff3e0772015-03-05 12:25:25 -070071/**
72 * pci_get_bus_max() - returns the bus number of the last active bus
73 *
74 * @return last bus number, or -1 if no active buses
75 */
76static int pci_get_bus_max(void)
77{
78 struct udevice *bus;
79 struct uclass *uc;
80 int ret = -1;
81
82 ret = uclass_get(UCLASS_PCI, &uc);
83 uclass_foreach_dev(bus, uc) {
84 if (bus->seq > ret)
85 ret = bus->seq;
86 }
87
88 debug("%s: ret=%d\n", __func__, ret);
89
90 return ret;
91}
92
93int pci_last_busno(void)
94{
Bin Meng069155c2015-10-01 00:36:01 -070095 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070096}
97
98int pci_get_ff(enum pci_size_t size)
99{
100 switch (size) {
101 case PCI_SIZE_8:
102 return 0xff;
103 case PCI_SIZE_16:
104 return 0xffff;
105 default:
106 return 0xffffffff;
107 }
108}
109
Marek Vasut02e4d382018-10-10 21:27:06 +0200110static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
111 ofnode *rnode)
112{
113 struct fdt_pci_addr addr;
114 ofnode node;
115 int ret;
116
117 dev_for_each_subnode(node, bus) {
118 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
119 &addr);
120 if (ret)
121 continue;
122
123 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
124 continue;
125
126 *rnode = node;
127 break;
128 }
129};
130
Simon Glassc4e72c42020-01-27 08:49:37 -0700131int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
Simon Glassff3e0772015-03-05 12:25:25 -0700132 struct udevice **devp)
133{
134 struct udevice *dev;
135
136 for (device_find_first_child(bus, &dev);
137 dev;
138 device_find_next_child(&dev)) {
139 struct pci_child_platdata *pplat;
140
141 pplat = dev_get_parent_platdata(dev);
142 if (pplat && pplat->devfn == find_devfn) {
143 *devp = dev;
144 return 0;
145 }
146 }
147
148 return -ENODEV;
149}
150
Simon Glassf3f1fae2015-11-29 13:17:48 -0700151int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700152{
153 struct udevice *bus;
154 int ret;
155
Simon Glass983c6ba22015-08-31 18:55:35 -0600156 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700157 if (ret)
158 return ret;
159 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
160}
161
162static int pci_device_matches_ids(struct udevice *dev,
163 struct pci_device_id *ids)
164{
165 struct pci_child_platdata *pplat;
166 int i;
167
168 pplat = dev_get_parent_platdata(dev);
169 if (!pplat)
170 return -EINVAL;
171 for (i = 0; ids[i].vendor != 0; i++) {
172 if (pplat->vendor == ids[i].vendor &&
173 pplat->device == ids[i].device)
174 return i;
175 }
176
177 return -EINVAL;
178}
179
180int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
181 int *indexp, struct udevice **devp)
182{
183 struct udevice *dev;
184
185 /* Scan all devices on this bus */
186 for (device_find_first_child(bus, &dev);
187 dev;
188 device_find_next_child(&dev)) {
189 if (pci_device_matches_ids(dev, ids) >= 0) {
190 if ((*indexp)-- <= 0) {
191 *devp = dev;
192 return 0;
193 }
194 }
195 }
196
197 return -ENODEV;
198}
199
200int pci_find_device_id(struct pci_device_id *ids, int index,
201 struct udevice **devp)
202{
203 struct udevice *bus;
204
205 /* Scan all known buses */
206 for (uclass_first_device(UCLASS_PCI, &bus);
207 bus;
208 uclass_next_device(&bus)) {
209 if (!pci_bus_find_devices(bus, ids, &index, devp))
210 return 0;
211 }
212 *devp = NULL;
213
214 return -ENODEV;
215}
216
Simon Glass5c0bf642015-11-29 13:17:50 -0700217static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
218 unsigned int device, int *indexp,
219 struct udevice **devp)
220{
221 struct pci_child_platdata *pplat;
222 struct udevice *dev;
223
224 for (device_find_first_child(bus, &dev);
225 dev;
226 device_find_next_child(&dev)) {
227 pplat = dev_get_parent_platdata(dev);
228 if (pplat->vendor == vendor && pplat->device == device) {
229 if (!(*indexp)--) {
230 *devp = dev;
231 return 0;
232 }
233 }
234 }
235
236 return -ENODEV;
237}
238
239int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
240 struct udevice **devp)
241{
242 struct udevice *bus;
243
244 /* Scan all known buses */
245 for (uclass_first_device(UCLASS_PCI, &bus);
246 bus;
247 uclass_next_device(&bus)) {
248 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
249 return device_probe(*devp);
250 }
251 *devp = NULL;
252
253 return -ENODEV;
254}
255
Simon Glassa0eb8352015-11-29 13:17:52 -0700256int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
257{
258 struct udevice *dev;
259
260 /* Scan all known buses */
261 for (pci_find_first_device(&dev);
262 dev;
263 pci_find_next_device(&dev)) {
264 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
265
266 if (pplat->class == find_class && !index--) {
267 *devp = dev;
268 return device_probe(*devp);
269 }
270 }
271 *devp = NULL;
272
273 return -ENODEV;
274}
275
Simon Glassff3e0772015-03-05 12:25:25 -0700276int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
277 unsigned long value, enum pci_size_t size)
278{
279 struct dm_pci_ops *ops;
280
281 ops = pci_get_ops(bus);
282 if (!ops->write_config)
283 return -ENOSYS;
284 return ops->write_config(bus, bdf, offset, value, size);
285}
286
Simon Glass319dba12016-03-06 19:27:52 -0700287int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
288 u32 clr, u32 set)
289{
290 ulong val;
291 int ret;
292
293 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
294 if (ret)
295 return ret;
296 val &= ~clr;
297 val |= set;
298
299 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
300}
301
Simon Glassff3e0772015-03-05 12:25:25 -0700302int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
303 enum pci_size_t size)
304{
305 struct udevice *bus;
306 int ret;
307
Simon Glass983c6ba22015-08-31 18:55:35 -0600308 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700309 if (ret)
310 return ret;
311
Bin Meng4d8615c2015-07-19 00:20:04 +0800312 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700313}
314
Simon Glass66afb4e2015-08-10 07:05:03 -0600315int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
316 enum pci_size_t size)
317{
318 struct udevice *bus;
319
Bin Meng1e0f2262015-09-11 03:24:34 -0700320 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600321 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700322 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
323 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600324}
325
Simon Glassff3e0772015-03-05 12:25:25 -0700326int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
327{
328 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
329}
330
331int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
332{
333 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
334}
335
336int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
337{
338 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
339}
340
Simon Glass66afb4e2015-08-10 07:05:03 -0600341int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
342{
343 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
344}
345
346int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
347{
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
349}
350
351int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
352{
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
354}
355
Simon Glass194fca92020-01-27 08:49:38 -0700356int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
Simon Glassff3e0772015-03-05 12:25:25 -0700357 unsigned long *valuep, enum pci_size_t size)
358{
359 struct dm_pci_ops *ops;
360
361 ops = pci_get_ops(bus);
362 if (!ops->read_config)
363 return -ENOSYS;
364 return ops->read_config(bus, bdf, offset, valuep, size);
365}
366
367int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
368 enum pci_size_t size)
369{
370 struct udevice *bus;
371 int ret;
372
Simon Glass983c6ba22015-08-31 18:55:35 -0600373 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700374 if (ret)
375 return ret;
376
Bin Meng4d8615c2015-07-19 00:20:04 +0800377 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700378}
379
Simon Glass194fca92020-01-27 08:49:38 -0700380int dm_pci_read_config(const struct udevice *dev, int offset,
381 unsigned long *valuep, enum pci_size_t size)
Simon Glass66afb4e2015-08-10 07:05:03 -0600382{
Simon Glass194fca92020-01-27 08:49:38 -0700383 const struct udevice *bus;
Simon Glass66afb4e2015-08-10 07:05:03 -0600384
Bin Meng1e0f2262015-09-11 03:24:34 -0700385 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600386 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700387 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600388 size);
389}
390
Simon Glassff3e0772015-03-05 12:25:25 -0700391int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
392{
393 unsigned long value;
394 int ret;
395
396 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
397 if (ret)
398 return ret;
399 *valuep = value;
400
401 return 0;
402}
403
404int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
405{
406 unsigned long value;
407 int ret;
408
409 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
410 if (ret)
411 return ret;
412 *valuep = value;
413
414 return 0;
415}
416
417int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
418{
419 unsigned long value;
420 int ret;
421
422 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
423 if (ret)
424 return ret;
425 *valuep = value;
426
427 return 0;
428}
429
Simon Glass194fca92020-01-27 08:49:38 -0700430int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
Simon Glass66afb4e2015-08-10 07:05:03 -0600431{
432 unsigned long value;
433 int ret;
434
435 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
436 if (ret)
437 return ret;
438 *valuep = value;
439
440 return 0;
441}
442
Simon Glass194fca92020-01-27 08:49:38 -0700443int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
Simon Glass66afb4e2015-08-10 07:05:03 -0600444{
445 unsigned long value;
446 int ret;
447
448 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
449 if (ret)
450 return ret;
451 *valuep = value;
452
453 return 0;
454}
455
Simon Glass194fca92020-01-27 08:49:38 -0700456int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
Simon Glass66afb4e2015-08-10 07:05:03 -0600457{
458 unsigned long value;
459 int ret;
460
461 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
462 if (ret)
463 return ret;
464 *valuep = value;
465
466 return 0;
467}
468
Simon Glass319dba12016-03-06 19:27:52 -0700469int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
470{
471 u8 val;
472 int ret;
473
474 ret = dm_pci_read_config8(dev, offset, &val);
475 if (ret)
476 return ret;
477 val &= ~clr;
478 val |= set;
479
480 return dm_pci_write_config8(dev, offset, val);
481}
482
483int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
484{
485 u16 val;
486 int ret;
487
488 ret = dm_pci_read_config16(dev, offset, &val);
489 if (ret)
490 return ret;
491 val &= ~clr;
492 val |= set;
493
494 return dm_pci_write_config16(dev, offset, val);
495}
496
497int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
498{
499 u32 val;
500 int ret;
501
502 ret = dm_pci_read_config32(dev, offset, &val);
503 if (ret)
504 return ret;
505 val &= ~clr;
506 val |= set;
507
508 return dm_pci_write_config32(dev, offset, val);
509}
510
Bin Mengbbbcb522015-10-01 00:36:02 -0700511static void set_vga_bridge_bits(struct udevice *dev)
512{
513 struct udevice *parent = dev->parent;
514 u16 bc;
515
516 while (parent->seq != 0) {
517 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
518 bc |= PCI_BRIDGE_CTL_VGA;
519 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
520 parent = parent->parent;
521 }
522}
523
Simon Glassff3e0772015-03-05 12:25:25 -0700524int pci_auto_config_devices(struct udevice *bus)
525{
526 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700527 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700528 unsigned int sub_bus;
529 struct udevice *dev;
530 int ret;
531
532 sub_bus = bus->seq;
533 debug("%s: start\n", __func__);
534 pciauto_config_init(hose);
535 for (ret = device_find_first_child(bus, &dev);
536 !ret && dev;
537 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700538 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600539 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700540
Simon Glassff3e0772015-03-05 12:25:25 -0700541 debug("%s: device %s\n", __func__, dev->name);
Suneel Garapatif0c36922020-05-04 21:25:25 -0700542 if (dev_of_valid(dev) &&
543 dev_read_bool(dev, "pci,no-autoconfig"))
Simon Glassd8c7fb52020-04-08 16:57:26 -0600544 continue;
Simon Glass5e23b8b2015-11-29 13:17:49 -0700545 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600546 if (ret < 0)
547 return ret;
548 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700549 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700550
551 pplat = dev_get_parent_platdata(dev);
552 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
553 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700554 }
555 debug("%s: done\n", __func__);
556
557 return sub_bus;
558}
559
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300560int pci_generic_mmap_write_config(
Simon Glassc4e72c42020-01-27 08:49:37 -0700561 const struct udevice *bus,
562 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
563 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300564 pci_dev_t bdf,
565 uint offset,
566 ulong value,
567 enum pci_size_t size)
568{
569 void *address;
570
571 if (addr_f(bus, bdf, offset, &address) < 0)
572 return 0;
573
574 switch (size) {
575 case PCI_SIZE_8:
576 writeb(value, address);
577 return 0;
578 case PCI_SIZE_16:
579 writew(value, address);
580 return 0;
581 case PCI_SIZE_32:
582 writel(value, address);
583 return 0;
584 default:
585 return -EINVAL;
586 }
587}
588
589int pci_generic_mmap_read_config(
Simon Glassc4e72c42020-01-27 08:49:37 -0700590 const struct udevice *bus,
591 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
592 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300593 pci_dev_t bdf,
594 uint offset,
595 ulong *valuep,
596 enum pci_size_t size)
597{
598 void *address;
599
600 if (addr_f(bus, bdf, offset, &address) < 0) {
601 *valuep = pci_get_ff(size);
602 return 0;
603 }
604
605 switch (size) {
606 case PCI_SIZE_8:
607 *valuep = readb(address);
608 return 0;
609 case PCI_SIZE_16:
610 *valuep = readw(address);
611 return 0;
612 case PCI_SIZE_32:
613 *valuep = readl(address);
614 return 0;
615 default:
616 return -EINVAL;
617 }
618}
619
Simon Glass5e23b8b2015-11-29 13:17:49 -0700620int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700621{
Simon Glassff3e0772015-03-05 12:25:25 -0700622 int sub_bus;
623 int ret;
Suneel Garapati636cc172019-10-19 15:52:32 -0700624 int ea_pos;
625 u8 reg;
Simon Glassff3e0772015-03-05 12:25:25 -0700626
627 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700628
Suneel Garapati636cc172019-10-19 15:52:32 -0700629 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
630 if (ea_pos) {
631 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
632 &reg);
633 sub_bus = reg;
634 } else {
635 sub_bus = pci_get_bus_max() + 1;
636 }
Simon Glassff3e0772015-03-05 12:25:25 -0700637 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700638 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700639
640 ret = device_probe(bus);
641 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600642 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700643 ret);
644 return ret;
645 }
Suneel Garapati636cc172019-10-19 15:52:32 -0700646
647 if (!ea_pos) {
648 if (sub_bus != bus->seq) {
649 debug("%s: Internal error, bus '%s' got seq %d, expected %d\n",
650 __func__, bus->name, bus->seq, sub_bus);
651 return -EPIPE;
652 }
653 sub_bus = pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -0700654 }
Simon Glass5e23b8b2015-11-29 13:17:49 -0700655 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700656
657 return sub_bus;
658}
659
Simon Glassaba92962015-07-06 16:47:44 -0600660/**
661 * pci_match_one_device - Tell if a PCI device structure has a matching
662 * PCI device id structure
663 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800664 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600665 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800666 * Returns true if the finding pci_device_id structure matched or false if
667 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600668 */
669static bool pci_match_one_id(const struct pci_device_id *id,
670 const struct pci_device_id *find)
671{
672 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
673 (id->device == PCI_ANY_ID || id->device == find->device) &&
674 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
675 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
676 !((id->class ^ find->class) & id->class_mask))
677 return true;
678
679 return false;
680}
681
682/**
683 * pci_find_and_bind_driver() - Find and bind the right PCI driver
684 *
685 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600686 *
687 * @parent: Parent bus
688 * @find_id: Specification of the driver to find
689 * @bdf: Bus/device/function addreess - see PCI_BDF()
690 * @devp: Returns a pointer to the device created
691 * @return 0 if OK, -EPERM if the device is not needed before relocation and
692 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600693 */
694static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600695 struct pci_device_id *find_id,
696 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600697{
698 struct pci_driver_entry *start, *entry;
Marek Vasut02e4d382018-10-10 21:27:06 +0200699 ofnode node = ofnode_null();
Simon Glassaba92962015-07-06 16:47:44 -0600700 const char *drv;
701 int n_ents;
702 int ret;
703 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700704 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600705
706 *devp = NULL;
707
708 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
709 find_id->vendor, find_id->device);
Marek Vasut02e4d382018-10-10 21:27:06 +0200710
711 /* Determine optional OF node */
Suneel Garapatibc301402019-10-19 16:02:48 -0700712 if (ofnode_valid(dev_ofnode(parent)))
713 pci_dev_find_ofnode(parent, bdf, &node);
Marek Vasut02e4d382018-10-10 21:27:06 +0200714
Michael Wallea6cd5972019-12-01 17:45:18 +0100715 if (ofnode_valid(node) && !ofnode_is_available(node)) {
716 debug("%s: Ignoring disabled device\n", __func__);
717 return -EPERM;
718 }
719
Simon Glassaba92962015-07-06 16:47:44 -0600720 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
721 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
722 for (entry = start; entry != start + n_ents; entry++) {
723 const struct pci_device_id *id;
724 struct udevice *dev;
725 const struct driver *drv;
726
727 for (id = entry->match;
728 id->vendor || id->subvendor || id->class_mask;
729 id++) {
730 if (!pci_match_one_id(id, find_id))
731 continue;
732
733 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700734
735 /*
736 * In the pre-relocation phase, we only bind devices
737 * whose driver has the DM_FLAG_PRE_RELOC set, to save
738 * precious memory space as on some platforms as that
739 * space is pretty limited (ie: using Cache As RAM).
740 */
741 if (!(gd->flags & GD_FLG_RELOC) &&
742 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600743 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700744
Simon Glassaba92962015-07-06 16:47:44 -0600745 /*
746 * We could pass the descriptor to the driver as
747 * platdata (instead of NULL) and allow its bind()
748 * method to return -ENOENT if it doesn't support this
749 * device. That way we could continue the search to
750 * find another driver. For now this doesn't seem
751 * necesssary, so just bind the first match.
752 */
Marek Vasut02e4d382018-10-10 21:27:06 +0200753 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
754 node, &dev);
Simon Glassaba92962015-07-06 16:47:44 -0600755 if (ret)
756 goto error;
757 debug("%s: Match found: %s\n", __func__, drv->name);
Bin Menged698aa2018-08-03 01:14:44 -0700758 dev->driver_data = id->driver_data;
Simon Glassaba92962015-07-06 16:47:44 -0600759 *devp = dev;
760 return 0;
761 }
762 }
763
Bin Meng08fc7b82015-08-20 06:40:17 -0700764 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
765 /*
766 * In the pre-relocation phase, we only bind bridge devices to save
767 * precious memory space as on some platforms as that space is pretty
768 * limited (ie: using Cache As RAM).
769 */
770 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600771 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700772
Simon Glassaba92962015-07-06 16:47:44 -0600773 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800774 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
775 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600776 str = strdup(name);
777 if (!str)
778 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700779 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
780
Marek Vasut02e4d382018-10-10 21:27:06 +0200781 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
Simon Glassaba92962015-07-06 16:47:44 -0600782 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600783 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200784 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600785 return ret;
786 }
787 debug("%s: No match found: bound generic driver instead\n", __func__);
788
789 return 0;
790
791error:
792 debug("%s: No match found: error %d\n", __func__, ret);
793 return ret;
794}
795
Simon Glassff3e0772015-03-05 12:25:25 -0700796int pci_bind_bus_devices(struct udevice *bus)
797{
798 ulong vendor, device;
799 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800800 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700801 bool found_multi;
Suneel Garapatia3fac3f2019-10-23 18:40:36 -0700802 int ari_off;
Simon Glassff3e0772015-03-05 12:25:25 -0700803 int ret;
804
805 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800806 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
807 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900808 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800809 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700810 struct pci_child_platdata *pplat;
811 struct udevice *dev;
812 ulong class;
813
Bin Meng64e45f72018-08-03 01:14:37 -0700814 if (!PCI_FUNC(bdf))
815 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800816 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700817 continue;
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800818
Simon Glassff3e0772015-03-05 12:25:25 -0700819 /* Check only the first access, we don't expect problems */
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800820 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
821 PCI_SIZE_16);
Simon Glassff3e0772015-03-05 12:25:25 -0700822 if (ret)
823 goto error;
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800824
Simon Glassff3e0772015-03-05 12:25:25 -0700825 if (vendor == 0xffff || vendor == 0x0000)
826 continue;
827
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800828 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
829 &header_type, PCI_SIZE_8);
830
Bin Meng4d8615c2015-07-19 00:20:04 +0800831 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700832 found_multi = header_type & 0x80;
833
Simon Glass09115692019-09-25 08:56:12 -0600834 debug("%s: bus %d/%s: found device %x, function %d", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800835 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
836 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700837 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800838 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600839 PCI_SIZE_32);
840 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700841
842 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800843 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glass09115692019-09-25 08:56:12 -0600844 debug(": find ret=%d\n", ret);
Simon Glassff3e0772015-03-05 12:25:25 -0700845
Simon Glass8bd42522015-11-29 13:18:09 -0700846 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700847 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600848 struct pci_device_id find_id;
849 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700850
Simon Glassaba92962015-07-06 16:47:44 -0600851 memset(&find_id, '\0', sizeof(find_id));
852 find_id.vendor = vendor;
853 find_id.device = device;
854 find_id.class = class;
855 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800856 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600857 PCI_SUBSYSTEM_VENDOR_ID,
858 &val, PCI_SIZE_32);
859 find_id.subvendor = val & 0xffff;
860 find_id.subdevice = val >> 16;
861 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800862 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600863 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700864 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600865 if (ret == -EPERM)
866 continue;
867 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700868 return ret;
869
870 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600871 pplat = dev_get_parent_platdata(dev);
872 pplat->devfn = PCI_MASK_BUS(bdf);
873 pplat->vendor = vendor;
874 pplat->device = device;
875 pplat->class = class;
Suneel Garapatia3fac3f2019-10-23 18:40:36 -0700876
877 if (IS_ENABLED(CONFIG_PCI_ARID)) {
878 ari_off = dm_pci_find_ext_capability(dev,
879 PCI_EXT_CAP_ID_ARI);
880 if (ari_off) {
881 u16 ari_cap;
882
883 /*
884 * Read Next Function number in ARI Cap
885 * Register
886 */
887 dm_pci_read_config16(dev, ari_off + 4,
888 &ari_cap);
889 /*
890 * Update next scan on this function number,
891 * subtract 1 in BDF to satisfy loop increment.
892 */
893 if (ari_cap & 0xff00) {
894 bdf = PCI_BDF(PCI_BUS(bdf),
895 PCI_DEV(ari_cap),
896 PCI_FUNC(ari_cap));
897 bdf = bdf - 0x100;
898 }
899 }
900 }
Simon Glassff3e0772015-03-05 12:25:25 -0700901 }
902
903 return 0;
904error:
905 printf("Cannot read bus configuration: %d\n", ret);
906
907 return ret;
908}
909
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700910static void decode_regions(struct pci_controller *hose, ofnode parent_node,
911 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700912{
913 int pci_addr_cells, addr_cells, size_cells;
914 int cells_per_record;
Stefan Roesedfaf6a52020-08-12 11:55:46 +0200915 struct bd_info *bd;
Simon Glassff3e0772015-03-05 12:25:25 -0700916 const u32 *prop;
Stefan Roesee0024742020-07-23 16:34:10 +0200917 int max_regions;
Simon Glassff3e0772015-03-05 12:25:25 -0700918 int len;
919 int i;
920
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900921 prop = ofnode_get_property(node, "ranges", &len);
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700922 if (!prop) {
923 debug("%s: Cannot decode regions\n", __func__);
924 return;
925 }
926
Simon Glass878d68c2017-06-12 06:21:31 -0600927 pci_addr_cells = ofnode_read_simple_addr_cells(node);
928 addr_cells = ofnode_read_simple_addr_cells(parent_node);
929 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700930
931 /* PCI addresses are always 3-cells */
932 len /= sizeof(u32);
933 cells_per_record = pci_addr_cells + addr_cells + size_cells;
934 hose->region_count = 0;
935 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
936 cells_per_record);
Stefan Roesee0024742020-07-23 16:34:10 +0200937
938 /* Dynamically allocate the regions array */
939 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
940 hose->regions = (struct pci_region *)
941 calloc(1, max_regions * sizeof(struct pci_region));
942
943 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
Simon Glassff3e0772015-03-05 12:25:25 -0700944 u64 pci_addr, addr, size;
945 int space_code;
946 u32 flags;
947 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700948 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700949
950 if (len < cells_per_record)
951 break;
952 flags = fdt32_to_cpu(prop[0]);
953 space_code = (flags >> 24) & 3;
954 pci_addr = fdtdec_get_number(prop + 1, 2);
955 prop += pci_addr_cells;
956 addr = fdtdec_get_number(prop, addr_cells);
957 prop += addr_cells;
958 size = fdtdec_get_number(prop, size_cells);
959 prop += size_cells;
Masahiro Yamadadee37fc2018-08-06 20:47:40 +0900960 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
961 __func__, hose->region_count, pci_addr, addr, size, space_code);
Simon Glassff3e0772015-03-05 12:25:25 -0700962 if (space_code & 2) {
963 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
964 PCI_REGION_MEM;
965 } else if (space_code & 1) {
966 type = PCI_REGION_IO;
967 } else {
968 continue;
969 }
Tuomas Tynkkynen52ba9072018-05-14 18:47:50 +0300970
971 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
972 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
973 debug(" - beyond the 32-bit boundary, ignoring\n");
974 continue;
975 }
976
Simon Glass9526d832015-11-19 20:26:58 -0700977 pos = -1;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700978 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
979 for (i = 0; i < hose->region_count; i++) {
980 if (hose->regions[i].flags == type)
981 pos = i;
982 }
Simon Glass9526d832015-11-19 20:26:58 -0700983 }
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700984
Simon Glass9526d832015-11-19 20:26:58 -0700985 if (pos == -1)
986 pos = hose->region_count++;
987 debug(" - type=%d, pos=%d\n", type, pos);
988 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700989 }
990
991 /* Add a region for our local memory */
Stefan Roesedfaf6a52020-08-12 11:55:46 +0200992 bd = gd->bd;
Bin Meng1eaf7802018-03-27 00:46:05 -0700993 if (!bd)
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700994 return;
Bin Meng1eaf7802018-03-27 00:46:05 -0700995
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100996 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
997 if (bd->bi_dram[i].size) {
998 pci_set_region(hose->regions + hose->region_count++,
999 bd->bi_dram[i].start,
1000 bd->bi_dram[i].start,
1001 bd->bi_dram[i].size,
1002 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1003 }
1004 }
Simon Glassff3e0772015-03-05 12:25:25 -07001005
Christian Gmeinerf2825f62018-06-10 06:25:05 -07001006 return;
Simon Glassff3e0772015-03-05 12:25:25 -07001007}
1008
1009static int pci_uclass_pre_probe(struct udevice *bus)
1010{
1011 struct pci_controller *hose;
Simon Glassff3e0772015-03-05 12:25:25 -07001012
1013 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
1014 bus->parent->name);
1015 hose = bus->uclass_priv;
1016
1017 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +01001018 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -07001019 hose->ctlr = bus;
Christian Gmeinerf2825f62018-06-10 06:25:05 -07001020 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -07001021 } else {
1022 struct pci_controller *parent_hose;
1023
1024 parent_hose = dev_get_uclass_priv(bus->parent);
1025 hose->ctlr = parent_hose->bus;
1026 }
1027 hose->bus = bus;
1028 hose->first_busno = bus->seq;
1029 hose->last_busno = bus->seq;
Suneel Garapatif0c36922020-05-04 21:25:25 -07001030 if (dev_of_valid(bus)) {
1031 hose->skip_auto_config_until_reloc =
1032 dev_read_bool(bus,
1033 "u-boot,skip-auto-config-until-reloc");
1034 }
Simon Glassff3e0772015-03-05 12:25:25 -07001035
1036 return 0;
1037}
1038
1039static int pci_uclass_post_probe(struct udevice *bus)
1040{
Simon Glass2206ac22019-12-06 21:41:37 -07001041 struct pci_controller *hose = dev_get_uclass_priv(bus);
Simon Glassff3e0772015-03-05 12:25:25 -07001042 int ret;
1043
Simon Glassff3e0772015-03-05 12:25:25 -07001044 debug("%s: probing bus %d\n", __func__, bus->seq);
1045 ret = pci_bind_bus_devices(bus);
1046 if (ret)
1047 return ret;
1048
Simon Glassf1f44382020-04-26 09:12:56 -06001049 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
Simon Glass2206ac22019-12-06 21:41:37 -07001050 (!hose->skip_auto_config_until_reloc ||
1051 (gd->flags & GD_FLG_RELOC))) {
1052 ret = pci_auto_config_devices(bus);
1053 if (ret < 0)
1054 return log_msg_ret("pci auto-config", ret);
1055 }
Simon Glassff3e0772015-03-05 12:25:25 -07001056
Bin Meng348b7442015-08-20 06:40:23 -07001057#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1058 /*
1059 * Per Intel FSP specification, we should call FSP notify API to
1060 * inform FSP that PCI enumeration has been done so that FSP will
1061 * do any necessary initialization as required by the chipset's
1062 * BIOS Writer's Guide (BWG).
1063 *
1064 * Unfortunately we have to put this call here as with driver model,
1065 * the enumeration is all done on a lazy basis as needed, so until
1066 * something is touched on PCI it won't happen.
1067 *
1068 * Note we only call this 1) after U-Boot is relocated, and 2)
1069 * root bus has finished probing.
1070 */
Simon Glassf1f44382020-04-26 09:12:56 -06001071 if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
Bin Meng348b7442015-08-20 06:40:23 -07001072 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -06001073 if (ret)
1074 return ret;
1075 }
Bin Meng348b7442015-08-20 06:40:23 -07001076#endif
1077
Simon Glass4d214552015-09-08 17:52:47 -06001078 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -07001079}
1080
1081static int pci_uclass_child_post_bind(struct udevice *dev)
1082{
1083 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -07001084
Simon Glassbf501592017-05-18 20:09:51 -06001085 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -07001086 return 0;
1087
Simon Glassff3e0772015-03-05 12:25:25 -07001088 pplat = dev_get_parent_platdata(dev);
Bin Meng1f6b08b2018-08-03 01:14:36 -07001089
1090 /* Extract vendor id and device id if available */
1091 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1092
1093 /* Extract the devfn from fdt_pci_addr */
Stefan Roeseb5214202019-01-25 11:52:42 +01001094 pplat->devfn = pci_get_devfn(dev);
Simon Glassff3e0772015-03-05 12:25:25 -07001095
1096 return 0;
1097}
1098
Simon Glassc4e72c42020-01-27 08:49:37 -07001099static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
Bin Meng4d8615c2015-07-19 00:20:04 +08001100 uint offset, ulong *valuep,
1101 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001102{
1103 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001104
1105 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1106}
1107
Bin Meng4d8615c2015-07-19 00:20:04 +08001108static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1109 uint offset, ulong value,
1110 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001111{
1112 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001113
1114 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1115}
1116
Simon Glass76c3fbc2015-08-10 07:05:04 -06001117static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1118{
1119 struct udevice *dev;
1120 int ret = 0;
1121
1122 /*
1123 * Scan through all the PCI controllers. On x86 there will only be one
1124 * but that is not necessarily true on other hardware.
1125 */
1126 do {
1127 device_find_first_child(bus, &dev);
1128 if (dev) {
1129 *devp = dev;
1130 return 0;
1131 }
1132 ret = uclass_next_device(&bus);
1133 if (ret)
1134 return ret;
1135 } while (bus);
1136
1137 return 0;
1138}
1139
1140int pci_find_next_device(struct udevice **devp)
1141{
1142 struct udevice *child = *devp;
1143 struct udevice *bus = child->parent;
1144 int ret;
1145
1146 /* First try all the siblings */
1147 *devp = NULL;
1148 while (child) {
1149 device_find_next_child(&child);
1150 if (child) {
1151 *devp = child;
1152 return 0;
1153 }
1154 }
1155
1156 /* We ran out of siblings. Try the next bus */
1157 ret = uclass_next_device(&bus);
1158 if (ret)
1159 return ret;
1160
1161 return bus ? skip_to_next_device(bus, devp) : 0;
1162}
1163
1164int pci_find_first_device(struct udevice **devp)
1165{
1166 struct udevice *bus;
1167 int ret;
1168
1169 *devp = NULL;
1170 ret = uclass_first_device(UCLASS_PCI, &bus);
1171 if (ret)
1172 return ret;
1173
1174 return skip_to_next_device(bus, devp);
1175}
1176
Simon Glass9289db62015-11-19 20:26:59 -07001177ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1178{
1179 switch (size) {
1180 case PCI_SIZE_8:
1181 return (value >> ((offset & 3) * 8)) & 0xff;
1182 case PCI_SIZE_16:
1183 return (value >> ((offset & 2) * 8)) & 0xffff;
1184 default:
1185 return value;
1186 }
1187}
1188
1189ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1190 enum pci_size_t size)
1191{
1192 uint off_mask;
1193 uint val_mask, shift;
1194 ulong ldata, mask;
1195
1196 switch (size) {
1197 case PCI_SIZE_8:
1198 off_mask = 3;
1199 val_mask = 0xff;
1200 break;
1201 case PCI_SIZE_16:
1202 off_mask = 2;
1203 val_mask = 0xffff;
1204 break;
1205 default:
1206 return value;
1207 }
1208 shift = (offset & off_mask) * 8;
1209 ldata = (value & val_mask) << shift;
1210 mask = val_mask << shift;
1211 value = (old & ~mask) | ldata;
1212
1213 return value;
1214}
1215
Rayagonda Kokatanur143eb5b2020-05-12 13:29:49 +05301216int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1217{
1218 int pci_addr_cells, addr_cells, size_cells;
1219 int cells_per_record;
1220 const u32 *prop;
1221 int len;
1222 int i = 0;
1223
1224 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1225 if (!prop) {
1226 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1227 dev->name);
1228 return -EINVAL;
1229 }
1230
1231 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1232 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1233 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1234
1235 /* PCI addresses are always 3-cells */
1236 len /= sizeof(u32);
1237 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1238 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1239 cells_per_record);
1240
1241 while (len) {
1242 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1243 prop += pci_addr_cells;
1244 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1245 prop += addr_cells;
1246 memp->size = fdtdec_get_number(prop, size_cells);
1247 prop += size_cells;
1248
1249 if (i == index)
1250 return 0;
1251 i++;
1252 len -= cells_per_record;
1253 }
1254
1255 return -EINVAL;
1256}
1257
Simon Glassf9260332015-11-19 20:27:01 -07001258int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1259 struct pci_region **memp, struct pci_region **prefp)
1260{
1261 struct udevice *bus = pci_get_controller(dev);
1262 struct pci_controller *hose = dev_get_uclass_priv(bus);
1263 int i;
1264
1265 *iop = NULL;
1266 *memp = NULL;
1267 *prefp = NULL;
1268 for (i = 0; i < hose->region_count; i++) {
1269 switch (hose->regions[i].flags) {
1270 case PCI_REGION_IO:
1271 if (!*iop || (*iop)->size < hose->regions[i].size)
1272 *iop = hose->regions + i;
1273 break;
1274 case PCI_REGION_MEM:
1275 if (!*memp || (*memp)->size < hose->regions[i].size)
1276 *memp = hose->regions + i;
1277 break;
1278 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1279 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1280 *prefp = hose->regions + i;
1281 break;
1282 }
1283 }
1284
1285 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1286}
1287
Simon Glass194fca92020-01-27 08:49:38 -07001288u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
Simon Glassbab17cf2015-11-29 13:17:53 -07001289{
1290 u32 addr;
1291 int bar;
1292
1293 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1294 dm_pci_read_config32(dev, bar, &addr);
Simon Glass9ece4b02020-04-09 10:27:36 -06001295
1296 /*
1297 * If we get an invalid address, return this so that comparisons with
1298 * FDT_ADDR_T_NONE work correctly
1299 */
1300 if (addr == 0xffffffff)
1301 return addr;
1302 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
Simon Glassbab17cf2015-11-29 13:17:53 -07001303 return addr & PCI_BASE_ADDRESS_IO_MASK;
1304 else
1305 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1306}
1307
Simon Glass9d731c82016-01-18 20:19:15 -07001308void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1309{
1310 int bar;
1311
1312 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1313 dm_pci_write_config32(dev, bar, addr);
1314}
1315
Simon Glass21d1fe72015-11-29 13:18:03 -07001316static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1317 pci_addr_t bus_addr, unsigned long flags,
1318 unsigned long skip_mask, phys_addr_t *pa)
1319{
1320 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1321 struct pci_region *res;
1322 int i;
1323
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001324 if (hose->region_count == 0) {
1325 *pa = bus_addr;
1326 return 0;
1327 }
1328
Simon Glass21d1fe72015-11-29 13:18:03 -07001329 for (i = 0; i < hose->region_count; i++) {
1330 res = &hose->regions[i];
1331
1332 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1333 continue;
1334
1335 if (res->flags & skip_mask)
1336 continue;
1337
1338 if (bus_addr >= res->bus_start &&
1339 (bus_addr - res->bus_start) < res->size) {
1340 *pa = (bus_addr - res->bus_start + res->phys_start);
1341 return 0;
1342 }
1343 }
1344
1345 return 1;
1346}
1347
1348phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1349 unsigned long flags)
1350{
1351 phys_addr_t phys_addr = 0;
1352 struct udevice *ctlr;
1353 int ret;
1354
1355 /* The root controller has the region information */
1356 ctlr = pci_get_controller(dev);
1357
1358 /*
1359 * if PCI_REGION_MEM is set we do a two pass search with preference
1360 * on matches that don't have PCI_REGION_SYS_MEMORY set
1361 */
1362 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1363 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1364 flags, PCI_REGION_SYS_MEMORY,
1365 &phys_addr);
1366 if (!ret)
1367 return phys_addr;
1368 }
1369
1370 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1371
1372 if (ret)
1373 puts("pci_hose_bus_to_phys: invalid physical address\n");
1374
1375 return phys_addr;
1376}
1377
1378int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1379 unsigned long flags, unsigned long skip_mask,
1380 pci_addr_t *ba)
1381{
1382 struct pci_region *res;
1383 struct udevice *ctlr;
1384 pci_addr_t bus_addr;
1385 int i;
1386 struct pci_controller *hose;
1387
1388 /* The root controller has the region information */
1389 ctlr = pci_get_controller(dev);
1390 hose = dev_get_uclass_priv(ctlr);
1391
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001392 if (hose->region_count == 0) {
1393 *ba = phys_addr;
1394 return 0;
1395 }
1396
Simon Glass21d1fe72015-11-29 13:18:03 -07001397 for (i = 0; i < hose->region_count; i++) {
1398 res = &hose->regions[i];
1399
1400 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1401 continue;
1402
1403 if (res->flags & skip_mask)
1404 continue;
1405
1406 bus_addr = phys_addr - res->phys_start + res->bus_start;
1407
1408 if (bus_addr >= res->bus_start &&
1409 (bus_addr - res->bus_start) < res->size) {
1410 *ba = bus_addr;
1411 return 0;
1412 }
1413 }
1414
1415 return 1;
1416}
1417
1418pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1419 unsigned long flags)
1420{
1421 pci_addr_t bus_addr = 0;
1422 int ret;
1423
1424 /*
1425 * if PCI_REGION_MEM is set we do a two pass search with preference
1426 * on matches that don't have PCI_REGION_SYS_MEMORY set
1427 */
1428 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1429 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1430 PCI_REGION_SYS_MEMORY, &bus_addr);
1431 if (!ret)
1432 return bus_addr;
1433 }
1434
1435 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1436
1437 if (ret)
1438 puts("pci_hose_phys_to_bus: invalid physical address\n");
1439
1440 return bus_addr;
1441}
1442
Suneel Garapati51eeae92019-10-19 16:34:16 -07001443static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1444 struct pci_child_platdata *pdata)
1445{
1446 phys_addr_t addr = 0;
1447
1448 /*
1449 * In the case of a Virtual Function device using BAR
1450 * base and size, add offset for VFn BAR(1, 2, 3...n)
1451 */
1452 if (pdata->is_virtfn) {
1453 size_t sz;
1454 u32 ea_entry;
1455
1456 /* MaxOffset, 1st DW */
1457 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1458 sz = ea_entry & PCI_EA_FIELD_MASK;
1459 /* Fill up lower 2 bits */
1460 sz |= (~PCI_EA_FIELD_MASK);
1461
1462 if (ea_entry & PCI_EA_IS_64) {
1463 /* MaxOffset 2nd DW */
1464 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1465 sz |= ((u64)ea_entry) << 32;
1466 }
1467
1468 addr = (pdata->virtid - 1) * (sz + 1);
1469 }
1470
1471 return addr;
1472}
1473
Alex Marginean0b143d82019-06-07 11:24:23 +03001474static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
Suneel Garapati51eeae92019-10-19 16:34:16 -07001475 int ea_off, struct pci_child_platdata *pdata)
Alex Marginean0b143d82019-06-07 11:24:23 +03001476{
1477 int ea_cnt, i, entry_size;
1478 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1479 u32 ea_entry;
1480 phys_addr_t addr;
1481
Suneel Garapati51eeae92019-10-19 16:34:16 -07001482 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1483 /*
1484 * In the case of a Virtual Function device, device is
1485 * Physical function, so pdata will point to required VF
1486 * specific data.
1487 */
1488 if (pdata->is_virtfn)
1489 bar_id += PCI_EA_BEI_VF_BAR0;
1490 }
1491
Alex Marginean0b143d82019-06-07 11:24:23 +03001492 /* EA capability structure header */
1493 dm_pci_read_config32(dev, ea_off, &ea_entry);
1494 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1495 ea_off += PCI_EA_FIRST_ENT;
1496
1497 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1498 /* Entry header */
1499 dm_pci_read_config32(dev, ea_off, &ea_entry);
1500 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1501
1502 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1503 continue;
1504
1505 /* Base address, 1st DW */
1506 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1507 addr = ea_entry & PCI_EA_FIELD_MASK;
1508 if (ea_entry & PCI_EA_IS_64) {
1509 /* Base address, 2nd DW, skip over 4B MaxOffset */
1510 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1511 addr |= ((u64)ea_entry) << 32;
1512 }
1513
Suneel Garapati51eeae92019-10-19 16:34:16 -07001514 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1515 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1516
Alex Marginean0b143d82019-06-07 11:24:23 +03001517 /* size ignored for now */
Suneel Garapatib3699a12019-10-19 16:44:35 -07001518 return map_physmem(addr, 0, flags);
Alex Marginean0b143d82019-06-07 11:24:23 +03001519 }
1520
1521 return 0;
1522}
1523
Simon Glass21d1fe72015-11-29 13:18:03 -07001524void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1525{
Suneel Garapati51eeae92019-10-19 16:34:16 -07001526 struct pci_child_platdata *pdata = dev_get_parent_platdata(dev);
1527 struct udevice *udev = dev;
Simon Glass21d1fe72015-11-29 13:18:03 -07001528 pci_addr_t pci_bus_addr;
1529 u32 bar_response;
Alex Marginean0b143d82019-06-07 11:24:23 +03001530 int ea_off;
1531
Suneel Garapati51eeae92019-10-19 16:34:16 -07001532 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1533 /*
1534 * In case of Virtual Function devices, use PF udevice
1535 * as EA capability is defined in Physical Function
1536 */
1537 if (pdata->is_virtfn)
1538 udev = pdata->pfdev;
1539 }
1540
Alex Marginean0b143d82019-06-07 11:24:23 +03001541 /*
1542 * if the function supports Enhanced Allocation use that instead of
1543 * BARs
Suneel Garapati51eeae92019-10-19 16:34:16 -07001544 * Incase of virtual functions, pdata will help read VF BEI
1545 * and EA entry size.
Alex Marginean0b143d82019-06-07 11:24:23 +03001546 */
Suneel Garapati51eeae92019-10-19 16:34:16 -07001547 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
Alex Marginean0b143d82019-06-07 11:24:23 +03001548 if (ea_off)
Suneel Garapati51eeae92019-10-19 16:34:16 -07001549 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
Simon Glass21d1fe72015-11-29 13:18:03 -07001550
1551 /* read BAR address */
Suneel Garapati51eeae92019-10-19 16:34:16 -07001552 dm_pci_read_config32(udev, bar, &bar_response);
Simon Glass21d1fe72015-11-29 13:18:03 -07001553 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1554
1555 /*
1556 * Pass "0" as the length argument to pci_bus_to_virt. The arg
Suneel Garapatib3699a12019-10-19 16:44:35 -07001557 * isn't actually used on any platform because U-Boot assumes a static
Simon Glass21d1fe72015-11-29 13:18:03 -07001558 * linear mapping. In the future, this could read the BAR size
1559 * and pass that as the size if needed.
1560 */
Suneel Garapati51eeae92019-10-19 16:34:16 -07001561 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
Simon Glass21d1fe72015-11-29 13:18:03 -07001562}
1563
Bin Menga8c5f8d2018-10-15 02:21:21 -07001564static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
Bin Mengdac01fd2018-08-03 01:14:52 -07001565{
Bin Mengdac01fd2018-08-03 01:14:52 -07001566 int ttl = PCI_FIND_CAP_TTL;
1567 u8 id;
1568 u16 ent;
Bin Mengdac01fd2018-08-03 01:14:52 -07001569
1570 dm_pci_read_config8(dev, pos, &pos);
Bin Menga8c5f8d2018-10-15 02:21:21 -07001571
Bin Mengdac01fd2018-08-03 01:14:52 -07001572 while (ttl--) {
1573 if (pos < PCI_STD_HEADER_SIZEOF)
1574 break;
1575 pos &= ~3;
1576 dm_pci_read_config16(dev, pos, &ent);
1577
1578 id = ent & 0xff;
1579 if (id == 0xff)
1580 break;
1581 if (id == cap)
1582 return pos;
1583 pos = (ent >> 8);
1584 }
1585
1586 return 0;
1587}
1588
Bin Menga8c5f8d2018-10-15 02:21:21 -07001589int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1590{
1591 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1592 cap);
1593}
1594
1595int dm_pci_find_capability(struct udevice *dev, int cap)
1596{
1597 u16 status;
1598 u8 header_type;
1599 u8 pos;
1600
1601 dm_pci_read_config16(dev, PCI_STATUS, &status);
1602 if (!(status & PCI_STATUS_CAP_LIST))
1603 return 0;
1604
1605 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1606 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1607 pos = PCI_CB_CAPABILITY_LIST;
1608 else
1609 pos = PCI_CAPABILITY_LIST;
1610
1611 return _dm_pci_find_next_capability(dev, pos, cap);
1612}
1613
1614int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
Bin Mengdac01fd2018-08-03 01:14:52 -07001615{
1616 u32 header;
1617 int ttl;
1618 int pos = PCI_CFG_SPACE_SIZE;
1619
1620 /* minimum 8 bytes per capability */
1621 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1622
Bin Menga8c5f8d2018-10-15 02:21:21 -07001623 if (start)
1624 pos = start;
1625
Bin Mengdac01fd2018-08-03 01:14:52 -07001626 dm_pci_read_config32(dev, pos, &header);
1627 /*
1628 * If we have no capabilities, this is indicated by cap ID,
1629 * cap version and next pointer all being 0.
1630 */
1631 if (header == 0)
1632 return 0;
1633
1634 while (ttl--) {
1635 if (PCI_EXT_CAP_ID(header) == cap)
1636 return pos;
1637
1638 pos = PCI_EXT_CAP_NEXT(header);
1639 if (pos < PCI_CFG_SPACE_SIZE)
1640 break;
1641
1642 dm_pci_read_config32(dev, pos, &header);
1643 }
1644
1645 return 0;
1646}
1647
Bin Menga8c5f8d2018-10-15 02:21:21 -07001648int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1649{
1650 return dm_pci_find_next_ext_capability(dev, 0, cap);
1651}
1652
Alex Margineanb8e1f822019-06-07 11:24:25 +03001653int dm_pci_flr(struct udevice *dev)
1654{
1655 int pcie_off;
1656 u32 cap;
1657
1658 /* look for PCI Express Capability */
1659 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1660 if (!pcie_off)
1661 return -ENOENT;
1662
1663 /* check FLR capability */
1664 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1665 if (!(cap & PCI_EXP_DEVCAP_FLR))
1666 return -ENOENT;
1667
1668 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1669 PCI_EXP_DEVCTL_BCR_FLR);
1670
1671 /* wait 100ms, per PCI spec */
1672 mdelay(100);
1673
1674 return 0;
1675}
1676
Suneel Garapatib8852dc2019-10-19 16:07:20 -07001677#if defined(CONFIG_PCI_SRIOV)
1678int pci_sriov_init(struct udevice *pdev, int vf_en)
1679{
1680 u16 vendor, device;
1681 struct udevice *bus;
1682 struct udevice *dev;
1683 pci_dev_t bdf;
1684 u16 ctrl;
1685 u16 num_vfs;
1686 u16 total_vf;
1687 u16 vf_offset;
1688 u16 vf_stride;
1689 int vf, ret;
1690 int pos;
1691
1692 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1693 if (!pos) {
1694 debug("Error: SRIOV capability not found\n");
1695 return -ENOENT;
1696 }
1697
1698 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1699
1700 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1701 if (vf_en > total_vf)
1702 vf_en = total_vf;
1703 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1704
1705 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1706 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1707
1708 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1709 if (num_vfs > vf_en)
1710 num_vfs = vf_en;
1711
1712 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1713 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1714
1715 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1716 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1717
1718 bdf = dm_pci_get_bdf(pdev);
1719
1720 pci_get_bus(PCI_BUS(bdf), &bus);
1721
1722 if (!bus)
1723 return -ENODEV;
1724
1725 bdf += PCI_BDF(0, 0, vf_offset);
1726
1727 for (vf = 0; vf < num_vfs; vf++) {
1728 struct pci_child_platdata *pplat;
1729 ulong class;
1730
1731 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1732 &class, PCI_SIZE_16);
1733
1734 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1735 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1736
1737 /* Find this device in the device tree */
1738 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1739
1740 if (ret == -ENODEV) {
1741 struct pci_device_id find_id;
1742
1743 memset(&find_id, '\0', sizeof(find_id));
1744 find_id.vendor = vendor;
1745 find_id.device = device;
1746 find_id.class = class;
1747
1748 ret = pci_find_and_bind_driver(bus, &find_id,
1749 bdf, &dev);
1750
1751 if (ret)
1752 return ret;
1753 }
1754
1755 /* Update the platform data */
1756 pplat = dev_get_parent_platdata(dev);
1757 pplat->devfn = PCI_MASK_BUS(bdf);
1758 pplat->vendor = vendor;
1759 pplat->device = device;
1760 pplat->class = class;
1761 pplat->is_virtfn = true;
1762 pplat->pfdev = pdev;
1763 pplat->virtid = vf * vf_stride + vf_offset;
1764
1765 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1766 __func__, dev->seq, dev->name, PCI_DEV(bdf),
1767 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1768 bdf += PCI_BDF(0, 0, vf_stride);
1769 }
1770
1771 return 0;
1772}
1773
1774int pci_sriov_get_totalvfs(struct udevice *pdev)
1775{
1776 u16 total_vf;
1777 int pos;
1778
1779 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1780 if (!pos) {
1781 debug("Error: SRIOV capability not found\n");
1782 return -ENOENT;
1783 }
1784
1785 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1786
1787 return total_vf;
1788}
1789#endif /* SRIOV */
1790
Simon Glassff3e0772015-03-05 12:25:25 -07001791UCLASS_DRIVER(pci) = {
1792 .id = UCLASS_PCI,
1793 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001794 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001795 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001796 .pre_probe = pci_uclass_pre_probe,
1797 .post_probe = pci_uclass_post_probe,
1798 .child_post_bind = pci_uclass_child_post_bind,
1799 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1800 .per_child_platdata_auto_alloc_size =
1801 sizeof(struct pci_child_platdata),
1802};
1803
1804static const struct dm_pci_ops pci_bridge_ops = {
1805 .read_config = pci_bridge_read_config,
1806 .write_config = pci_bridge_write_config,
1807};
1808
1809static const struct udevice_id pci_bridge_ids[] = {
1810 { .compatible = "pci-bridge" },
1811 { }
1812};
1813
1814U_BOOT_DRIVER(pci_bridge_drv) = {
1815 .name = "pci_bridge_drv",
1816 .id = UCLASS_PCI,
1817 .of_match = pci_bridge_ids,
1818 .ops = &pci_bridge_ops,
1819};
1820
1821UCLASS_DRIVER(pci_generic) = {
1822 .id = UCLASS_PCI_GENERIC,
1823 .name = "pci_generic",
1824};
1825
1826static const struct udevice_id pci_generic_ids[] = {
1827 { .compatible = "pci-generic" },
1828 { }
1829};
1830
1831U_BOOT_DRIVER(pci_generic_drv) = {
1832 .name = "pci_generic_drv",
1833 .id = UCLASS_PCI_GENERIC,
1834 .of_match = pci_generic_ids,
1835};
Stephen Warrene578b922016-01-26 11:10:11 -07001836
1837void pci_init(void)
1838{
1839 struct udevice *bus;
1840
1841 /*
1842 * Enumerate all known controller devices. Enumeration has the side-
1843 * effect of probing them, so PCIe devices will be enumerated too.
1844 */
Marek BehĂșn60ee6092019-05-21 12:04:31 +02001845 for (uclass_first_device_check(UCLASS_PCI, &bus);
Stephen Warrene578b922016-01-26 11:10:11 -07001846 bus;
Marek BehĂșn60ee6092019-05-21 12:04:31 +02001847 uclass_next_device_check(&bus)) {
Stephen Warrene578b922016-01-26 11:10:11 -07001848 ;
1849 }
1850}