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Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +02001/*
2 * WORK Microwave work_92105 board configuration file
3 *
4 * (C) Copyright 2014 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_WORK_92105_H__
11#define __CONFIG_WORK_92105_H__
12
13/* SoC and board defines */
14#include <linux/sizes.h>
15#include <asm/arch/cpu.h>
16
17/*
18 * Define work_92105 machine type by hand -- done only for compatibility
19 * with original board code
20 */
Tom Rinicd7b6342017-01-25 20:42:38 -050021#define CONFIG_MACH_TYPE 736
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020022
23#define CONFIG_SYS_ICACHE_OFF
24#define CONFIG_SYS_DCACHE_OFF
25#if !defined(CONFIG_SPL_BUILD)
26#define CONFIG_SKIP_LOWLEVEL_INIT
27#endif
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020028#define CONFIG_BOARD_EARLY_INIT_R
29
30/* generate LPC32XX-specific SPL image */
31#define CONFIG_LPC32XX_SPL
32
33/*
34 * Memory configurations
35 */
36#define CONFIG_NR_DRAM_BANKS 1
37#define CONFIG_SYS_MALLOC_LEN SZ_1M
38#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
39#define CONFIG_SYS_SDRAM_SIZE SZ_128M
40#define CONFIG_SYS_TEXT_BASE 0x80100000
41#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
42#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
43
44#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
45
46#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
47 - GENERATED_GBL_DATA_SIZE)
48
49/*
50 * Serial Driver
51 */
52#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020053
54/*
55 * Ethernet Driver
56 */
57
58#define CONFIG_PHY_SMSC
59#define CONFIG_LPC32XX_ETH
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020060#define CONFIG_PHY_ADDR 0
61#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020062/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
63
64/*
65 * I2C driver
66 */
67
68#define CONFIG_SYS_I2C_LPC32XX
69#define CONFIG_SYS_I2C
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020070#define CONFIG_SYS_I2C_SPEED 350000
71
72/*
73 * I2C EEPROM
74 */
75
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020076#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
77#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
78
79/*
80 * I2C RTC
81 */
82
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020083#define CONFIG_RTC_DS1374
84
85/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020086 * U-Boot General Configurations
87 */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020088#define CONFIG_SYS_LONGHELP
89#define CONFIG_SYS_CBSIZE 1024
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020090#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
91
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020092#define CONFIG_AUTO_COMPLETE
93#define CONFIG_CMDLINE_EDITING
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020094
95/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020096 * NAND chip timings for FIXME: which one?
97 */
98
99#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
100#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
101#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
102#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
103#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
104#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
105#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
106
107/*
108 * NAND
109 */
110
111/* driver configuration */
112#define CONFIG_SYS_NAND_SELF_INIT
113#define CONFIG_SYS_MAX_NAND_DEVICE 1
114#define CONFIG_SYS_MAX_NAND_CHIPS 1
115#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
116#define CONFIG_NAND_LPC32XX_MLC
117
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200118/*
119 * GPIO
120 */
121
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200122#define CONFIG_LPC32XX_GPIO
123
124/*
125 * SSP/SPI/DISPLAY
126 */
127
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200128#define CONFIG_LPC32XX_SSP
129#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200130/*
131 * Environment
132 */
133
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200134#define CONFIG_ENV_SIZE 0x00020000
135#define CONFIG_ENV_OFFSET 0x00100000
136#define CONFIG_ENV_OFFSET_REDUND 0x00120000
137#define CONFIG_ENV_ADDR 0x80000100
138
139/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200140 * Boot Linux
141 */
142#define CONFIG_CMDLINE_TAG
143#define CONFIG_SETUP_MEMORY_TAGS
144#define CONFIG_INITRD_TAG
145
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200146#define CONFIG_BOOTFILE "uImage"
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200147#define CONFIG_LOADADDR 0x80008000
148
149/*
150 * SPL
151 */
152
153/* SPL will be executed at offset 0 */
154#define CONFIG_SPL_TEXT_BASE 0x00000000
155/* SPL will use SRAM as stack */
156#define CONFIG_SPL_STACK 0x0000FFF8
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200157/* Use the framework and generic lib */
158#define CONFIG_SPL_FRAMEWORK
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200159/* SPL will use serial */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200160/* SPL will load U-Boot from NAND offset 0x40000 */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200161#define CONFIG_SPL_NAND_DRIVERS
162#define CONFIG_SPL_NAND_BASE
163#define CONFIG_SPL_NAND_BOOT
164#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
165#define CONFIG_SPL_PAD_TO 0x20000
166/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
167#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
168#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
169#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
170
171/*
172 * Include SoC specific configuration
173 */
174#include <asm/arch/config.h>
175
176#endif /* __CONFIG_WORK_92105_H__*/