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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05002/*
3 * RealTek PHY drivers
4 *
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +02005 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
Andy Fleming9082eea2011-04-07 21:56:05 -05006 * author Andy Fleming
Karsten Merker563d8d92016-03-21 20:29:07 +01007 * Copyright 2016 Karsten Merker <merker@debian.org>
Andy Fleming9082eea2011-04-07 21:56:05 -05008 */
Andy Fleming9082eea2011-04-07 21:56:05 -05009#include <common.h>
oliver@schinagl.nl020f6762016-11-08 17:38:57 +010010#include <linux/bitops.h>
Andy Fleming9082eea2011-04-07 21:56:05 -050011#include <phy.h>
12
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010013#define PHY_RTL8211x_FORCE_MASTER BIT(1)
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060014#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
Carlo Caioned47cfdb2019-01-24 08:54:37 +000015#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010016
Andy Fleming9082eea2011-04-07 21:56:05 -050017#define PHY_AUTONEGOTIATE_TIMEOUT 5000
18
Michael Haas525d1872016-03-25 18:22:50 +010019/* RTL8211x 1000BASE-T Control Register */
oliver@schinagl.nl020f6762016-11-08 17:38:57 +010020#define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
oliver@schinagl.nlcbe40e12016-11-08 17:38:58 +010021#define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
Michael Haas525d1872016-03-25 18:22:50 +010022
Bhupesh Sharmac624d162013-07-18 13:58:20 +053023/* RTL8211x PHY Status Register */
24#define MIIM_RTL8211x_PHY_STATUS 0x11
25#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
26#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
27#define MIIM_RTL8211x_PHYSTAT_100 0x4000
28#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
29#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
30#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
Andy Fleming9082eea2011-04-07 21:56:05 -050031
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +020032/* RTL8211x PHY Interrupt Enable Register */
33#define MIIM_RTL8211x_PHY_INER 0x12
34#define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
35#define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
36
37/* RTL8211x PHY Interrupt Status Register */
38#define MIIM_RTL8211x_PHY_INSR 0x13
Andy Fleming9082eea2011-04-07 21:56:05 -050039
Shengzhou Liu3d6af742015-03-12 18:54:59 +080040/* RTL8211F PHY Status Register */
41#define MIIM_RTL8211F_PHY_STATUS 0x1a
42#define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
43#define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
44#define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
45#define MIIM_RTL8211F_PHYSTAT_100 0x0010
46#define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
47#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
48#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
49
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060050#define MIIM_RTL8211E_CONFREG 0x1c
51#define MIIM_RTL8211E_CONFREG_TXD 0x0002
52#define MIIM_RTL8211E_CONFREG_RXD 0x0004
53#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
54
55#define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
56
Shengzhou Liu3d6af742015-03-12 18:54:59 +080057#define MIIM_RTL8211F_PAGE_SELECT 0x1f
Shengzhou Liu793ea942015-04-24 16:57:17 +080058#define MIIM_RTL8211F_TX_DELAY 0x100
Fugang Duane32e4d02020-05-03 22:41:16 +080059#define MIIM_RTL8211F_RX_DELAY 0x8
Shengzhou Liu90712742015-05-21 18:07:35 +080060#define MIIM_RTL8211F_LCR 0x10
Shengzhou Liu3d6af742015-03-12 18:54:59 +080061
Carlo Caionee57c9fd2019-01-16 11:34:50 +000062static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
63 int devaddr, int regnum)
64{
65 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
66 MIIM_RTL8211F_PAGE_SELECT);
67 int val;
68
69 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
70 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
71 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
72
73 return val;
74}
75
76static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
77 int devaddr, int regnum, u16 val)
78{
79 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
80 MIIM_RTL8211F_PAGE_SELECT);
81
82 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
83 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
84 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
85
86 return 0;
87}
88
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010089static int rtl8211b_probe(struct phy_device *phydev)
90{
91#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
92 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
93#endif
94
95 return 0;
96}
97
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060098static int rtl8211e_probe(struct phy_device *phydev)
99{
100#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
101 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
102#endif
103
104 return 0;
105}
106
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000107static int rtl8211f_probe(struct phy_device *phydev)
108{
109#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
110 phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
111#endif
112
113 return 0;
114}
115
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530116/* RealTek RTL8211x */
117static int rtl8211x_config(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500118{
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
120
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +0200121 /* mask interrupt at init; if the interrupt is
122 * needed indeed, it should be explicitly enabled
123 */
124 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
125 MIIM_RTL8211x_PHY_INTR_DIS);
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +0100126
127 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
128 unsigned int reg;
129
130 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
131 /* force manual master/slave configuration */
132 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
133 /* force master mode */
134 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
135 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
136 }
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -0600137 if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
138 unsigned int reg;
139
140 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
141 7);
142 phy_write(phydev, MDIO_DEVAD_NONE,
143 MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
144 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
145 /* Ensure both internal delays are turned off */
146 reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
147 /* Flip the magic undocumented bits */
148 reg |= MIIM_RTL8211E_CONFREG_MAGIC;
149 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
150 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
151 0);
152 }
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +0200153 /* read interrupt status just to clear it */
154 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
155
Andy Fleming9082eea2011-04-07 21:56:05 -0500156 genphy_config_aneg(phydev);
157
158 return 0;
159}
160
Shengzhou Liu793ea942015-04-24 16:57:17 +0800161static int rtl8211f_config(struct phy_device *phydev)
162{
163 u16 reg;
164
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000165 if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
166 unsigned int reg;
167
168 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
169 reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
170 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
171 }
172
Shengzhou Liu793ea942015-04-24 16:57:17 +0800173 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
174
Madalin Bucur05b29aa2017-08-18 11:35:24 +0300175 phy_write(phydev, MDIO_DEVAD_NONE,
176 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
177 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
178
179 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
180 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
181 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
Shengzhou Liu793ea942015-04-24 16:57:17 +0800182 reg |= MIIM_RTL8211F_TX_DELAY;
Madalin Bucur05b29aa2017-08-18 11:35:24 +0300183 else
184 reg &= ~MIIM_RTL8211F_TX_DELAY;
185
186 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
Fugang Duane32e4d02020-05-03 22:41:16 +0800187
188 /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
189 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
190 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
191 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
192 reg |= MIIM_RTL8211F_RX_DELAY;
193 else
194 reg &= ~MIIM_RTL8211F_RX_DELAY;
195 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
196
Madalin Bucur05b29aa2017-08-18 11:35:24 +0300197 /* restore to default page 0 */
198 phy_write(phydev, MDIO_DEVAD_NONE,
199 MIIM_RTL8211F_PAGE_SELECT, 0x0);
Shengzhou Liu793ea942015-04-24 16:57:17 +0800200
Shengzhou Liu90712742015-05-21 18:07:35 +0800201 /* Set green LED for Link, yellow LED for Active */
202 phy_write(phydev, MDIO_DEVAD_NONE,
203 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
204 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
205 phy_write(phydev, MDIO_DEVAD_NONE,
206 MIIM_RTL8211F_PAGE_SELECT, 0x0);
207
Shengzhou Liu793ea942015-04-24 16:57:17 +0800208 genphy_config_aneg(phydev);
209
210 return 0;
211}
212
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530213static int rtl8211x_parse_status(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500214{
215 unsigned int speed;
216 unsigned int mii_reg;
217
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530218 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
Andy Fleming9082eea2011-04-07 21:56:05 -0500219
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530220 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
Andy Fleming9082eea2011-04-07 21:56:05 -0500221 int i = 0;
222
223 /* in case of timeout ->link is cleared */
224 phydev->link = 1;
225 puts("Waiting for PHY realtime link");
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530226 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
Andy Fleming9082eea2011-04-07 21:56:05 -0500227 /* Timeout reached ? */
228 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
229 puts(" TIMEOUT !\n");
230 phydev->link = 0;
231 break;
232 }
233
234 if ((i++ % 1000) == 0)
235 putc('.');
236 udelay(1000); /* 1 ms */
237 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530238 MIIM_RTL8211x_PHY_STATUS);
Andy Fleming9082eea2011-04-07 21:56:05 -0500239 }
240 puts(" done\n");
241 udelay(500000); /* another 500 ms (results in faster booting) */
242 } else {
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530243 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
Andy Fleming9082eea2011-04-07 21:56:05 -0500244 phydev->link = 1;
245 else
246 phydev->link = 0;
247 }
248
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530249 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
Andy Fleming9082eea2011-04-07 21:56:05 -0500250 phydev->duplex = DUPLEX_FULL;
251 else
252 phydev->duplex = DUPLEX_HALF;
253
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530254 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
Andy Fleming9082eea2011-04-07 21:56:05 -0500255
256 switch (speed) {
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530257 case MIIM_RTL8211x_PHYSTAT_GBIT:
Andy Fleming9082eea2011-04-07 21:56:05 -0500258 phydev->speed = SPEED_1000;
259 break;
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530260 case MIIM_RTL8211x_PHYSTAT_100:
Andy Fleming9082eea2011-04-07 21:56:05 -0500261 phydev->speed = SPEED_100;
262 break;
263 default:
264 phydev->speed = SPEED_10;
265 }
266
267 return 0;
268}
269
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800270static int rtl8211f_parse_status(struct phy_device *phydev)
271{
272 unsigned int speed;
273 unsigned int mii_reg;
274 int i = 0;
275
276 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
277 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
278
279 phydev->link = 1;
280 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
281 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
282 puts(" TIMEOUT !\n");
283 phydev->link = 0;
284 break;
285 }
286
287 if ((i++ % 1000) == 0)
288 putc('.');
289 udelay(1000);
290 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
291 MIIM_RTL8211F_PHY_STATUS);
292 }
293
294 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
295 phydev->duplex = DUPLEX_FULL;
296 else
297 phydev->duplex = DUPLEX_HALF;
298
299 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
300
301 switch (speed) {
302 case MIIM_RTL8211F_PHYSTAT_GBIT:
303 phydev->speed = SPEED_1000;
304 break;
305 case MIIM_RTL8211F_PHYSTAT_100:
306 phydev->speed = SPEED_100;
307 break;
308 default:
309 phydev->speed = SPEED_10;
310 }
311
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800312 return 0;
313}
314
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530315static int rtl8211x_startup(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500316{
Michal Simekb733c272016-05-18 12:46:12 +0200317 int ret;
Andy Fleming9082eea2011-04-07 21:56:05 -0500318
Michal Simekb733c272016-05-18 12:46:12 +0200319 /* Read the Status (2x to make sure link is right) */
320 ret = genphy_update_link(phydev);
321 if (ret)
322 return ret;
323
324 return rtl8211x_parse_status(phydev);
Andy Fleming9082eea2011-04-07 21:56:05 -0500325}
326
Michal Simek6a10bc52016-02-13 10:31:32 +0100327static int rtl8211e_startup(struct phy_device *phydev)
328{
Michal Simekb733c272016-05-18 12:46:12 +0200329 int ret;
Michal Simek6a10bc52016-02-13 10:31:32 +0100330
Michal Simekb733c272016-05-18 12:46:12 +0200331 ret = genphy_update_link(phydev);
332 if (ret)
333 return ret;
334
335 return genphy_parse_link(phydev);
Michal Simek6a10bc52016-02-13 10:31:32 +0100336}
337
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800338static int rtl8211f_startup(struct phy_device *phydev)
339{
Michal Simekb733c272016-05-18 12:46:12 +0200340 int ret;
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800341
Michal Simekb733c272016-05-18 12:46:12 +0200342 /* Read the Status (2x to make sure link is right) */
343 ret = genphy_update_link(phydev);
344 if (ret)
345 return ret;
346 /* Read the Status (2x to make sure link is right) */
347
348 return rtl8211f_parse_status(phydev);
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800349}
350
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530351/* Support for RTL8211B PHY */
Andy Fleming9082eea2011-04-07 21:56:05 -0500352static struct phy_driver RTL8211B_driver = {
353 .name = "RealTek RTL8211B",
Karsten Merker563d8d92016-03-21 20:29:07 +0100354 .uid = 0x1cc912,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530355 .mask = 0xffffff,
Andy Fleming9082eea2011-04-07 21:56:05 -0500356 .features = PHY_GBIT_FEATURES,
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +0100357 .probe = &rtl8211b_probe,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530358 .config = &rtl8211x_config,
359 .startup = &rtl8211x_startup,
360 .shutdown = &genphy_shutdown,
361};
362
363/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
364static struct phy_driver RTL8211E_driver = {
365 .name = "RealTek RTL8211E",
366 .uid = 0x1cc915,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530367 .mask = 0xffffff,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530368 .features = PHY_GBIT_FEATURES,
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -0600369 .probe = &rtl8211e_probe,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530370 .config = &rtl8211x_config,
Michal Simek6a10bc52016-02-13 10:31:32 +0100371 .startup = &rtl8211e_startup,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530372 .shutdown = &genphy_shutdown,
373};
374
375/* Support for RTL8211DN PHY */
376static struct phy_driver RTL8211DN_driver = {
377 .name = "RealTek RTL8211DN",
378 .uid = 0x1cc914,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530379 .mask = 0xffffff,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530380 .features = PHY_GBIT_FEATURES,
381 .config = &rtl8211x_config,
382 .startup = &rtl8211x_startup,
Andy Fleming9082eea2011-04-07 21:56:05 -0500383 .shutdown = &genphy_shutdown,
384};
385
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800386/* Support for RTL8211F PHY */
387static struct phy_driver RTL8211F_driver = {
388 .name = "RealTek RTL8211F",
389 .uid = 0x1cc916,
390 .mask = 0xffffff,
391 .features = PHY_GBIT_FEATURES,
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000392 .probe = &rtl8211f_probe,
Shengzhou Liu793ea942015-04-24 16:57:17 +0800393 .config = &rtl8211f_config,
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800394 .startup = &rtl8211f_startup,
395 .shutdown = &genphy_shutdown,
Carlo Caionee57c9fd2019-01-16 11:34:50 +0000396 .readext = &rtl8211f_phy_extread,
397 .writeext = &rtl8211f_phy_extwrite,
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800398};
399
Andy Fleming9082eea2011-04-07 21:56:05 -0500400int phy_realtek_init(void)
401{
402 phy_register(&RTL8211B_driver);
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530403 phy_register(&RTL8211E_driver);
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800404 phy_register(&RTL8211F_driver);
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530405 phy_register(&RTL8211DN_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500406
407 return 0;
408}