blob: 74fb528d2e9771f141db93bcdbc8615db8d42210 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09002/*
3 * Configuation settings for the sh7753evb board
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09006 */
7
8#ifndef __SH7753EVB_H
9#define __SH7753EVB_H
10
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090011#define CONFIG_CPU_SH7753 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090012
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020013#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090014
15/* MEMORY */
16#define SH7753EVB_SDRAM_BASE (0x40000000)
17#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
18
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090019#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090020#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
21
22/* SCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090023#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090024
25#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
26#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
27 480 * 1024 * 1024)
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090028#undef CONFIG_SYS_LOADS_BAUD_CHANGE
29
30#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
31#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
32#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
33 128 * 1024 * 1024)
34
35#define CONFIG_SYS_MONITOR_BASE 0x00000000
36#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
37#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
38#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
39
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090040/* Ether */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090041#define CONFIG_SH_ETHER_USE_PORT 0
42#define CONFIG_SH_ETHER_PHY_ADDR 18
43#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
44#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090045#define CONFIG_BITBANGMII_MULTI
46#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090047
48#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
49#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
50#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
51#define SH7753EVB_ETHERNET_MAC_SIZE 17
52#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090053
54/* SPI */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090055#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090056
57/* MMCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090058#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
59#define CONFIG_SH_MMCIF_CLK 48000000
60
61/* ENV setting */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090062#define CONFIG_ENV_OVERWRITE 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090063#define CONFIG_EXTRA_ENV_SETTINGS \
64 "netboot=bootp; bootm\0"
65
66/* Board Clock */
67#define CONFIG_SYS_CLK_FREQ 48000000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090068#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090069#endif /* __SH7753EVB_H */