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Mike Frysingercb4b5e82008-10-12 23:08:03 -04001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF537 PNAV board
Mike Frysingercb4b5e82008-10-12 23:08:03 -04003 */
4
5#ifndef __CONFIG_BF537_PNAV_H__
6#define __CONFIG_BF537_PNAV_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingercb4b5e82008-10-12 23:08:03 -04009
Mike Frysingercb4b5e82008-10-12 23:08:03 -040010/*
11 * Processor Settings
12 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050013#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingercb4b5e82008-10-12 23:08:03 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
15
Mike Frysingercb4b5e82008-10-12 23:08:03 -040016/*
17 * Clock Settings
18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
20 */
21/* CONFIG_CLKIN_HZ is any value in Hz */
22#define CONFIG_CLKIN_HZ 24576000
23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
24/* 1 = CLKIN / 2 */
25#define CONFIG_CLKIN_HALF 0
26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
27/* 1 = bypass PLL */
28#define CONFIG_PLL_BYPASS 0
29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
30/* Values can range from 0-63 (where 0 means 64) */
31#define CONFIG_VCO_MULT 20
32/* CCLK_DIV controls the core clock divider */
33/* Values can be 1, 2, 4, or 8 ONLY */
34#define CONFIG_CCLK_DIV 1
35/* SCLK_DIV controls the system clock divider */
36/* Values can range from 1-15 */
37#define CONFIG_SCLK_DIV 4
38
Mike Frysingercb4b5e82008-10-12 23:08:03 -040039/*
40 * Memory Settings
41 */
42#define CONFIG_MEM_ADD_WDTH 10
43#define CONFIG_MEM_SIZE 64
44
45#define CONFIG_EBIU_SDRRC_VAL 0x3b7
46#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
47
48#define CONFIG_EBIU_AMGCTL_VAL 0xFF
49#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
50#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
51
Mike Frysinger4c95ff62010-10-01 19:42:08 -040052#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercb4b5e82008-10-12 23:08:03 -040053#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
54
Mike Frysingercb4b5e82008-10-12 23:08:03 -040055/*
56 * Network Settings
57 */
58#ifndef __ADSPBF534__
59#define ADI_CMDS_NETWORK 1
60#define CONFIG_BFIN_MAC
61#define CONFIG_RMII
Mike Frysingercb4b5e82008-10-12 23:08:03 -040062#endif
63#define CONFIG_HOSTNAME bf537-pnav
Mike Frysingercb4b5e82008-10-12 23:08:03 -040064
65/*
66 * Flash Settings
67 */
68#define CONFIG_FLASH_CFI_DRIVER
69#define CONFIG_SYS_FLASH_BASE 0x20000000
70#define CONFIG_SYS_FLASH_CFI
71#define CONFIG_SYS_MAX_FLASH_BANKS 1
72#define CONFIG_SYS_MAX_FLASH_SECT 71
73
Mike Frysingercb4b5e82008-10-12 23:08:03 -040074/*
75 * SPI Settings
76 */
77#define CONFIG_BFIN_SPI
78#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040079#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercb4b5e82008-10-12 23:08:03 -040080
Mike Frysingercb4b5e82008-10-12 23:08:03 -040081/*
82 * Env Storage Settings
83 */
84#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysinger76d82182009-07-21 22:17:36 -040085#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercb4b5e82008-10-12 23:08:03 -040086#define CONFIG_ENV_IS_IN_SPI_FLASH
87#define CONFIG_ENV_OFFSET 0x4000
88#else
89#define ENV_IS_EMBEDDED
90#define CONFIG_ENV_IS_IN_FLASH 1
91#define CONFIG_ENV_ADDR 0x20004000
92#define CONFIG_ENV_OFFSET 0x4000
93#endif
94#define CONFIG_ENV_SIZE 0x1000
95#define CONFIG_ENV_SECT_SIZE 0x2000
Mike Frysinger9ff67e52009-06-14 06:29:07 -040096#ifdef ENV_IS_EMBEDDED
97/* WARNING - the following is hand-optimized to fit within
98 * the sector before the environment sector. If it throws
99 * an error during compilation remove an object here to get
100 * it linked after the configuration sector.
101 */
102# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900103 arch/blackfin/lib/built-in.o (.text*); \
104 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400105 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500106 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400107#endif
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400108
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400109/*
110 * NAND Settings
111 */
112#define CONFIG_NAND_PLAT
113
114#define CONFIG_SYS_NAND_BASE 0x20100000
115#define CONFIG_SYS_MAX_NAND_DEVICE 1
116
117#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
118#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400119#define BFIN_NAND_WRITE(addr, cmd) \
120 do { \
121 bfin_write8(addr, cmd); \
122 SSYNC(); \
123 } while (0)
124
125#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
126#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400127#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400128
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400129/*
130 * I2C settings
131 */
Scott Jiangc4697032014-11-13 15:30:55 +0800132#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800133#define CONFIG_SYS_I2C_ADI
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400134
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400135/*
136 * Misc Settings
137 */
138#define CONFIG_BAUDRATE 115200
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400139#define CONFIG_RTC_BFIN
140#define CONFIG_UART_CONSOLE 0
141
142/* JFFS Partition offset set */
143#define CONFIG_SYS_JFFS2_FIRST_BANK 0
144#define CONFIG_SYS_JFFS2_NUM_BANKS 1
145/* 512k reserved for u-boot */
146#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
147
148#define CONFIG_BOOTCOMMAND "run nandboot"
149#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
150
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400151/*
152 * Pull in common ADI header for remaining command/environment setup
153 */
154#include <configs/bfin_adi_common.h>
155
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400156#endif