blob: 4963b5109b22fe977891c0b68e176b7fb0e336c2 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Rick Chenf94c44e2017-12-26 13:55:52 +08002#
3# Copyright (C) 2017 Andes Technology Corporation.
4# Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chenf94c44e2017-12-26 13:55:52 +08005
Lukas Auer0c074842018-11-22 11:26:15 +01006ifeq ($(CONFIG_ARCH_RV64I),y)
7 ARCH_BASE = rv64im
Heinrich Schuchardte67f34f2022-10-12 14:59:51 +02008 ABI_BASE = lp64
Lukas Auer0c074842018-11-22 11:26:15 +01009endif
10ifeq ($(CONFIG_ARCH_RV32I),y)
11 ARCH_BASE = rv32im
Heinrich Schuchardte67f34f2022-10-12 14:59:51 +020012 ABI_BASE = ilp32
Lukas Auer0c074842018-11-22 11:26:15 +010013endif
14ifeq ($(CONFIG_RISCV_ISA_A),y)
15 ARCH_A = a
16endif
Heinrich Schuchardte67f34f2022-10-12 14:59:51 +020017ifeq ($(CONFIG_RISCV_ISA_F),y)
18 ARCH_F = f
19endif
20ifeq ($(CONFIG_RISCV_ISA_D),y)
21 ARCH_D = d
22 ABI_D = d
23endif
Lukas Auer0c074842018-11-22 11:26:15 +010024ifeq ($(CONFIG_RISCV_ISA_C),y)
25 ARCH_C = c
26endif
Lukas Auer8176ea42018-12-12 06:12:23 -080027ifeq ($(CONFIG_CMODEL_MEDLOW),y)
28 CMODEL = medlow
29endif
30ifeq ($(CONFIG_CMODEL_MEDANY),y)
31 CMODEL = medany
32endif
Lukas Auer0c074842018-11-22 11:26:15 +010033
Heinrich Schuchardte67f34f2022-10-12 14:59:51 +020034
35RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
36ABI = $(ABI_BASE)$(ABI_D)
Alexandre Ghiti1dde9772022-10-03 18:07:54 +020037
38# Newer binutils versions default to ISA spec version 20191213 which moves some
39# instructions from the I extension to the Zicsr and Zifencei extensions.
40toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
41ifeq ($(toolchain-need-zicsr-zifencei),y)
42 RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
43endif
44
45ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
Lukas Auer8176ea42018-12-12 06:12:23 -080046 -mcmodel=$(CMODEL)
Lukas Auer0c074842018-11-22 11:26:15 +010047
48PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
49CFLAGS_EFI += $(ARCH_FLAGS)
50
Bin Mengb5369c52018-09-26 06:55:17 -070051head-y := arch/riscv/cpu/start.o
Rick Chenf94c44e2017-12-26 13:55:52 +080052
Bin Meng2fab2e92018-09-26 06:55:14 -070053libs-y += arch/riscv/cpu/
Rick Chenf94c44e2017-12-26 13:55:52 +080054libs-y += arch/riscv/cpu/$(CPU)/
55libs-y += arch/riscv/lib/