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Mike Frysinger84a9dda2008-10-12 21:32:52 -04001/*
2 * U-boot - u-boot.lds.S
3 *
Mike Frysingera3c08362010-03-23 16:23:39 -04004 * Copyright (c) 2005-2010 Analog Device Inc.
Mike Frysinger84a9dda2008-10-12 21:32:52 -04005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <asm/blackfin.h>
30#undef ALIGN
31#undef ENTRY
Mike Frysinger84a9dda2008-10-12 21:32:52 -040032
Mike Frysinger9ff67e52009-06-14 06:29:07 -040033#ifndef LDS_BOARD_TEXT
34# define LDS_BOARD_TEXT
35#endif
36
Mike Frysinger84a9dda2008-10-12 21:32:52 -040037/* If we don't actually load anything into L1 data, this will avoid
38 * a syntax error. If we do actually load something into L1 data,
39 * we'll get a linker memory load error (which is what we'd want).
40 * This is here in the first place so we can quickly test building
41 * for different CPU's which may lack non-cache L1 data.
42 */
Mike Frysinger105be902010-12-24 19:31:55 -050043#ifndef L1_DATA_A_SRAM
44# define L1_DATA_A_SRAM 0
45# define L1_DATA_A_SRAM_SIZE 0
46#endif
Mike Frysinger84a9dda2008-10-12 21:32:52 -040047#ifndef L1_DATA_B_SRAM
Mike Frysinger105be902010-12-24 19:31:55 -050048# define L1_DATA_B_SRAM L1_DATA_A_SRAM
49# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
Mike Frysinger84a9dda2008-10-12 21:32:52 -040050#endif
51
Mike Frysingerf51e0012009-07-23 16:26:58 -040052/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
53#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
54# define L1_CODE_ORIGIN L1_INST_SRAM
55#else
56# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
57#endif
58
Mike Frysinger84a9dda2008-10-12 21:32:52 -040059OUTPUT_ARCH(bfin)
60
61MEMORY
62{
Mike Frysinger7527fee2009-11-09 19:38:23 -050063#if CONFIG_MEM_SIZE
Mike Frysinger84a9dda2008-10-12 21:32:52 -040064 ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
Mike Frysinger7527fee2009-11-09 19:38:23 -050065# define ram_code ram
66# define ram_data ram
67#else
68# define ram_code l1_code
69# define ram_data l1_data
70#endif
Mike Frysingerf51e0012009-07-23 16:26:58 -040071 l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
Mike Frysinger84a9dda2008-10-12 21:32:52 -040072 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
73}
74
75ENTRY(_start)
76SECTIONS
77{
Mike Frysingerb1e2c552009-11-03 06:11:31 -050078 .text.pre :
Mike Frysinger84a9dda2008-10-12 21:32:52 -040079 {
Peter Tyserc6fb83d2010-04-12 22:28:13 -050080 arch/blackfin/cpu/start.o (.text .text.*)
Mike Frysinger9ff67e52009-06-14 06:29:07 -040081
82 LDS_BOARD_TEXT
Mike Frysingerb1e2c552009-11-03 06:11:31 -050083 } >ram_code
Mike Frysinger9ff67e52009-06-14 06:29:07 -040084
Mike Frysingerb1e2c552009-11-03 06:11:31 -050085 .text.init :
86 {
Peter Tyserc6fb83d2010-04-12 22:28:13 -050087 arch/blackfin/cpu/initcode.o (.text .text.*)
Mike Frysingerb1e2c552009-11-03 06:11:31 -050088 } >ram_code
89 __initcode_lma = LOADADDR(.text.init);
90 __initcode_len = SIZEOF(.text.init);
Mike Frysinger9ff67e52009-06-14 06:29:07 -040091
Mike Frysingerb1e2c552009-11-03 06:11:31 -050092 .text :
93 {
Mike Frysinger84a9dda2008-10-12 21:32:52 -040094 *(.text .text.*)
Mike Frysinger7527fee2009-11-09 19:38:23 -050095 } >ram_code
Mike Frysinger84a9dda2008-10-12 21:32:52 -040096
97 .rodata :
98 {
99 . = ALIGN(4);
Mike Frysingered912d42010-01-15 04:47:06 -0500100 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400101 . = ALIGN(4);
Mike Frysinger7527fee2009-11-09 19:38:23 -0500102 } >ram_data
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400103
104 .data :
105 {
Mike Frysinger38b9b742010-01-19 21:02:00 -0500106 . = ALIGN(4);
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400107 *(.data .data.*)
108 *(.data1)
109 *(.sdata)
110 *(.sdata2)
111 *(.dynamic)
112 CONSTRUCTORS
Mike Frysinger7527fee2009-11-09 19:38:23 -0500113 } >ram_data
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400114
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400115
Marek Vasut55675142012-10-12 10:27:03 +0000116 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +0000117 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +0000118 } >ram_data
119
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400120 .text_l1 :
121 {
122 . = ALIGN(4);
123 __stext_l1 = .;
124 *(.l1.text)
125 . = ALIGN(4);
126 __etext_l1 = .;
Mike Frysinger7527fee2009-11-09 19:38:23 -0500127 } >l1_code AT>ram_code
Mike Frysingerb1e2c552009-11-03 06:11:31 -0500128 __text_l1_lma = LOADADDR(.text_l1);
129 __text_l1_len = SIZEOF(.text_l1);
130 ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400131
132 .data_l1 :
133 {
134 . = ALIGN(4);
135 __sdata_l1 = .;
136 *(.l1.data)
137 *(.l1.bss)
138 . = ALIGN(4);
139 __edata_l1 = .;
Mike Frysinger7527fee2009-11-09 19:38:23 -0500140 } >l1_data AT>ram_data
Mike Frysingerb1e2c552009-11-03 06:11:31 -0500141 __data_l1_lma = LOADADDR(.data_l1);
142 __data_l1_len = SIZEOF(.data_l1);
Mike Frysinger105be902010-12-24 19:31:55 -0500143 ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400144
145 .bss :
146 {
147 . = ALIGN(4);
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400148 *(.sbss) *(.scommon)
149 *(.dynbss)
150 *(.bss .bss.*)
151 *(COMMON)
Mike Frysinger49508d42010-11-15 08:16:19 -0500152 . = ALIGN(4);
Mike Frysinger7527fee2009-11-09 19:38:23 -0500153 } >ram_data
Mike Frysingerb1e2c552009-11-03 06:11:31 -0500154 __bss_vma = ADDR(.bss);
155 __bss_len = SIZEOF(.bss);
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400156}