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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass6ec1b752014-12-10 08:55:51 -07002/*
3 * Test-related constants for sandbox
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass6ec1b752014-12-10 08:55:51 -07006 */
7
8#ifndef __ASM_TEST_H
9#define __ASM_TEST_H
10
11/* The sandbox driver always permits an I2C device with this address */
Simon Glass9569c402015-03-05 12:25:26 -070012#define SANDBOX_I2C_TEST_ADDR 0x59
13
14#define SANDBOX_PCI_VENDOR_ID 0x1234
Simon Glass34145812019-09-25 08:56:01 -060015#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
Simon Glass3b65ee32019-12-06 21:41:54 -070016#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
Simon Glass3e17ffb2019-12-06 21:41:57 -070017#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
Simon Glass9569c402015-03-05 12:25:26 -070018#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
19#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
Simon Glass6ec1b752014-12-10 08:55:51 -070020
Bin Meng95e11062018-08-03 01:14:53 -070021#define PCI_CAP_ID_PM_OFFSET 0x50
22#define PCI_CAP_ID_EXP_OFFSET 0x60
23#define PCI_CAP_ID_MSIX_OFFSET 0x70
Alex Marginean21ebbaf2019-06-07 11:24:24 +030024#define PCI_CAP_ID_EA_OFFSET 0x80
Bin Meng95e11062018-08-03 01:14:53 -070025
26#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
27#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
28#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
29
Bin Meng59a160e2018-08-03 01:14:46 -070030/* Useful for PCI_VDEVICE() macro */
31#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
32#define SWAP_CASE_DRV_DATA 0x55aa
33
Simon Glass6a1c7ce2015-07-06 12:54:24 -060034#define SANDBOX_CLK_RATE 32768
35
Alex Marginean21ebbaf2019-06-07 11:24:24 +030036/* Macros used to test PCI EA capability structure */
37#define PCI_CAP_EA_BASE_LO0 0x00100000
38#define PCI_CAP_EA_BASE_LO1 0x00110000
39#define PCI_CAP_EA_BASE_LO2 0x00120000
40#define PCI_CAP_EA_BASE_LO4 0x00140000
41#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
42#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
43#define PCI_CAP_EA_SIZE_LO 0x0000ffff
44#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
45#define PCI_EA_BAR2_MAGIC 0x72727272
46#define PCI_EA_BAR4_MAGIC 0x74747474
47
Simon Glassba876072020-02-06 09:54:57 -070048enum {
49 SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
50};
51
Simon Glass04035fd2015-07-06 12:54:35 -060052/* System controller driver data */
53enum {
54 SYSCON0 = 32,
55 SYSCON1,
56
57 SYSCON_COUNT
58};
59
Simon Glass182bf922015-04-20 12:37:15 -060060/**
Simon Glassd8e9a932021-01-16 14:52:22 -070061 */
62enum cros_ec_test_t {
63 CROSECT_BREAK_HELLO = BIT(1),
Simon Glass3a6c9942021-01-16 14:52:28 -070064 CROSECT_LID_OPEN = BIT(2),
Simon Glassd8e9a932021-01-16 14:52:22 -070065};
66
67/**
Simon Glass182bf922015-04-20 12:37:15 -060068 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
69 *
70 * See sandbox_i2c_xfer() for the behaviour changes.
71 *
72 * @bus: sandbox I2C bus to adjust
73 * @test_mode: true to select test mode, false to run normally
74 */
75void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
76
Simon Glass6ec1b752014-12-10 08:55:51 -070077enum sandbox_i2c_eeprom_test_mode {
78 SIE_TEST_MODE_NONE,
79 /* Permits read/write of only one byte per I2C transaction */
80 SIE_TEST_MODE_SINGLE_BYTE,
81};
82
83void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
84 enum sandbox_i2c_eeprom_test_mode mode);
85
86void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
87
Robert Beckett951674a2019-10-28 17:44:59 +000088void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
89 uint mask);
90
Robert Beckett22e93512019-10-28 17:44:58 +000091uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev);
92
93uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev);
94
Simon Glassdd18e5d2015-04-20 12:37:24 -060095/**
96 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
97 *
98 * @dev: RTC device to adjust
99 * @use_system_time: true to use system time, false to use @base_time
100 * @offset: RTC offset from current system/base time (-1 for no
101 * change)
102 * @return old value of RTC offset
103 */
104long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
105 int offset);
106
107/**
108 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
109 *
110 * @dev: RTC device to adjust
111 * @base_time: New base system time (set to -1 for no change)
112 * @return old base time
113 */
114long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
115
Simon Glassd8a26f02015-11-08 23:48:06 -0700116int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
117
Mario Six4eea5312018-09-27 09:19:31 +0200118/**
119 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
120 *
121 * @dev: OSD device for which to access the internal memory for
122 * @buf: pointer to buffer to receive the OSD memory data
123 * @buflen: length of buffer in bytes
124 */
125int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
Simon Glass5d9a88f2018-10-01 12:22:40 -0600126
127/**
128 * sandbox_pwm_get_config() - get the PWM config for a channel
129 *
130 * @dev: Device to check
131 * @channel: Channel number to check
132 * @period_ns: Period of the PWM in nanoseconds
133 * @duty_ns: Current duty cycle of the PWM in nanoseconds
134 * @enable: true if the PWM is enabled
135 * @polarity: true if the PWM polarity is active high
136 * @return 0 if OK, -ENOSPC if the PWM number is invalid
137 */
138int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
139 uint *duty_nsp, bool *enablep, bool *polarityp);
140
Simon Glassa58986c2018-11-06 15:21:41 -0700141/**
142 * sandbox_sf_set_block_protect() - Set the BP bits of the status register
143 *
144 * @dev: Device to update
145 * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
146 */
147void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
148
Simon Glassce6d99a2018-12-10 10:37:33 -0700149/**
150 * sandbox_get_codec_params() - Read back codec parameters
151 *
152 * This reads back the parameters set by audio_codec_set_params() for the
153 * sandbox audio driver. Arguments are as for that function.
154 */
155void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
156 int *mclk_freqp, int *bits_per_samplep,
157 uint *channelsp);
158
Simon Glasse96fa6c2018-12-10 10:37:34 -0700159/**
160 * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
161 *
162 * This data is provided to the sandbox driver by the I2S tx_data() method.
163 *
164 * @dev: Device to check
165 * @return sum of audio data
166 */
167int sandbox_get_i2s_sum(struct udevice *dev);
168
Simon Glassd4901892018-12-10 10:37:36 -0700169/**
170 * sandbox_get_setup_called() - Returns the number of times setup(*) was called
171 *
172 * This is used in the sound test
173 *
174 * @dev: Device to check
175 * @return call count for the setup() method
176 */
177int sandbox_get_setup_called(struct udevice *dev);
178
179/**
Simon Glass3062cd12020-02-03 07:36:06 -0700180 * sandbox_get_sound_active() - Returns whether sound play is in progress
181 *
182 * @return true if active, false if not
183 */
184int sandbox_get_sound_active(struct udevice *dev);
185
186/**
Simon Glassd4901892018-12-10 10:37:36 -0700187 * sandbox_get_sound_sum() - Read back the sum of the sound data so far
188 *
189 * This data is provided to the sandbox driver by the sound play() method.
190 *
191 * @dev: Device to check
192 * @return sum of audio data
193 */
194int sandbox_get_sound_sum(struct udevice *dev);
195
Simon Glassb45c8332019-02-16 20:24:50 -0700196/**
Simon Glass28502662019-02-16 20:24:54 -0700197 * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
198 *
199 * @dev: Device to update
200 * @allow: true to allow the start_beep() method, false to disallow it
201 */
202void sandbox_set_allow_beep(struct udevice *dev, bool allow);
203
204/**
205 * sandbox_get_beep_frequency() - Get the frequency of the current beep
206 *
207 * @dev: Device to check
208 * @return frequency of beep, if there is an active beep, else 0
209 */
210int sandbox_get_beep_frequency(struct udevice *dev);
211
212/**
Ovidiu Panaitadd685f2020-12-14 19:06:49 +0200213 * sandbox_spi_get_speed() - Get current speed setting of a sandbox spi bus
214 *
215 * @dev: Device to check
216 * @return current bus speed
217 */
218uint sandbox_spi_get_speed(struct udevice *dev);
219
220/**
221 * sandbox_spi_get_mode() - Get current mode setting of a sandbox spi bus
222 *
223 * @dev: Device to check
224 * @return current mode
225 */
226uint sandbox_spi_get_mode(struct udevice *dev);
227
228/**
Simon Glassb45c8332019-02-16 20:24:50 -0700229 * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
230 *
231 * @dev: Device to check
232 * @return 0 if not protected, 1 if protected
233 */
234int sandbox_get_pch_spi_protect(struct udevice *dev);
235
Ramon Friedf2a55ac2019-04-27 11:15:24 +0300236/**
237 * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
238 *
239 * @dev: Device to check
240 * @return irq count
241 */
242int sandbox_get_pci_ep_irq_count(struct udevice *dev);
243
Simon Glass75d8f492019-09-25 08:56:42 -0600244/**
245 * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
246 *
247 * This is used in PCI emulators to read a base address reset. This has special
248 * rules because when the register is set to 0xffffffff it can be used to
249 * discover the type and size of the BAR.
250 *
251 * @barval: Current value of the BAR
252 * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
253 * PCI_BASE_ADDRESS_MEM_TYPE_32)
254 * @size: Size of BAR in bytes
255 * @return BAR value to return from emulator
256 */
257uint sandbox_pci_read_bar(u32 barval, int type, uint size);
258
Simon Glass619025b2019-10-11 16:16:48 -0600259/**
260 * sandbox_set_enable_memio() - Enable readl/writel() for sandbox
261 *
262 * Normally these I/O functions do nothing with sandbox. Certain tests need them
263 * to work as for other architectures, so this function can be used to enable
264 * them.
265 *
266 * @enable: true to enable, false to disable
267 */
268void sandbox_set_enable_memio(bool enable);
269
Simon Glassd8e9a932021-01-16 14:52:22 -0700270/**
271 * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes
272 *
273 * @dev: Device to check
274 * @flags: Flags to control behaviour (CROSECT_...)
275 */
276void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags);
277
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300278/**
279 * sandbox_cros_ec_get_pwm_duty() - Get EC PWM config for testing purposes
280 *
281 * @dev: Device to check
282 * @index: PWM channel index
283 * @duty: Current duty cycle in 0..EC_PWM_MAX_DUTY range.
284 * @return 0 if OK, -ENOSPC if the PWM number is invalid
285 */
286int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
287
Simon Glass6ec1b752014-12-10 08:55:51 -0700288#endif