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Markus Klotzbuecher7c93b242006-04-25 16:48:48 +02001/*
2 * (C) Copyright 2006 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
Marek Vasut3ba8bf72010-09-09 09:50:39 +020024#include <asm/io.h>
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020025
Jon Loeligerab3abcb2007-07-09 18:45:16 -050026#if defined(CONFIG_CMD_NAND)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020027
28#include <nand.h>
29#include <asm/arch/pxa-regs.h>
30
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#ifdef CONFIG_SYS_DFC_DEBUG1
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020032# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
33#else
34# define DFC_DEBUG1(fmt, args...)
35#endif
36
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#ifdef CONFIG_SYS_DFC_DEBUG2
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020038# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
39#else
40# define DFC_DEBUG2(fmt, args...)
41#endif
42
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#ifdef CONFIG_SYS_DFC_DEBUG3
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020044# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
45#else
46# define DFC_DEBUG3(fmt, args...)
47#endif
48
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020049/* These really don't belong here, as they are specific to the NAND Model */
50static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
51
52static struct nand_bbt_descr delta_bbt_descr = {
53 .options = 0,
54 .offs = 0,
55 .len = 2,
56 .pattern = scan_ff_pattern
57};
58
Scott Wood66446412008-09-10 11:48:49 -050059static struct nand_ecclayout delta_oob = {
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020060 .eccbytes = 6,
61 .eccpos = {2, 3, 4, 5, 6, 7},
62 .oobfree = { {8, 2}, {12, 4} }
63};
64
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020065/*
66 * not required for Monahans DFC
67 */
William Juulcfa460a2007-10-31 13:53:06 +010068static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020069{
70 return;
71}
72
73#if 0
74/* read device ready pin */
75static int dfc_device_ready(struct mtd_info *mtdinfo)
76{
77 if(NDSR & NDSR_RDY)
78 return 1;
79 else
80 return 0;
81 return 0;
82}
83#endif
84
85/*
86 * Write buf to the DFC Controller Data Buffer
87 */
88static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
89{
90 unsigned long bytes_multi = len & 0xfffffffc;
91 unsigned long rest = len & 0x3;
92 unsigned long *long_buf;
93 int i;
94
95 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
96 if(bytes_multi) {
97 for(i=0; i<bytes_multi; i+=4) {
98 long_buf = (unsigned long*) &buf[i];
Marek Vasut3ba8bf72010-09-09 09:50:39 +020099 writel(*long_buf, NDDB);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200100 }
101 }
102 if(rest) {
103 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
104 }
105 return;
106}
107
108
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200109/* The original:
110 * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
111 *
112 * Shouldn't this be "u_char * const buf" ?
113 */
114static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
115{
116 int i=0, j;
117
118 /* we have to be carefull not to overflow the buffer if len is
119 * not a multiple of 4 */
120 unsigned long bytes_multi = len & 0xfffffffc;
121 unsigned long rest = len & 0x3;
122 unsigned long *long_buf;
123
124 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
125 /* if there are any, first copy multiple of 4 bytes */
126 if(bytes_multi) {
127 for(i=0; i<bytes_multi; i+=4) {
128 long_buf = (unsigned long*) &buf[i];
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200129 *long_buf = readl(NDDB);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200130 }
131 }
132
133 /* ...then the rest */
134 if(rest) {
135 unsigned long rest_data = NDDB;
136 for(j=0;j<rest; j++)
137 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
138 }
139
140 return;
141}
142
143/*
144 * read a word. Not implemented as not used in NAND code.
145 */
146static u16 dfc_read_word(struct mtd_info *mtd)
147{
William Juulcfa460a2007-10-31 13:53:06 +0100148 printf("dfc_read_word: UNIMPLEMENTED.\n");
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200149 return 0;
150}
151
152/* global var, too bad: mk@tbd: move to ->priv pointer */
153static unsigned long read_buf = 0;
154static int bytes_read = -1;
155
156/*
157 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
158 * a time, we buffer the remaining bytes. The buffer is reset when a
159 * new command is sent to the chip.
160 *
161 * WARNING:
162 * This function is currently only used to read status and id
163 * bytes. For these commands always 8 bytes need to be read from
164 * NDDB. So we read and discard these bytes right now. In case this
165 * function is used for anything else in the future, we must check
166 * what was the last command issued and read the appropriate amount of
167 * bytes respectively.
168 */
169static u_char dfc_read_byte(struct mtd_info *mtd)
170{
171 unsigned char byte;
172 unsigned long dummy;
173
174 if(bytes_read < 0) {
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200175 read_buf = readl(NDDB);
176 dummy = readl(NDDB);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200177 bytes_read = 0;
178 }
179 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
180 if(bytes_read >= 4)
181 bytes_read = -1;
182
183 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
184 return byte;
185}
186
187/* calculate delta between OSCR values start and now */
188static unsigned long get_delta(unsigned long start)
189{
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200190 unsigned long cur = readl(OSCR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200191
192 if(cur < start) /* OSCR overflowed */
193 return (cur + (start^0xffffffff));
194 else
195 return (cur - start);
196}
197
198/* delay function, this doesn't belong here */
199static void wait_us(unsigned long us)
200{
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200201 unsigned long start = readl(OSCR);
Wolfgang Denk4af34172009-08-16 23:40:13 +0200202 us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200203
204 while (get_delta(start) < us) {
205 /* do nothing */
206 }
207}
208
209static void dfc_clear_nddb(void)
210{
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200211 writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 wait_us(CONFIG_SYS_NAND_OTHER_TO);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200213}
214
215/* wait_event with timeout */
216static unsigned long dfc_wait_event(unsigned long event)
217{
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200218 unsigned long ndsr, timeout, start = readl(OSCR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200219
220 if(!event)
221 return 0xff000000;
222 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
Wolfgang Denk4af34172009-08-16 23:40:13 +0200223 timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
224 * OSCR_CLK_FREQ, 1000);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200225 else
Wolfgang Denk4af34172009-08-16 23:40:13 +0200226 timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
227 * OSCR_CLK_FREQ, 1000);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200228
229 while(1) {
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200230 ndsr = readl(NDSR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200231 if(ndsr & event) {
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200232 writel(readl(NDSR) | event, NDSR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200233 break;
234 }
235 if(get_delta(start) > timeout) {
Jean-Christophe PLAGNIOL-VILLARD0a5676b2008-07-12 14:36:34 +0200236 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200237 return 0xff000000;
238 }
239
240 }
241 return ndsr;
242}
243
244/* we don't always wan't to do this */
245static void dfc_new_cmd(void)
246{
247 int retry = 0;
248 unsigned long status;
249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200251 /* Clear NDSR */
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200252 writel(0xFFF, NDSR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200253
254 /* set NDCR[NDRUN] */
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200255 if (!(readl(NDCR) & NDCR_ND_RUN))
256 writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200257
258 status = dfc_wait_event(NDSR_WRCMDREQ);
259
260 if(status & NDSR_WRCMDREQ)
261 return;
262
263 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
264 dfc_clear_nddb();
265 }
266 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
267}
268
269/* this function is called after Programm and Erase Operations to
270 * check for success or failure */
William Juulcfa460a2007-10-31 13:53:06 +0100271static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200272{
273 unsigned long ndsr=0, event=0;
William Juulcfa460a2007-10-31 13:53:06 +0100274 int state = this->state;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200275
276 if(state == FL_WRITING) {
277 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
278 } else if(state == FL_ERASING) {
279 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
280 }
281
282 ndsr = dfc_wait_event(event);
283
284 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
285 return(0x1); /* Status Read error */
286 return 0;
287}
288
289/* cmdfunc send commands to the DFC */
290static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
291 int column, int page_addr)
292{
293 /* register struct nand_chip *this = mtd->priv; */
294 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
295
296 /* clear the ugly byte read buffer */
297 bytes_read = -1;
298 read_buf = 0;
299
300 switch (command) {
301 case NAND_CMD_READ0:
302 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
303 dfc_new_cmd();
304 ndcb0 = (NAND_CMD_READ0 | (4<<16));
305 column >>= 1; /* adjust for 16 bit bus */
306 ndcb1 = (((column>>1) & 0xff) |
307 ((page_addr<<8) & 0xff00) |
308 ((page_addr<<8) & 0xff0000) |
309 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
310 event = NDSR_RDDREQ;
311 goto write_cmd;
312 case NAND_CMD_READ1:
313 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
314 goto end;
315 case NAND_CMD_READOOB:
316 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
317 goto end;
318 case NAND_CMD_READID:
319 dfc_new_cmd();
320 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
321 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
322 event = NDSR_RDDREQ;
323 goto write_cmd;
324 case NAND_CMD_PAGEPROG:
325 /* sent as a multicommand in NAND_CMD_SEQIN */
326 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
327 goto end;
328 case NAND_CMD_ERASE1:
329 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
330 dfc_new_cmd();
331 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
332 ndcb1 = (page_addr & 0x00ffffff);
333 goto write_cmd;
334 case NAND_CMD_ERASE2:
335 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
336 goto end;
337 case NAND_CMD_SEQIN:
338 /* send PAGE_PROG command(0x1080) */
339 dfc_new_cmd();
340 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
341 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
342 column >>= 1; /* adjust for 16 bit bus */
343 ndcb1 = (((column>>1) & 0xff) |
344 ((page_addr<<8) & 0xff00) |
345 ((page_addr<<8) & 0xff0000) |
346 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
347 event = NDSR_WRDREQ;
348 goto write_cmd;
349 case NAND_CMD_STATUS:
350 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
351 dfc_new_cmd();
352 ndcb0 = NAND_CMD_STATUS | (4<<21);
353 event = NDSR_RDDREQ;
354 goto write_cmd;
355 case NAND_CMD_RESET:
356 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
357 ndcb0 = NAND_CMD_RESET | (5<<21);
358 event = NDSR_CS0_CMDD;
359 goto write_cmd;
360 default:
361 printk("dfc_cmdfunc: error, unsupported command.\n");
362 goto end;
363 }
364
365 write_cmd:
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200366 writel(ndcb0, NDCB0);
367 writel(ndcb1, NDCB0);
368 writel(ndcb2, NDCB0);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200369
370 /* wait_event: */
371 dfc_wait_event(event);
372 end:
373 return;
374}
375
376static void dfc_gpio_init(void)
377{
378 DFC_DEBUG2("Setting up DFC GPIO's.\n");
379
380 /* no idea what is done here, see zylonite.c */
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200381 writel(0x1, GPIO4);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200382
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200383 writel(0x00000001, DF_ALE_nWE1);
384 writel(0x00000001, DF_ALE_nWE2);
385 writel(0x00000001, DF_nCS0);
386 writel(0x00000001, DF_nCS1);
387 writel(0x00000001, DF_nWE);
388 writel(0x00000001, DF_nRE);
389 writel(0x00000001, DF_IO0);
390 writel(0x00000001, DF_IO8);
391 writel(0x00000001, DF_IO1);
392 writel(0x00000001, DF_IO9);
393 writel(0x00000001, DF_IO2);
394 writel(0x00000001, DF_IO10);
395 writel(0x00000001, DF_IO3);
396 writel(0x00000001, DF_IO11);
397 writel(0x00000001, DF_IO4);
398 writel(0x00000001, DF_IO12);
399 writel(0x00000001, DF_IO5);
400 writel(0x00000001, DF_IO13);
401 writel(0x00000001, DF_IO6);
402 writel(0x00000001, DF_IO14);
403 writel(0x00000001, DF_IO7);
404 writel(0x00000001, DF_IO15);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200405
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200406 writel(0x1901, DF_nWE);
407 writel(0x1901, DF_nRE);
408 writel(0x1900, DF_CLE_nOE);
409 writel(0x1901, DF_ALE_nWE1);
410 writel(0x1900, DF_INT_RnB);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200411}
412
413/*
414 * Board-specific NAND initialization. The following members of the
415 * argument are board-specific (per include/linux/mtd/nand_new.h):
416 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
417 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
William Juulcfa460a2007-10-31 13:53:06 +0100418 * - cmd_ctrl: hardwarespecific function for accesing control-lines
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200419 * - dev_ready: hardwarespecific function for accesing device ready/busy line
420 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
421 * only be provided if a hardware ECC is available
William Juulcfa460a2007-10-31 13:53:06 +0100422 * - ecc.mode: mode of ecc, see defines
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200423 * - chip_delay: chip dependent delay for transfering data from array to
424 * read regs (tR)
425 * - options: various chip options. They can partly be set to inform
426 * nand_scan about special functionality. See the defines for further
427 * explanation
428 * Members with a "?" were not set in the merged testing-NAND branch,
429 * so they are not set here either.
430 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100431int board_nand_init(struct nand_chip *nand)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200432{
433 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
434
435 /* set up GPIO Control Registers */
436 dfc_gpio_init();
437
438 /* turn on the NAND Controller Clock (104 MHz @ D0) */
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200439 writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#undef CONFIG_SYS_TIMING_TIGHT
442#ifndef CONFIG_SYS_TIMING_TIGHT
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200443 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
444 DFC_MAX_tCH);
445 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
446 DFC_MAX_tCS);
447 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
448 DFC_MAX_tWH);
449 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
450 DFC_MAX_tWP);
451 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
452 DFC_MAX_tRH);
453 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
454 DFC_MAX_tRP);
455 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
456 DFC_MAX_tR);
457 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
458 DFC_MAX_tWHR);
459 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
460 DFC_MAX_tAR);
461#else /* this is the tight timing */
462
463 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
464 DFC_MAX_tCH);
465 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
466 DFC_MAX_tCS);
467 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
468 DFC_MAX_tWH);
469 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
470 DFC_MAX_tWP);
471 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
472 DFC_MAX_tRH);
473 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
474 DFC_MAX_tRP);
475 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
476 DFC_MAX_tR);
477 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
478 DFC_MAX_tWHR);
479 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
480 DFC_MAX_tAR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#endif /* CONFIG_SYS_TIMING_TIGHT */
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200482
483
484 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
485
486 /* tRP value is split in the register */
487 if(tRP & (1 << 4)) {
488 tRP_high = 1;
489 tRP &= ~(1 << 4);
490 } else {
491 tRP_high = 0;
492 }
493
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200494 writel((tCH << 19) |
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200495 (tCS << 16) |
496 (tWH << 11) |
497 (tWP << 8) |
498 (tRP_high << 6) |
499 (tRH << 3) |
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200500 (tRP << 0),
501 NDTR0CS0);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200502
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200503 writel((tR << 16) |
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200504 (tWHR << 4) |
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200505 (tAR << 0),
506 NDTR1CS0);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200507
508 /* If it doesn't work (unlikely) think about:
509 * - ecc enable
510 * - chip select don't care
511 * - read id byte count
512 *
513 * Intentionally enabled by not setting bits:
514 * - dma (DMA_EN)
515 * - page size = 512
516 * - cs don't care, see if we can enable later!
517 * - row address start position (after second cycle)
518 * - pages per block = 32
519 * - ND_RDY : clears command buffer
520 */
521 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
522
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200523 writel(NDCR_SPARE_EN | /* use the spare area */
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200524 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
525 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
526 (2 << 16) | /* read id count = 7 ???? mk@tbd */
527 NDCR_ND_ARB_EN | /* enable bus arbiter */
528 NDCR_RDYM | /* flash device ready ir masked */
529 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
530 NDCR_CS1_PAGEDM |
531 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
532 NDCR_CS1_CMDDM |
533 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
534 NDCR_CS1_BBDM |
535 NDCR_DBERRM | /* double bit error ir masked */
536 NDCR_SBERRM | /* single bit error ir masked */
537 NDCR_WRDREQM | /* write data request ir masked */
538 NDCR_RDDREQM | /* read data request ir masked */
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200539 NDCR_WRCMDREQM, /* write command request ir masked */
540 NDCR);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200541
542
543 /* wait 10 us due to cmd buffer clear reset */
544 /* wait(10); */
545
William Juulcfa460a2007-10-31 13:53:06 +0100546 nand->cmd_ctrl = dfc_hwcontrol;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200547/* nand->dev_ready = dfc_device_ready; */
William Juulcfa460a2007-10-31 13:53:06 +0100548 nand->ecc.mode = NAND_ECC_SOFT;
Scott Wood66446412008-09-10 11:48:49 -0500549 nand->ecc.layout = &delta_oob;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200550 nand->options = NAND_BUSWIDTH_16;
551 nand->waitfunc = dfc_wait;
552 nand->read_byte = dfc_read_byte;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200553 nand->read_word = dfc_read_word;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200554 nand->read_buf = dfc_read_buf;
555 nand->write_buf = dfc_write_buf;
556
557 nand->cmdfunc = dfc_cmdfunc;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200558 nand->badblock_pattern = &delta_bbt_descr;
Heiko Schocherfa230442006-12-21 17:17:02 +0100559 return 0;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200560}
561
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200562#endif