Wenyou Yang | 9e5935c | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 1 | config CLK_AT91 |
| 2 | bool "AT91 clock drivers" |
| 3 | depends on CLK |
Wenyou Yang | 6cadaa0 | 2016-09-27 11:00:29 +0800 | [diff] [blame] | 4 | select MISC |
Wenyou Yang | 9e5935c | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 5 | help |
| 6 | This option is used to enable the AT91 clock driver. |
| 7 | The driver supports the AT91 clock generator, including |
| 8 | the oscillators and PLLs, such as main clock, slow clock, |
| 9 | PLLA, UTMI PLL. Clocks can also be a source clock of other |
| 10 | clocks a tree structure, such as master clock, usb device |
| 11 | clock, matrix clock and generic clock. |
| 12 | Devices can use a common clock API to request a particular |
| 13 | clock, enable it and get its rate. |
| 14 | |
| 15 | config AT91_UTMI |
| 16 | bool "Support UTMI PLL Clock" |
Wenyou Yang | e7c8315 | 2017-09-05 18:30:07 +0800 | [diff] [blame^] | 17 | depends on CLK_AT91 && SPL_DM |
| 18 | select REGMAP |
| 19 | select SPL_REGMAP |
| 20 | select SYSCON |
| 21 | select SPL_SYSCON |
Wenyou Yang | 9e5935c | 2016-07-20 17:55:12 +0800 | [diff] [blame] | 22 | help |
| 23 | This option is used to enable the AT91 UTMI PLL clock |
| 24 | driver. It is the clock provider of USB, and UPLLCK is the |
| 25 | output of 480 MHz UTMI PLL, The souce clock of the UTMI |
| 26 | PLL is the main clock, so the main clock must select the |
| 27 | fast crystal oscillator to meet the frequency accuracy |
| 28 | required by USB. |
| 29 | |
| 30 | config AT91_H32MX |
| 31 | bool "Support H32MX 32-bit Matrix Clock" |
| 32 | depends on CLK_AT91 |
| 33 | help |
| 34 | This option is used to enable the AT91 H32MX matrixes |
| 35 | clock driver. There are H64MX and H32MX matrixes clocks, |
| 36 | H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit |
| 37 | matrix clock is to be configured as MCK if MCK does not |
| 38 | exceed 83 MHz, else it is to be configured as MCK/2. |
| 39 | |
| 40 | config AT91_GENERIC_CLK |
| 41 | bool "Support Generic Clock" |
| 42 | depends on CLK_AT91 |
| 43 | help |
| 44 | This option is used to enable the AT91 generic clock |
| 45 | driver. Some peripherals may need a second clock source |
| 46 | that may be different from the system clock. This second |
| 47 | clock is the generic clock (GCLK) and is managed by |
| 48 | the PMC via PMC_PCR register. |