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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
Jon Loeligerbaa26db2007-07-08 17:51:39 -050030#if defined(CONFIG_CMD_NET)
wdenk4a9cbbe2002-08-27 09:48:53 +000031#include <net.h>
32#endif
wdenk8bde7f72003-06-27 21:31:46 +000033#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000034#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000035
wdenk4a9cbbe2002-08-27 09:48:53 +000036/* Local functions */
wdenkd4ca31c2004-01-02 14:00:00 +000037static int fpga_get_op (char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000038
39/* Local defines */
40#define FPGA_NONE -1
41#define FPGA_INFO 0
42#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000043#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000044#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020045#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000046
wdenk30ce5ab2005-01-09 18:12:51 +000047/* Convert bitstream data and load into the fpga */
48int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
49{
Matthias Fuchs01335022007-12-27 17:12:34 +010050#if defined(CONFIG_FPGA_XILINX)
Wolfgang Denk8b019da2005-08-08 00:14:41 +020051 unsigned int length;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020052 unsigned int swapsize;
wdenk30ce5ab2005-01-09 18:12:51 +000053 char buffer[80];
Wolfgang Denk8b019da2005-08-08 00:14:41 +020054 unsigned char *dataptr;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020055 unsigned int i;
wdenk30ce5ab2005-01-09 18:12:51 +000056 int rc;
57
Wolfgang Denk77ddac92005-10-13 16:45:02 +020058 dataptr = (unsigned char *)fpgadata;
wdenk30ce5ab2005-01-09 18:12:51 +000059
Wolfgang Denk8b019da2005-08-08 00:14:41 +020060 /* skip the first bytes of the bitsteam, their meaning is unknown */
61 length = (*dataptr << 8) + *(dataptr+1);
62 dataptr+=2;
63 dataptr+=length;
wdenk30ce5ab2005-01-09 18:12:51 +000064
65 /* get design name (identifier, length, string) */
Wolfgang Denk8b019da2005-08-08 00:14:41 +020066 length = (*dataptr << 8) + *(dataptr+1);
67 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +000068 if (*dataptr++ != 0x61) {
Stefano Babic06297db2011-12-28 06:47:01 +000069 debug("%s: Design name identifier not recognized "
70 "in bitstream\n",
71 __func__);
wdenk30ce5ab2005-01-09 18:12:51 +000072 return FPGA_FAIL;
73 }
74
wdenka562e1b2005-01-09 18:21:42 +000075 length = (*dataptr << 8) + *(dataptr+1);
wdenk30ce5ab2005-01-09 18:12:51 +000076 dataptr+=2;
77 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +020078 buffer[i] = *dataptr++;
wdenka562e1b2005-01-09 18:21:42 +000079
Wolfgang Denk8b019da2005-08-08 00:14:41 +020080 printf(" design filename = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +000081
82 /* get part number (identifier, length, string) */
83 if (*dataptr++ != 0x62) {
Stefano Babic06297db2011-12-28 06:47:01 +000084 printf("%s: Part number identifier not recognized "
85 "in bitstream\n",
86 __func__);
wdenk30ce5ab2005-01-09 18:12:51 +000087 return FPGA_FAIL;
88 }
wdenka562e1b2005-01-09 18:21:42 +000089
Wolfgang Denk8b019da2005-08-08 00:14:41 +020090 length = (*dataptr << 8) + *(dataptr+1);
91 dataptr+=2;
wdenka562e1b2005-01-09 18:21:42 +000092 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +020093 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020094 printf(" part number = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +000095
wdenk30ce5ab2005-01-09 18:12:51 +000096 /* get date (identifier, length, string) */
97 if (*dataptr++ != 0x63) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020098 printf("%s: Date identifier not recognized in bitstream\n",
Stefano Babic06297db2011-12-28 06:47:01 +000099 __func__);
wdenk30ce5ab2005-01-09 18:12:51 +0000100 return FPGA_FAIL;
101 }
wdenka562e1b2005-01-09 18:21:42 +0000102
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200103 length = (*dataptr << 8) + *(dataptr+1);
104 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000105 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200106 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200107 printf(" date = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +0000108
109 /* get time (identifier, length, string) */
110 if (*dataptr++ != 0x64) {
Stefano Babic06297db2011-12-28 06:47:01 +0000111 printf("%s: Time identifier not recognized in bitstream\n",
112 __func__);
wdenk30ce5ab2005-01-09 18:12:51 +0000113 return FPGA_FAIL;
114 }
wdenka562e1b2005-01-09 18:21:42 +0000115
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200116 length = (*dataptr << 8) + *(dataptr+1);
117 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000118 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200119 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200120 printf(" time = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000121
wdenk30ce5ab2005-01-09 18:12:51 +0000122 /* get fpga data length (identifier, length) */
123 if (*dataptr++ != 0x65) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200124 printf("%s: Data length identifier not recognized in bitstream\n",
Stefano Babic06297db2011-12-28 06:47:01 +0000125 __func__);
wdenk30ce5ab2005-01-09 18:12:51 +0000126 return FPGA_FAIL;
127 }
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200128 swapsize = ((unsigned int) *dataptr <<24) +
129 ((unsigned int) *(dataptr+1) <<16) +
130 ((unsigned int) *(dataptr+2) <<8 ) +
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200131 ((unsigned int) *(dataptr+3) ) ;
wdenk30ce5ab2005-01-09 18:12:51 +0000132 dataptr+=4;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200133 printf(" bytes in bitstream = %d\n", swapsize);
wdenka562e1b2005-01-09 18:21:42 +0000134
Matthias Fuchsc26acc12007-12-27 17:13:11 +0100135 rc = fpga_load(dev, dataptr, swapsize);
wdenk30ce5ab2005-01-09 18:12:51 +0000136 return rc;
137#else
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200138 printf("Bitstream support only for Xilinx devices\n");
wdenk30ce5ab2005-01-09 18:12:51 +0000139 return FPGA_FAIL;
140#endif
141}
142
wdenk4a9cbbe2002-08-27 09:48:53 +0000143/* ------------------------------------------------------------------------- */
144/* command form:
145 * fpga <op> <device number> <data addr> <datasize>
146 * where op is 'load', 'dump', or 'info'
147 * If there is no device number field, the fpga environment variable is used.
148 * If there is no data addr field, the fpgadata environment variable is used.
149 * The info command requires no data address field.
150 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200151int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000152{
wdenkd4ca31c2004-01-02 14:00:00 +0000153 int op, dev = FPGA_INVALID_DEVICE;
154 size_t data_size = 0;
155 void *fpga_data = NULL;
156 char *devstr = getenv ("fpga");
157 char *datastr = getenv ("fpgadata");
158 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +0200159 int wrong_parms = 0;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100160#if defined (CONFIG_FIT)
161 const char *fit_uname = NULL;
162 ulong fit_addr;
163#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000164
wdenkd4ca31c2004-01-02 14:00:00 +0000165 if (devstr)
166 dev = (int) simple_strtoul (devstr, NULL, 16);
167 if (datastr)
168 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000169
wdenkd4ca31c2004-01-02 14:00:00 +0000170 switch (argc) {
171 case 5: /* fpga <op> <dev> <data> <datasize> */
172 data_size = simple_strtoul (argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100173
wdenkd4ca31c2004-01-02 14:00:00 +0000174 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100175#if defined(CONFIG_FIT)
176 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
177 &fit_addr, &fit_uname)) {
178 fpga_data = (void *)fit_addr;
Stefano Babic06297db2011-12-28 06:47:01 +0000179 debug("* fpga: subimage '%s' from FIT image "
180 "at 0x%08lx\n",
181 fit_uname, fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100182 } else
183#endif
184 {
185 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000186 debug("* fpga: cmdline image address = 0x%08lx\n",
187 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100188 }
Stefano Babic06297db2011-12-28 06:47:01 +0000189 debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100190
wdenkd4ca31c2004-01-02 14:00:00 +0000191 case 3: /* fpga <op> <dev | data addr> */
192 dev = (int) simple_strtoul (argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000193 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000194 /* FIXME - this is a really weak test */
195 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
Stefano Babic06297db2011-12-28 06:47:01 +0000196 debug("%s: Assuming buffer pointer in arg 3\n",
197 __func__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100198
199#if defined(CONFIG_FIT)
200 if (fit_parse_subimage (argv[2], (ulong)fpga_data,
201 &fit_addr, &fit_uname)) {
202 fpga_data = (void *)fit_addr;
Stefano Babic06297db2011-12-28 06:47:01 +0000203 debug("* fpga: subimage '%s' from FIT image "
204 "at 0x%08lx\n",
205 fit_uname, fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100206 } else
207#endif
208 {
209 fpga_data = (void *) dev;
Stefano Babic06297db2011-12-28 06:47:01 +0000210 debug("* fpga: cmdline image address = "
211 "0x%08lx\n", (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100212 }
213
Stefano Babic06297db2011-12-28 06:47:01 +0000214 debug("%s: fpga_data = 0x%x\n",
215 __func__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000216 dev = FPGA_INVALID_DEVICE; /* reset device num */
217 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100218
wdenkd4ca31c2004-01-02 14:00:00 +0000219 case 2: /* fpga <op> */
220 op = (int) fpga_get_op (argv[1]);
221 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100222
wdenkd4ca31c2004-01-02 14:00:00 +0000223 default:
Stefano Babic06297db2011-12-28 06:47:01 +0000224 debug("%s: Too many or too few args (%d)\n",
225 __func__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000226 op = FPGA_NONE; /* force usage display */
227 break;
228 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000229
Stefano Babica790b5b2010-10-19 09:22:52 +0200230 if (dev == FPGA_INVALID_DEVICE) {
231 puts("FPGA device not specified\n");
232 op = FPGA_NONE;
233 }
234
235 switch (op) {
236 case FPGA_NONE:
237 case FPGA_INFO:
238 break;
239 case FPGA_LOAD:
240 case FPGA_LOADB:
241 case FPGA_DUMP:
242 if (!fpga_data || !data_size)
243 wrong_parms = 1;
244 break;
245 case FPGA_LOADMK:
246 if (!fpga_data)
247 wrong_parms = 1;
248 break;
249 }
250
251 if (wrong_parms) {
252 puts("Wrong parameters for FPGA request\n");
253 op = FPGA_NONE;
254 }
255
wdenkd4ca31c2004-01-02 14:00:00 +0000256 switch (op) {
257 case FPGA_NONE:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000258 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000259
wdenkd4ca31c2004-01-02 14:00:00 +0000260 case FPGA_INFO:
261 rc = fpga_info (dev);
262 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000263
wdenkd4ca31c2004-01-02 14:00:00 +0000264 case FPGA_LOAD:
265 rc = fpga_load (dev, fpga_data, data_size);
266 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000267
wdenk30ce5ab2005-01-09 18:12:51 +0000268 case FPGA_LOADB:
269 rc = fpga_loadbitstream(dev, fpga_data, data_size);
270 break;
271
Stefan Roesef0ff4692006-08-15 14:15:51 +0200272 case FPGA_LOADMK:
Marian Balakowicz9a4daad2008-02-29 14:58:34 +0100273 switch (genimg_get_format (fpga_data)) {
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100274 case IMAGE_FORMAT_LEGACY:
275 {
276 image_header_t *hdr = (image_header_t *)fpga_data;
277 ulong data;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200278
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100279 data = (ulong)image_get_data (hdr);
280 data_size = image_get_data_size (hdr);
281 rc = fpga_load (dev, (void *)data, data_size);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200282 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100283 break;
284#if defined(CONFIG_FIT)
285 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100286 {
287 const void *fit_hdr = (const void *)fpga_data;
288 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000289 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100290
291 if (fit_uname == NULL) {
292 puts ("No FIT subimage unit name\n");
293 return 1;
294 }
295
296 if (!fit_check_format (fit_hdr)) {
297 puts ("Bad FIT image format\n");
298 return 1;
299 }
300
301 /* get fpga component image node offset */
302 noffset = fit_image_get_node (fit_hdr, fit_uname);
303 if (noffset < 0) {
304 printf ("Can't find '%s' FIT subimage\n", fit_uname);
305 return 1;
306 }
307
308 /* verify integrity */
309 if (!fit_image_check_hashes (fit_hdr, noffset)) {
310 puts ("Bad Data Hash\n");
311 return 1;
312 }
313
314 /* get fpga subimage data address and length */
315 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
316 puts ("Could not find fpga subimage data\n");
317 return 1;
318 }
319
320 rc = fpga_load (dev, fit_data, data_size);
321 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100322 break;
323#endif
324 default:
325 puts ("** Unknown image type\n");
326 rc = FPGA_FAIL;
327 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200328 }
329 break;
330
wdenkd4ca31c2004-01-02 14:00:00 +0000331 case FPGA_DUMP:
332 rc = fpga_dump (dev, fpga_data, data_size);
333 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000334
wdenkd4ca31c2004-01-02 14:00:00 +0000335 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200336 printf ("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000337 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000338 }
339 return (rc);
wdenk4a9cbbe2002-08-27 09:48:53 +0000340}
341
wdenk4a9cbbe2002-08-27 09:48:53 +0000342/*
343 * Map op to supported operations. We don't use a table since we
344 * would just have to relocate it from flash anyway.
345 */
wdenkd4ca31c2004-01-02 14:00:00 +0000346static int fpga_get_op (char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000347{
348 int op = FPGA_NONE;
349
350 if (!strcmp ("info", opstr)) {
351 op = FPGA_INFO;
wdenk30ce5ab2005-01-09 18:12:51 +0000352 } else if (!strcmp ("loadb", opstr)) {
353 op = FPGA_LOADB;
wdenkd4ca31c2004-01-02 14:00:00 +0000354 } else if (!strcmp ("load", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000355 op = FPGA_LOAD;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200356 } else if (!strcmp ("loadmk", opstr)) {
357 op = FPGA_LOADMK;
wdenkd4ca31c2004-01-02 14:00:00 +0000358 } else if (!strcmp ("dump", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000359 op = FPGA_DUMP;
360 }
361
wdenkd4ca31c2004-01-02 14:00:00 +0000362 if (op == FPGA_NONE) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000363 printf ("Unknown fpga operation \"%s\"\n", opstr);
364 }
365 return op;
366}
367
wdenkd4ca31c2004-01-02 14:00:00 +0000368U_BOOT_CMD (fpga, 6, 1, do_fpga,
Stefano Babica790b5b2010-10-19 09:22:52 +0200369 "loadable FPGA image support",
370 "[operation type] [device number] [image address] [image size]\n"
371 "fpga operations:\n"
372 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
373 " info\t[dev]\t\t\tlist known device information\n"
374 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
375 " loadb\t[dev] [address] [size]\t"
376 "Load device from bitstream buffer (Xilinx only)\n"
377 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100378#if defined(CONFIG_FIT)
Stefano Babica790b5b2010-10-19 09:22:52 +0200379 "\n"
380 "\tFor loadmk operating on FIT format uImage address must include\n"
381 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100382#endif
383);