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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbelle24ea552014-05-05 14:42:31 +01002/*
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
6 *
7 * MMC driver for allwinner sunxi platform.
Andre Przywaraba16b532022-07-13 17:21:44 +01008 *
9 * This driver is used by the (ARM) SPL with the legacy MMC interface, and
10 * by U-Boot proper using the full DM interface. The actual hardware access
11 * code is common, and comes first in this file.
12 * The legacy MMC interface implementation comes next, followed by the
13 * proper DM_MMC implementation at the end.
Ian Campbelle24ea552014-05-05 14:42:31 +010014 */
15
16#include <common.h>
Simon Glassdd279182017-07-04 13:31:27 -060017#include <dm.h>
Hans de Goede90641f82015-04-22 17:03:17 +020018#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060019#include <log.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010020#include <malloc.h>
21#include <mmc.h>
Andre Przywarac57572e2019-01-29 15:54:13 +000022#include <clk.h>
23#include <reset.h>
Samuel Holland42508462021-09-11 16:50:47 -050024#include <asm/gpio.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010025#include <asm/io.h>
26#include <asm/arch/clock.h>
27#include <asm/arch/cpu.h>
28#include <asm/arch/mmc.h>
Simon Glassc05ed002020-05-10 11:40:11 -060029#include <linux/delay.h>
Andre Przywara207ed0a2022-09-06 10:36:38 +010030#include <sunxi_gpio.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010031
Andre Przywaraf85c0912021-05-05 09:57:47 +010032#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
33#define CCM_MMC_CTRL_MODE_SEL_NEW 0
34#endif
35
Simon Glassdd279182017-07-04 13:31:27 -060036struct sunxi_mmc_plat {
37 struct mmc_config cfg;
38 struct mmc mmc;
39};
40
Simon Glasse3c794e2017-07-04 13:31:23 -060041struct sunxi_mmc_priv {
Ian Campbelle24ea552014-05-05 14:42:31 +010042 unsigned mmc_no;
43 uint32_t *mclkreg;
Ian Campbelle24ea552014-05-05 14:42:31 +010044 unsigned fatal_err;
Simon Glassdd279182017-07-04 13:31:27 -060045 struct gpio_desc cd_gpio; /* Change Detect GPIO */
Ian Campbelle24ea552014-05-05 14:42:31 +010046 struct sunxi_mmc *reg;
47 struct mmc_config cfg;
48};
49
Andre Przywarab5dd39c2021-05-05 10:06:24 +010050/*
51 * All A64 and later MMC controllers feature auto-calibration. This would
52 * normally be detected via the compatible string, but we need something
53 * which works in the SPL as well.
54 */
55static bool sunxi_mmc_can_calibrate(void)
56{
57 return IS_ENABLED(CONFIG_MACH_SUN50I) ||
58 IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
59 IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
Andre Przywara4a9e89a2022-10-05 17:54:19 +010060 IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
Andre Przywarab5dd39c2021-05-05 10:06:24 +010061 IS_ENABLED(CONFIG_MACH_SUN8I_R40);
62}
63
Simon Glass3f5af122017-07-04 13:31:24 -060064static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
Hans de Goedefc3a8322014-12-07 20:55:10 +010065{
66 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
Andre Przywaraf85c0912021-05-05 09:57:47 +010067 bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
Maxime Ripardde9b1772017-08-23 12:03:41 +020068 u32 val = 0;
69
Vasily Khoruzhick0e21a2f2018-11-09 20:41:46 -080070 /* A83T support new mode only on eMMC */
71 if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
72 new_mode = false;
Maxime Ripardde9b1772017-08-23 12:03:41 +020073
Hans de Goedefc3a8322014-12-07 20:55:10 +010074 if (hz <= 24000000) {
75 pll = CCM_MMC_CTRL_OSCM24;
76 pll_hz = 24000000;
77 } else {
Hans de Goededaf22632015-01-14 19:05:03 +010078#ifdef CONFIG_MACH_SUN9I
79 pll = CCM_MMC_CTRL_PLL_PERIPH0;
80 pll_hz = clock_get_pll4_periph0();
81#else
Andre Przywara937ee312021-05-05 09:57:47 +010082 /*
83 * SoCs since the A64 (H5, H6, H616) actually use the doubled
84 * rate of PLL6/PERIPH0 as an input clock, but compensate for
85 * that with a fixed post-divider of 2 in the mod clock.
86 * This cancels each other out, so for simplicity we just
87 * pretend it's always PLL6 without a post divider here.
88 */
Hans de Goedefc3a8322014-12-07 20:55:10 +010089 pll = CCM_MMC_CTRL_PLL6;
90 pll_hz = clock_get_pll6();
Hans de Goededaf22632015-01-14 19:05:03 +010091#endif
Hans de Goedefc3a8322014-12-07 20:55:10 +010092 }
93
94 div = pll_hz / hz;
95 if (pll_hz % hz)
96 div++;
97
98 n = 0;
99 while (div > 16) {
100 n++;
101 div = (div + 1) / 2;
102 }
103
104 if (n > 3) {
Simon Glass3f5af122017-07-04 13:31:24 -0600105 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
106 hz);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100107 return -1;
108 }
109
110 /* determine delays */
111 if (hz <= 400000) {
112 oclk_dly = 0;
Hans de Goedebe909742015-09-23 16:13:10 +0200113 sclk_dly = 0;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100114 } else if (hz <= 25000000) {
115 oclk_dly = 0;
116 sclk_dly = 5;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100117 } else {
Andre Przywaraf4826fb2020-12-18 22:02:11 +0000118 if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
119 if (hz <= 52000000)
120 oclk_dly = 5;
121 else
122 oclk_dly = 2;
123 } else {
124 if (hz <= 52000000)
125 oclk_dly = 3;
126 else
127 oclk_dly = 1;
128 }
Hans de Goedefc3a8322014-12-07 20:55:10 +0100129 sclk_dly = 4;
130 }
131
Maxime Ripardde9b1772017-08-23 12:03:41 +0200132 if (new_mode) {
Andre Przywaraf85c0912021-05-05 09:57:47 +0100133 val |= CCM_MMC_CTRL_MODE_SEL_NEW;
Chen-Yu Tsai8a647fc2017-08-31 21:57:48 +0800134 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
Andre Przywarab5dd39c2021-05-05 10:06:24 +0100135 }
136
137 if (!sunxi_mmc_can_calibrate()) {
Vasily Khoruzhick20940ef2018-11-05 20:24:28 -0800138 /*
139 * Use hardcoded delay values if controller doesn't support
140 * calibration
141 */
Maxime Ripardde9b1772017-08-23 12:03:41 +0200142 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
143 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
144 }
145
146 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
147 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100148
149 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
Simon Glass3f5af122017-07-04 13:31:24 -0600150 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100151
152 return 0;
153}
154
Simon Glass034e2262017-07-04 13:31:25 -0600155static int mmc_update_clk(struct sunxi_mmc_priv *priv)
Ian Campbelle24ea552014-05-05 14:42:31 +0100156{
Ian Campbelle24ea552014-05-05 14:42:31 +0100157 unsigned int cmd;
158 unsigned timeout_msecs = 2000;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100159 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100160
161 cmd = SUNXI_MMC_CMD_START |
162 SUNXI_MMC_CMD_UPCLK_ONLY |
163 SUNXI_MMC_CMD_WAIT_PRE_OVER;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100164
Simon Glass3f5af122017-07-04 13:31:24 -0600165 writel(cmd, &priv->reg->cmd);
166 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100167 if (get_timer(start) > timeout_msecs)
Ian Campbelle24ea552014-05-05 14:42:31 +0100168 return -1;
Ian Campbelle24ea552014-05-05 14:42:31 +0100169 }
170
171 /* clock update sets various irq status bits, clear these */
Simon Glass3f5af122017-07-04 13:31:24 -0600172 writel(readl(&priv->reg->rint), &priv->reg->rint);
Ian Campbelle24ea552014-05-05 14:42:31 +0100173
174 return 0;
175}
176
Simon Glass034e2262017-07-04 13:31:25 -0600177static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
Ian Campbelle24ea552014-05-05 14:42:31 +0100178{
Simon Glass3f5af122017-07-04 13:31:24 -0600179 unsigned rval = readl(&priv->reg->clkcr);
Ian Campbelle24ea552014-05-05 14:42:31 +0100180
181 /* Disable Clock */
182 rval &= ~SUNXI_MMC_CLK_ENABLE;
Simon Glass3f5af122017-07-04 13:31:24 -0600183 writel(rval, &priv->reg->clkcr);
Simon Glass034e2262017-07-04 13:31:25 -0600184 if (mmc_update_clk(priv))
Ian Campbelle24ea552014-05-05 14:42:31 +0100185 return -1;
186
Hans de Goedefc3a8322014-12-07 20:55:10 +0100187 /* Set mod_clk to new rate */
Simon Glass3f5af122017-07-04 13:31:24 -0600188 if (mmc_set_mod_clk(priv, mmc->clock))
Ian Campbelle24ea552014-05-05 14:42:31 +0100189 return -1;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100190
191 /* Clear internal divider */
192 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
Simon Glass3f5af122017-07-04 13:31:24 -0600193 writel(rval, &priv->reg->clkcr);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100194
Andre Przywara4a9e89a2022-10-05 17:54:19 +0100195#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
Vasily Khoruzhick20940ef2018-11-05 20:24:28 -0800196 /* A64 supports calibration of delays on MMC controller and we
197 * have to set delay of zero before starting calibration.
198 * Allwinner BSP driver sets a delay only in the case of
199 * using HS400 which is not supported by mainline U-Boot or
200 * Linux at the moment
201 */
Andre Przywarab5dd39c2021-05-05 10:06:24 +0100202 if (sunxi_mmc_can_calibrate())
203 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
Vasily Khoruzhick20940ef2018-11-05 20:24:28 -0800204#endif
205
Ian Campbelle24ea552014-05-05 14:42:31 +0100206 /* Re-enable Clock */
207 rval |= SUNXI_MMC_CLK_ENABLE;
Simon Glass3f5af122017-07-04 13:31:24 -0600208 writel(rval, &priv->reg->clkcr);
Simon Glass034e2262017-07-04 13:31:25 -0600209 if (mmc_update_clk(priv))
Ian Campbelle24ea552014-05-05 14:42:31 +0100210 return -1;
211
212 return 0;
213}
214
Simon Glass034e2262017-07-04 13:31:25 -0600215static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
216 struct mmc *mmc)
Ian Campbelle24ea552014-05-05 14:42:31 +0100217{
Hans de Goedefc3a8322014-12-07 20:55:10 +0100218 debug("set ios: bus_width: %x, clock: %d\n",
219 mmc->bus_width, mmc->clock);
Ian Campbelle24ea552014-05-05 14:42:31 +0100220
221 /* Change clock first */
Simon Glass034e2262017-07-04 13:31:25 -0600222 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
Simon Glass3f5af122017-07-04 13:31:24 -0600223 priv->fatal_err = 1;
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900224 return -EINVAL;
Ian Campbelle24ea552014-05-05 14:42:31 +0100225 }
226
227 /* Change bus width */
228 if (mmc->bus_width == 8)
Simon Glass3f5af122017-07-04 13:31:24 -0600229 writel(0x2, &priv->reg->width);
Ian Campbelle24ea552014-05-05 14:42:31 +0100230 else if (mmc->bus_width == 4)
Simon Glass3f5af122017-07-04 13:31:24 -0600231 writel(0x1, &priv->reg->width);
Ian Campbelle24ea552014-05-05 14:42:31 +0100232 else
Simon Glass3f5af122017-07-04 13:31:24 -0600233 writel(0x0, &priv->reg->width);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900234
235 return 0;
Ian Campbelle24ea552014-05-05 14:42:31 +0100236}
237
Simon Glass034e2262017-07-04 13:31:25 -0600238static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
239 struct mmc_data *data)
Ian Campbelle24ea552014-05-05 14:42:31 +0100240{
Ian Campbelle24ea552014-05-05 14:42:31 +0100241 const int reading = !!(data->flags & MMC_DATA_READ);
242 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
243 SUNXI_MMC_STATUS_FIFO_FULL;
244 unsigned i;
Ian Campbelle24ea552014-05-05 14:42:31 +0100245 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
Andre Przywara9faae542021-05-05 11:33:40 +0100246 unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
247 unsigned timeout_msecs = word_cnt >> 6;
248 uint32_t status;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100249 unsigned long start;
250
251 if (timeout_msecs < 2000)
252 timeout_msecs = 2000;
Ian Campbelle24ea552014-05-05 14:42:31 +0100253
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200254 /* Always read / write data through the CPU */
Simon Glass3f5af122017-07-04 13:31:24 -0600255 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200256
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100257 start = get_timer(0);
258
Andre Przywara9faae542021-05-05 11:33:40 +0100259 for (i = 0; i < word_cnt;) {
260 unsigned int in_fifo;
261
262 while ((status = readl(&priv->reg->status)) & status_bit) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100263 if (get_timer(start) > timeout_msecs)
Ian Campbelle24ea552014-05-05 14:42:31 +0100264 return -1;
Ian Campbelle24ea552014-05-05 14:42:31 +0100265 }
266
Andre Przywara9faae542021-05-05 11:33:40 +0100267 /*
268 * For writing we do not easily know the FIFO size, so have
269 * to check the FIFO status after every word written.
270 * TODO: For optimisation we could work out a minimum FIFO
271 * size across all SoCs, and use that together with the current
272 * fill level to write chunks of words.
273 */
274 if (!reading) {
275 writel(buff[i++], &priv->reg->fifo);
276 continue;
277 }
278
279 /*
280 * The status register holds the current FIFO level, so we
281 * can be sure to collect as many words from the FIFO
282 * register without checking the status register after every
283 * read. That saves half of the costly MMIO reads, effectively
284 * doubling the read performance.
Andre Przywara0b508ca2021-09-03 16:49:16 +0100285 * Some SoCs (A20) report a level of 0 if the FIFO is
286 * completely full (value masked out?). Use a safe minimal
287 * FIFO size in this case.
Andre Przywara9faae542021-05-05 11:33:40 +0100288 */
Andre Przywara0b508ca2021-09-03 16:49:16 +0100289 in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
290 if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
291 in_fifo = 32;
292 for (; in_fifo > 0; in_fifo--)
Andre Przywara9faae542021-05-05 11:33:40 +0100293 buff[i++] = readl_relaxed(&priv->reg->fifo);
294 dmb();
Ian Campbelle24ea552014-05-05 14:42:31 +0100295 }
296
297 return 0;
298}
299
Simon Glass034e2262017-07-04 13:31:25 -0600300static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
301 uint timeout_msecs, uint done_bit, const char *what)
Ian Campbelle24ea552014-05-05 14:42:31 +0100302{
Ian Campbelle24ea552014-05-05 14:42:31 +0100303 unsigned int status;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100304 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100305
306 do {
Simon Glass3f5af122017-07-04 13:31:24 -0600307 status = readl(&priv->reg->rint);
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100308 if ((get_timer(start) > timeout_msecs) ||
Ian Campbelle24ea552014-05-05 14:42:31 +0100309 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
310 debug("%s timeout %x\n", what,
311 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900312 return -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100313 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100314 } while (!(status & done_bit));
315
316 return 0;
317}
318
Simon Glass034e2262017-07-04 13:31:25 -0600319static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
320 struct mmc *mmc, struct mmc_cmd *cmd,
321 struct mmc_data *data)
Ian Campbelle24ea552014-05-05 14:42:31 +0100322{
Ian Campbelle24ea552014-05-05 14:42:31 +0100323 unsigned int cmdval = SUNXI_MMC_CMD_START;
324 unsigned int timeout_msecs;
325 int error = 0;
326 unsigned int status = 0;
Ian Campbelle24ea552014-05-05 14:42:31 +0100327 unsigned int bytecnt = 0;
328
Simon Glass3f5af122017-07-04 13:31:24 -0600329 if (priv->fatal_err)
Ian Campbelle24ea552014-05-05 14:42:31 +0100330 return -1;
331 if (cmd->resp_type & MMC_RSP_BUSY)
332 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
333 if (cmd->cmdidx == 12)
334 return 0;
335
336 if (!cmd->cmdidx)
337 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
338 if (cmd->resp_type & MMC_RSP_PRESENT)
339 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
340 if (cmd->resp_type & MMC_RSP_136)
341 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
342 if (cmd->resp_type & MMC_RSP_CRC)
343 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
344
345 if (data) {
Alexander Graf0ea5a042016-03-29 17:29:09 +0200346 if ((u32)(long)data->dest & 0x3) {
Ian Campbelle24ea552014-05-05 14:42:31 +0100347 error = -1;
348 goto out;
349 }
350
351 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
352 if (data->flags & MMC_DATA_WRITE)
353 cmdval |= SUNXI_MMC_CMD_WRITE;
354 if (data->blocks > 1)
355 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
Simon Glass3f5af122017-07-04 13:31:24 -0600356 writel(data->blocksize, &priv->reg->blksz);
357 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
Ian Campbelle24ea552014-05-05 14:42:31 +0100358 }
359
Simon Glass3f5af122017-07-04 13:31:24 -0600360 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
Ian Campbelle24ea552014-05-05 14:42:31 +0100361 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
Simon Glass3f5af122017-07-04 13:31:24 -0600362 writel(cmd->cmdarg, &priv->reg->arg);
Ian Campbelle24ea552014-05-05 14:42:31 +0100363
364 if (!data)
Simon Glass3f5af122017-07-04 13:31:24 -0600365 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
Ian Campbelle24ea552014-05-05 14:42:31 +0100366
367 /*
368 * transfer data and check status
369 * STATREG[2] : FIFO empty
370 * STATREG[3] : FIFO full
371 */
372 if (data) {
373 int ret = 0;
374
375 bytecnt = data->blocksize * data->blocks;
376 debug("trans data %d bytes\n", bytecnt);
Simon Glass3f5af122017-07-04 13:31:24 -0600377 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
Simon Glass034e2262017-07-04 13:31:25 -0600378 ret = mmc_trans_data_by_cpu(priv, mmc, data);
Ian Campbelle24ea552014-05-05 14:42:31 +0100379 if (ret) {
Simon Glass3f5af122017-07-04 13:31:24 -0600380 error = readl(&priv->reg->rint) &
Ian Campbelle24ea552014-05-05 14:42:31 +0100381 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900382 error = -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100383 goto out;
384 }
385 }
386
Simon Glass034e2262017-07-04 13:31:25 -0600387 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
388 "cmd");
Ian Campbelle24ea552014-05-05 14:42:31 +0100389 if (error)
390 goto out;
391
392 if (data) {
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200393 timeout_msecs = 120;
Ian Campbelle24ea552014-05-05 14:42:31 +0100394 debug("cacl timeout %x msec\n", timeout_msecs);
Simon Glass034e2262017-07-04 13:31:25 -0600395 error = mmc_rint_wait(priv, mmc, timeout_msecs,
Ian Campbelle24ea552014-05-05 14:42:31 +0100396 data->blocks > 1 ?
397 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
398 SUNXI_MMC_RINT_DATA_OVER,
399 "data");
400 if (error)
401 goto out;
402 }
403
404 if (cmd->resp_type & MMC_RSP_BUSY) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100405 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100406 timeout_msecs = 2000;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100407
Ian Campbelle24ea552014-05-05 14:42:31 +0100408 do {
Simon Glass3f5af122017-07-04 13:31:24 -0600409 status = readl(&priv->reg->status);
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100410 if (get_timer(start) > timeout_msecs) {
Ian Campbelle24ea552014-05-05 14:42:31 +0100411 debug("busy timeout\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900412 error = -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100413 goto out;
414 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100415 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
416 }
417
418 if (cmd->resp_type & MMC_RSP_136) {
Simon Glass3f5af122017-07-04 13:31:24 -0600419 cmd->response[0] = readl(&priv->reg->resp3);
420 cmd->response[1] = readl(&priv->reg->resp2);
421 cmd->response[2] = readl(&priv->reg->resp1);
422 cmd->response[3] = readl(&priv->reg->resp0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100423 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
424 cmd->response[3], cmd->response[2],
425 cmd->response[1], cmd->response[0]);
426 } else {
Simon Glass3f5af122017-07-04 13:31:24 -0600427 cmd->response[0] = readl(&priv->reg->resp0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100428 debug("mmc resp 0x%08x\n", cmd->response[0]);
429 }
430out:
Ian Campbelle24ea552014-05-05 14:42:31 +0100431 if (error < 0) {
Simon Glass3f5af122017-07-04 13:31:24 -0600432 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
Simon Glass034e2262017-07-04 13:31:25 -0600433 mmc_update_clk(priv);
Ian Campbelle24ea552014-05-05 14:42:31 +0100434 }
Simon Glass3f5af122017-07-04 13:31:24 -0600435 writel(0xffffffff, &priv->reg->rint);
436 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
437 &priv->reg->gctrl);
Ian Campbelle24ea552014-05-05 14:42:31 +0100438
439 return error;
440}
441
Andre Przywaraba16b532022-07-13 17:21:44 +0100442/* non-DM code here is used by the (ARM) SPL only */
443
Simon Glassdd279182017-07-04 13:31:27 -0600444#if !CONFIG_IS_ENABLED(DM_MMC)
Andre Przywaraba16b532022-07-13 17:21:44 +0100445/* support 4 mmc hosts */
446struct sunxi_mmc_priv mmc_host[4];
447
448static int mmc_resource_init(int sdc_no)
449{
450 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
451 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
452
453 debug("init mmc %d resource\n", sdc_no);
454
455 switch (sdc_no) {
456 case 0:
457 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
458 priv->mclkreg = &ccm->sd0_clk_cfg;
459 break;
460 case 1:
461 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
462 priv->mclkreg = &ccm->sd1_clk_cfg;
463 break;
464#ifdef SUNXI_MMC2_BASE
465 case 2:
466 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
467 priv->mclkreg = &ccm->sd2_clk_cfg;
468 break;
469#endif
470#ifdef SUNXI_MMC3_BASE
471 case 3:
472 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
473 priv->mclkreg = &ccm->sd3_clk_cfg;
474 break;
475#endif
476 default:
477 printf("Wrong mmc number %d\n", sdc_no);
478 return -1;
479 }
480 priv->mmc_no = sdc_no;
481
482 return 0;
483}
484
485static int sunxi_mmc_core_init(struct mmc *mmc)
486{
487 struct sunxi_mmc_priv *priv = mmc->priv;
488
489 /* Reset controller */
490 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
491 udelay(1000);
492
493 return 0;
494}
495
Simon Glass034e2262017-07-04 13:31:25 -0600496static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
497{
498 struct sunxi_mmc_priv *priv = mmc->priv;
499
500 return sunxi_mmc_set_ios_common(priv, mmc);
501}
502
503static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
504 struct mmc_data *data)
505{
506 struct sunxi_mmc_priv *priv = mmc->priv;
507
508 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
509}
510
Andre Przywara5db81f12022-07-13 17:21:43 +0100511/* .getcd is not needed by the SPL */
Ian Campbelle24ea552014-05-05 14:42:31 +0100512static const struct mmc_ops sunxi_mmc_ops = {
Simon Glass034e2262017-07-04 13:31:25 -0600513 .send_cmd = sunxi_mmc_send_cmd_legacy,
514 .set_ios = sunxi_mmc_set_ios_legacy,
Siarhei Siamashka5abdb152015-02-01 00:42:14 +0200515 .init = sunxi_mmc_core_init,
Ian Campbelle24ea552014-05-05 14:42:31 +0100516};
517
Hans de Goedee79c7c82014-10-02 21:13:54 +0200518struct mmc *sunxi_mmc_init(int sdc_no)
Ian Campbelle24ea552014-05-05 14:42:31 +0100519{
Simon Glassec73d962017-07-04 13:31:26 -0600520 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Simon Glass034e2262017-07-04 13:31:25 -0600521 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
522 struct mmc_config *cfg = &priv->cfg;
Simon Glassec73d962017-07-04 13:31:26 -0600523 int ret;
Ian Campbelle24ea552014-05-05 14:42:31 +0100524
Simon Glass034e2262017-07-04 13:31:25 -0600525 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
Ian Campbelle24ea552014-05-05 14:42:31 +0100526
527 cfg->name = "SUNXI SD/MMC";
528 cfg->ops = &sunxi_mmc_ops;
529
530 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
531 cfg->host_caps = MMC_MODE_4BIT;
Andre Przywaraf4826fb2020-12-18 22:02:11 +0000532
533 if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
534 IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200535 cfg->host_caps = MMC_MODE_8BIT;
Andre Przywaraf4826fb2020-12-18 22:02:11 +0000536
Rob Herring5a203972015-03-23 17:56:59 -0500537 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Ian Campbelle24ea552014-05-05 14:42:31 +0100538 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
539
540 cfg->f_min = 400000;
541 cfg->f_max = 52000000;
542
Hans de Goede967325f2014-10-31 16:55:02 +0100543 if (mmc_resource_init(sdc_no) != 0)
544 return NULL;
545
Simon Glassec73d962017-07-04 13:31:26 -0600546 /* config ahb clock */
547 debug("init mmc %d clock and io\n", sdc_no);
Andre Przywara4a9e89a2022-10-05 17:54:19 +0100548#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2)
Simon Glassec73d962017-07-04 13:31:26 -0600549 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
550
551#ifdef CONFIG_SUNXI_GEN_SUN6I
552 /* unassert reset */
553 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
554#endif
555#if defined(CONFIG_MACH_SUN9I)
556 /* sun9i has a mmc-common module, also set the gate and reset there */
557 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
558 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
559#endif
Jernej Skrabecaaebb902021-01-11 21:11:35 +0100560#else /* CONFIG_SUN50I_GEN_H6 */
Icenowy Zheng42956f12018-07-21 16:20:29 +0800561 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
562 /* unassert reset */
563 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
564#endif
Simon Glassec73d962017-07-04 13:31:26 -0600565 ret = mmc_set_mod_clk(priv, 24000000);
566 if (ret)
567 return NULL;
Ian Campbelle24ea552014-05-05 14:42:31 +0100568
Maxime Ripardead36972017-08-23 13:41:33 +0200569 return mmc_create(cfg, priv);
Ian Campbelle24ea552014-05-05 14:42:31 +0100570}
Andre Przywaraba16b532022-07-13 17:21:44 +0100571
572#else /* CONFIG_DM_MMC code below, as used by U-Boot proper */
Simon Glassdd279182017-07-04 13:31:27 -0600573
574static int sunxi_mmc_set_ios(struct udevice *dev)
575{
Simon Glassc69cda22020-12-03 16:55:20 -0700576 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600577 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
578
579 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
580}
581
582static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
583 struct mmc_data *data)
584{
Simon Glassc69cda22020-12-03 16:55:20 -0700585 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600586 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
587
588 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
589}
590
591static int sunxi_mmc_getcd(struct udevice *dev)
592{
Andre Przywaraac62dad2021-04-21 09:33:04 +0100593 struct mmc *mmc = mmc_get_mmc_dev(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600594 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
595
Andre Przywaraac62dad2021-04-21 09:33:04 +0100596 /* If polling, assume that the card is always present. */
597 if ((mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE) ||
598 (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL))
599 return 1;
600
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +0100601 if (dm_gpio_is_valid(&priv->cd_gpio)) {
602 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
Simon Glassdd279182017-07-04 13:31:27 -0600603
Andre Przywaraac62dad2021-04-21 09:33:04 +0100604 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
605 return !cd_state;
606 else
607 return cd_state;
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +0100608 }
Simon Glassdd279182017-07-04 13:31:27 -0600609 return 1;
610}
611
612static const struct dm_mmc_ops sunxi_mmc_ops = {
613 .send_cmd = sunxi_mmc_send_cmd,
614 .set_ios = sunxi_mmc_set_ios,
615 .get_cd = sunxi_mmc_getcd,
616};
617
Andre Przywara0237b302021-01-11 21:11:44 +0100618static unsigned get_mclk_offset(void)
619{
620 if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
621 return 0x410;
622
Andre Przywara4a9e89a2022-10-05 17:54:19 +0100623 if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
Andre Przywara0237b302021-01-11 21:11:44 +0100624 return 0x830;
625
626 return 0x88;
627};
628
Simon Glassdd279182017-07-04 13:31:27 -0600629static int sunxi_mmc_probe(struct udevice *dev)
630{
631 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700632 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600633 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
Andre Przywarac57572e2019-01-29 15:54:13 +0000634 struct reset_ctl_bulk reset_bulk;
635 struct clk gate_clk;
Simon Glassdd279182017-07-04 13:31:27 -0600636 struct mmc_config *cfg = &plat->cfg;
637 struct ofnode_phandle_args args;
Andre Przywarac57572e2019-01-29 15:54:13 +0000638 u32 *ccu_reg;
Andre Przywaraac62dad2021-04-21 09:33:04 +0100639 int ret;
Simon Glassdd279182017-07-04 13:31:27 -0600640
641 cfg->name = dev->name;
Simon Glassdd279182017-07-04 13:31:27 -0600642
643 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Andre Przywaraac62dad2021-04-21 09:33:04 +0100644 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
Simon Glassdd279182017-07-04 13:31:27 -0600645 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
646
647 cfg->f_min = 400000;
648 cfg->f_max = 52000000;
649
Andre Przywaraac62dad2021-04-21 09:33:04 +0100650 ret = mmc_of_parse(dev, cfg);
651 if (ret)
652 return ret;
653
Andre Przywaraca496ba2021-04-29 09:31:58 +0100654 priv->reg = dev_read_addr_ptr(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600655
656 /* We don't have a sunxi clock driver so find the clock address here */
657 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
658 1, &args);
659 if (ret)
660 return ret;
Andre Przywaraca496ba2021-04-29 09:31:58 +0100661 ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
Simon Glassdd279182017-07-04 13:31:27 -0600662
Jagan Tekie8f37f42019-01-09 16:58:39 +0530663 priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
Andre Przywara0237b302021-01-11 21:11:44 +0100664 priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
Andre Przywarac57572e2019-01-29 15:54:13 +0000665
666 ret = clk_get_by_name(dev, "ahb", &gate_clk);
667 if (!ret)
668 clk_enable(&gate_clk);
669
670 ret = reset_get_bulk(dev, &reset_bulk);
671 if (!ret)
672 reset_deassert_bulk(&reset_bulk);
Simon Glassdd279182017-07-04 13:31:27 -0600673
674 ret = mmc_set_mod_clk(priv, 24000000);
675 if (ret)
676 return ret;
677
678 /* This GPIO is optional */
Samuel Hollandfb6f6702021-10-20 23:52:57 -0500679 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
680 GPIOD_IS_IN | GPIOD_PULL_UP);
Simon Glassdd279182017-07-04 13:31:27 -0600681
682 upriv->mmc = &plat->mmc;
683
684 /* Reset controller */
685 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
686 udelay(1000);
687
688 return 0;
689}
690
691static int sunxi_mmc_bind(struct udevice *dev)
692{
Simon Glassc69cda22020-12-03 16:55:20 -0700693 struct sunxi_mmc_plat *plat = dev_get_plat(dev);
Simon Glassdd279182017-07-04 13:31:27 -0600694
695 return mmc_bind(dev, &plat->mmc, &plat->cfg);
696}
697
698static const struct udevice_id sunxi_mmc_ids[] = {
Andre Przywara0237b302021-01-11 21:11:44 +0100699 { .compatible = "allwinner,sun4i-a10-mmc" },
700 { .compatible = "allwinner,sun5i-a13-mmc" },
701 { .compatible = "allwinner,sun7i-a20-mmc" },
702 { .compatible = "allwinner,sun8i-a83t-emmc" },
703 { .compatible = "allwinner,sun9i-a80-mmc" },
704 { .compatible = "allwinner,sun50i-a64-mmc" },
705 { .compatible = "allwinner,sun50i-a64-emmc" },
706 { .compatible = "allwinner,sun50i-h6-mmc" },
707 { .compatible = "allwinner,sun50i-h6-emmc" },
708 { .compatible = "allwinner,sun50i-a100-mmc" },
709 { .compatible = "allwinner,sun50i-a100-emmc" },
Andre Przywara95168d72022-09-06 15:59:57 +0100710 { .compatible = "allwinner,sun20i-d1-mmc" },
Jagan Tekie8f37f42019-01-09 16:58:39 +0530711 { /* sentinel */ }
Simon Glassdd279182017-07-04 13:31:27 -0600712};
713
714U_BOOT_DRIVER(sunxi_mmc_drv) = {
715 .name = "sunxi_mmc",
716 .id = UCLASS_MMC,
717 .of_match = sunxi_mmc_ids,
718 .bind = sunxi_mmc_bind,
719 .probe = sunxi_mmc_probe,
720 .ops = &sunxi_mmc_ops,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700721 .plat_auto = sizeof(struct sunxi_mmc_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700722 .priv_auto = sizeof(struct sunxi_mmc_priv),
Simon Glassdd279182017-07-04 13:31:27 -0600723};
724#endif