| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 6 | * |
| Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 8 | */ |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 9 | |
| Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 10 | #include <asm-offsets.h> |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 11 | #include <ppc_asm.tmpl> |
| 12 | #include <config.h> |
| Peter Tyser | 61f2b38 | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 13 | #include <asm/mmu.h> |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 14 | |
| 15 | /************************************************************************** |
| 16 | * TLB TABLE |
| 17 | * |
| 18 | * This table is used by the cpu boot code to setup the initial tlb |
| 19 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 20 | * this table lets each board set things up however they like. |
| 21 | * |
| 22 | * Pointer to the table is returned in r1 |
| 23 | * |
| 24 | *************************************************************************/ |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 25 | .section .bootpg,"ax" |
| 26 | .globl tlbtab |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 27 | |
| 28 | tlbtab: |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 29 | tlbtab_start |
| Stefan Roese | c57c798 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 30 | |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 31 | /* |
| 32 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 33 | * speed up boot process. It is patched after relocation to enable SA_I |
| 34 | */ |
| 35 | #ifndef CONFIG_NAND_SPL |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 36 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 37 | #else |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 38 | tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G) |
| 39 | tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 40 | #endif |
| Stefan Roese | c57c798 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 41 | |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 42 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 43 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) |
| Stefan Roese | c57c798 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 44 | |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 45 | /* PCI base & peripherals */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 46 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG) |
| Stefan Roese | 8a316c9 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 47 | |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 48 | tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I) |
| 49 | tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I) |
| Stefan Roese | 8a316c9 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 50 | |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 51 | /* PCI */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 52 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG) |
| 53 | tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG) |
| 54 | tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG) |
| 55 | tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG) |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 56 | |
| 57 | /* USB 2.0 Device */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 58 | tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 59 | |
| 60 | tlbtab_end |
| 61 | |
| 62 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
| 63 | /* |
| 64 | * For NAND booting the first TLB has to be reconfigured to full size |
| 65 | * and with caching disabled after running from RAM! |
| 66 | */ |
| Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
| 68 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 69 | #define TLB02 TLB2(AC_RWX | SA_IG) |
| Stefan Roese | a471db0 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 70 | |
| 71 | .globl reconfig_tlb0 |
| 72 | reconfig_tlb0: |
| 73 | sync |
| 74 | isync |
| 75 | addi r4,r0,0x0000 /* TLB entry #0 */ |
| 76 | lis r5,TLB00@h |
| 77 | ori r5,r5,TLB00@l |
| 78 | tlbwe r5,r4,0x0000 /* Save it out */ |
| 79 | lis r5,TLB01@h |
| 80 | ori r5,r5,TLB01@l |
| 81 | tlbwe r5,r4,0x0001 /* Save it out */ |
| 82 | lis r5,TLB02@h |
| 83 | ori r5,r5,TLB02@l |
| 84 | tlbwe r5,r4,0x0002 /* Save it out */ |
| 85 | sync |
| 86 | isync |
| 87 | blr |
| 88 | #endif |