Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 1 | /* |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 2 | * Copyright 2007,2009 Wind River Systems <www.windriver.com> |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 3 | * Copyright 2007 Embedded Specialties, Inc. |
| 4 | * Copyright 2004, 2007 Freescale Semiconductor. |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * sbc8548 board configuration file |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 11 | * Please refer to doc/README.sbc8548 for more info. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 12 | */ |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 16 | /* |
| 17 | * Top level Makefile configuration choices |
| 18 | */ |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 19 | #ifdef CONFIG_PCI |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 20 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 21 | #define CONFIG_PCI1 |
| 22 | #endif |
| 23 | |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 24 | #ifdef CONFIG_66 |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 25 | #define CONFIG_SYS_CLK_DIV 1 |
| 26 | #endif |
| 27 | |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 28 | #ifdef CONFIG_33 |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 29 | #define CONFIG_SYS_CLK_DIV 2 |
| 30 | #endif |
| 31 | |
Wolfgang Denk | d24f2d3 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 32 | #ifdef CONFIG_PCIE |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 33 | #define CONFIG_PCIE1 |
| 34 | #endif |
| 35 | |
| 36 | /* |
| 37 | * High Level Configuration Options |
| 38 | */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 39 | #define CONFIG_SBC8548 1 /* SBC8548 board specific */ |
| 40 | |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 41 | /* |
| 42 | * If you want to boot from the SODIMM flash, instead of the soldered |
| 43 | * on flash, set this, and change JP12, SW2:8 accordingly. |
| 44 | */ |
| 45 | #undef CONFIG_SYS_ALT_BOOT |
| 46 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 47 | #ifndef CONFIG_SYS_TEXT_BASE |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 48 | #ifdef CONFIG_SYS_ALT_BOOT |
| 49 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 50 | #else |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_TEXT_BASE 0xfffa0000 |
| 52 | #endif |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 53 | #endif |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 54 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 55 | #undef CONFIG_RIO |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 56 | |
| 57 | #ifdef CONFIG_PCI |
| 58 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 59 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 60 | #endif |
| 61 | #ifdef CONFIG_PCIE1 |
| 62 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 63 | #endif |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 64 | |
| 65 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 66 | #define CONFIG_ENV_OVERWRITE |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 67 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 68 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
| 69 | |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 70 | /* |
| 71 | * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] |
| 72 | */ |
| 73 | #ifndef CONFIG_SYS_CLK_DIV |
| 74 | #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ |
| 75 | #endif |
| 76 | #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * These can be toggled for performance analysis, otherwise use default. |
| 80 | */ |
| 81 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 82 | #define CONFIG_BTB /* toggle branch predition */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 83 | |
| 84 | /* |
| 85 | * Only possible on E500 Version 2 or newer cores. |
| 86 | */ |
| 87 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 88 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 90 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 91 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 92 | |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 93 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 94 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 95 | |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 96 | /* DDR Setup */ |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 97 | #undef CONFIG_FSL_DDR_INTERACTIVE |
Paul Gortmaker | 7e44f2b | 2011-12-30 23:53:10 -0500 | [diff] [blame] | 98 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 99 | /* |
| 100 | * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD |
| 101 | * to collide, meaning you couldn't reliably read either. So |
| 102 | * physically remove the LBC PC100 SDRAM module from the board |
Paul Gortmaker | 3e3262b | 2011-12-30 23:53:12 -0500 | [diff] [blame] | 103 | * before enabling the two SPD options below, or check that you |
| 104 | * have the hardware fix on your board via "i2c probe" and looking |
| 105 | * for a device at 0x53. |
Paul Gortmaker | 7e44f2b | 2011-12-30 23:53:10 -0500 | [diff] [blame] | 106 | */ |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 107 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 108 | #undef CONFIG_DDR_SPD |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 109 | |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 110 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 111 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 112 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 114 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 115 | #define CONFIG_VERY_BIG_RAM |
| 116 | |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 117 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 118 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 119 | |
Paul Gortmaker | 3e3262b | 2011-12-30 23:53:12 -0500 | [diff] [blame] | 120 | /* |
| 121 | * The hardware fix for the I2C address collision puts the DDR |
| 122 | * SPD at 0x53, but if we are running on an older board w/o the |
| 123 | * fix, it will still be at 0x51. We check 0x53 1st. |
| 124 | */ |
Kumar Gala | 33b9079 | 2008-08-26 23:15:28 -0500 | [diff] [blame] | 125 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Paul Gortmaker | 3e3262b | 2011-12-30 23:53:12 -0500 | [diff] [blame] | 126 | #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Make sure required options are set |
| 130 | */ |
| 131 | #ifndef CONFIG_SPD_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
Paul Gortmaker | 2a6b3b7 | 2011-12-30 23:53:11 -0500 | [diff] [blame] | 133 | #define CONFIG_SYS_DDR_CONTROL 0xc300c000 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 134 | #endif |
| 135 | |
| 136 | #undef CONFIG_CLOCKS_IN_MHZ |
| 137 | |
| 138 | /* |
| 139 | * FLASH on the Local Bus |
| 140 | * Two banks, one 8MB the other 64MB, using the CFI driver. |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 141 | * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have |
| 142 | * CS0 the 8MB boot flash, and CS6 the 64MB flash. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 143 | * |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 144 | * Default: |
| 145 | * ec00_0000 efff_ffff 64MB SODIMM |
| 146 | * ff80_0000 ffff_ffff 8MB soldered flash |
| 147 | * |
| 148 | * Alternate: |
| 149 | * ef80_0000 efff_ffff 8MB soldered flash |
| 150 | * fc00_0000 ffff_ffff 64MB SODIMM |
| 151 | * |
| 152 | * BR0_8M: |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 153 | * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 |
| 154 | * Port Size = 8 bits = BRx[19:20] = 01 |
| 155 | * Use GPCM = BRx[24:26] = 000 |
| 156 | * Valid = BRx[31] = 1 |
| 157 | * |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 158 | * BR0_64M: |
| 159 | * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 160 | * Port Size = 32 bits = BRx[19:20] = 11 |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 161 | * |
| 162 | * 0 4 8 12 16 20 24 28 |
| 163 | * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M |
| 164 | * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M |
| 165 | */ |
| 166 | #define CONFIG_SYS_BR0_8M 0xff800801 |
| 167 | #define CONFIG_SYS_BR0_64M 0xfc001801 |
| 168 | |
| 169 | /* |
| 170 | * BR6_8M: |
| 171 | * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 |
| 172 | * Port Size = 8 bits = BRx[19:20] = 01 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 173 | * Use GPCM = BRx[24:26] = 000 |
| 174 | * Valid = BRx[31] = 1 |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 175 | |
| 176 | * BR6_64M: |
| 177 | * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 |
| 178 | * Port Size = 32 bits = BRx[19:20] = 11 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 179 | * |
| 180 | * 0 4 8 12 16 20 24 28 |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 181 | * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M |
| 182 | * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M |
| 183 | */ |
| 184 | #define CONFIG_SYS_BR6_8M 0xef800801 |
| 185 | #define CONFIG_SYS_BR6_64M 0xec001801 |
| 186 | |
| 187 | /* |
| 188 | * OR0_8M: |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 189 | * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 |
| 190 | * XAM = OR0[17:18] = 11 |
| 191 | * CSNT = OR0[20] = 1 |
| 192 | * ACS = half cycle delay = OR0[21:22] = 11 |
| 193 | * SCY = 6 = OR0[24:27] = 0110 |
| 194 | * TRLX = use relaxed timing = OR0[29] = 1 |
| 195 | * EAD = use external address latch delay = OR0[31] = 1 |
| 196 | * |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 197 | * OR0_64M: |
| 198 | * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 199 | * |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 200 | * |
| 201 | * 0 4 8 12 16 20 24 28 |
| 202 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M |
| 203 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M |
| 204 | */ |
| 205 | #define CONFIG_SYS_OR0_8M 0xff806e65 |
| 206 | #define CONFIG_SYS_OR0_64M 0xfc006e65 |
| 207 | |
| 208 | /* |
| 209 | * OR6_8M: |
| 210 | * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 211 | * XAM = OR6[17:18] = 11 |
| 212 | * CSNT = OR6[20] = 1 |
| 213 | * ACS = half cycle delay = OR6[21:22] = 11 |
| 214 | * SCY = 6 = OR6[24:27] = 0110 |
| 215 | * TRLX = use relaxed timing = OR6[29] = 1 |
| 216 | * EAD = use external address latch delay = OR6[31] = 1 |
| 217 | * |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 218 | * OR6_64M: |
| 219 | * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 |
| 220 | * |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 221 | * 0 4 8 12 16 20 24 28 |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 222 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M |
| 223 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 224 | */ |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 225 | #define CONFIG_SYS_OR6_8M 0xff806e65 |
| 226 | #define CONFIG_SYS_OR6_64M 0xfc006e65 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 227 | |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 228 | #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 229 | #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
Paul Gortmaker | 3fd673c | 2011-12-30 23:53:07 -0500 | [diff] [blame] | 230 | #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 231 | |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 232 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M |
| 233 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 234 | |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 235 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M |
| 236 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M |
| 237 | #else /* JP12 in alternate position */ |
| 238 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ |
| 239 | #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 240 | |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 241 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M |
| 242 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M |
| 243 | |
| 244 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M |
| 245 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M |
| 246 | #endif |
| 247 | |
| 248 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK |
Paul Gortmaker | 9b3ba24 | 2009-09-18 19:08:41 -0400 | [diff] [blame] | 249 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
| 250 | CONFIG_SYS_ALT_FLASH} |
| 251 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 252 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 254 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 255 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 256 | |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 258 | |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 259 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 260 | #define CONFIG_SYS_FLASH_CFI |
| 261 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 262 | |
| 263 | /* CS5 = Local bus peripherals controlled by the EPLD */ |
| 264 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 265 | #define CONFIG_SYS_BR5_PRELIM 0xf8000801 |
| 266 | #define CONFIG_SYS_OR5_PRELIM 0xff006e65 |
| 267 | #define CONFIG_SYS_EPLD_BASE 0xf8000000 |
| 268 | #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 |
| 269 | #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 |
| 270 | #define CONFIG_SYS_BD_REV 0xf8300000 |
| 271 | #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 272 | |
| 273 | /* |
Paul Gortmaker | 11d5a62 | 2009-09-20 20:36:04 -0400 | [diff] [blame] | 274 | * SDRAM on the Local Bus (CS3 and CS4) |
Paul Gortmaker | 7e44f2b | 2011-12-30 23:53:10 -0500 | [diff] [blame] | 275 | * Note that most boards have a hardware errata where both the |
| 276 | * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible |
| 277 | * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. |
Paul Gortmaker | 3e3262b | 2011-12-30 23:53:12 -0500 | [diff] [blame] | 278 | * A hardware workaround is also available, see README.sbc8548 file. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 279 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
Paul Gortmaker | 11d5a62 | 2009-09-20 20:36:04 -0400 | [diff] [blame] | 281 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 282 | |
| 283 | /* |
Paul Gortmaker | 11d5a62 | 2009-09-20 20:36:04 -0400 | [diff] [blame] | 284 | * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 286 | * |
| 287 | * For BR3, need: |
| 288 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 289 | * port-size = 32-bits = BR2[19:20] = 11 |
| 290 | * no parity checking = BR2[21:22] = 00 |
| 291 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 292 | * Valid = BR[31] = 1 |
| 293 | * |
| 294 | * 0 4 8 12 16 20 24 28 |
| 295 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 296 | * |
| 297 | */ |
| 298 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 300 | |
| 301 | /* |
Paul Gortmaker | 11d5a62 | 2009-09-20 20:36:04 -0400 | [diff] [blame] | 302 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 303 | * |
| 304 | * For OR3, need: |
| 305 | * 64MB mask for AM, OR3[0:7] = 1111 1100 |
| 306 | * XAM, OR3[17:18] = 11 |
| 307 | * 10 columns OR3[19-21] = 011 |
| 308 | * 12 rows OR3[23-25] = 011 |
| 309 | * EAD set for extra time OR[31] = 0 |
| 310 | * |
| 311 | * 0 4 8 12 16 20 24 28 |
| 312 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 |
| 313 | */ |
| 314 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 316 | |
Paul Gortmaker | 11d5a62 | 2009-09-20 20:36:04 -0400 | [diff] [blame] | 317 | /* |
| 318 | * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. |
| 319 | * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. |
| 320 | * |
| 321 | * For BR4, need: |
| 322 | * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 |
| 323 | * port-size = 32-bits = BR2[19:20] = 11 |
| 324 | * no parity checking = BR2[21:22] = 00 |
| 325 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 326 | * Valid = BR[31] = 1 |
| 327 | * |
| 328 | * 0 4 8 12 16 20 24 28 |
| 329 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 |
| 330 | * |
| 331 | */ |
| 332 | |
| 333 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 |
| 334 | |
| 335 | /* |
| 336 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 337 | * |
| 338 | * For OR4, need: |
| 339 | * 64MB mask for AM, OR3[0:7] = 1111 1100 |
| 340 | * XAM, OR3[17:18] = 11 |
| 341 | * 10 columns OR3[19-21] = 011 |
| 342 | * 12 rows OR3[23-25] = 011 |
| 343 | * EAD set for extra time OR[31] = 0 |
| 344 | * |
| 345 | * 0 4 8 12 16 20 24 28 |
| 346 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 |
| 347 | */ |
| 348 | |
| 349 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 |
| 350 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 351 | #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
| 352 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 353 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 354 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 355 | |
| 356 | /* |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 357 | * Common settings for all Local Bus SDRAM commands. |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 358 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 359 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
Paul Gortmaker | 5f4c6f0 | 2011-12-30 23:53:09 -0500 | [diff] [blame] | 360 | | LSDMR_BSMA1516 \ |
| 361 | | LSDMR_PRETOACT3 \ |
| 362 | | LSDMR_ACTTORW3 \ |
| 363 | | LSDMR_BUFCMD \ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 364 | | LSDMR_BL8 \ |
Paul Gortmaker | 5f4c6f0 | 2011-12-30 23:53:09 -0500 | [diff] [blame] | 365 | | LSDMR_WRC2 \ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 366 | | LSDMR_CL3 \ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 367 | ) |
| 368 | |
Paul Gortmaker | 5f4c6f0 | 2011-12-30 23:53:09 -0500 | [diff] [blame] | 369 | #define CONFIG_SYS_LBC_LSDMR_PCHALL \ |
| 370 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 371 | #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ |
| 372 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
| 373 | #define CONFIG_SYS_LBC_LSDMR_MRW \ |
| 374 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) |
| 375 | #define CONFIG_SYS_LBC_LSDMR_RFEN \ |
| 376 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) |
| 377 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 379 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 380 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 381 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 382 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 383 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 384 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 385 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 386 | |
Paul Gortmaker | dd9ca98 | 2009-09-25 11:14:11 -0400 | [diff] [blame] | 387 | /* |
| 388 | * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 389 | * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM |
Paul Gortmaker | dd9ca98 | 2009-09-25 11:14:11 -0400 | [diff] [blame] | 390 | * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 391 | * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right |
Paul Gortmaker | dd9ca98 | 2009-09-25 11:14:11 -0400 | [diff] [blame] | 392 | * thing for MONITOR_LEN in both cases. |
| 393 | */ |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 394 | #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) |
Paul Gortmaker | f0aec4e | 2011-12-30 23:53:08 -0500 | [diff] [blame] | 395 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 396 | |
| 397 | /* Serial Port */ |
| 398 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 399 | #define CONFIG_SYS_NS16550_SERIAL |
| 400 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
Paul Gortmaker | 2738bc8 | 2009-09-20 20:36:06 -0400 | [diff] [blame] | 401 | #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 402 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 403 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 404 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 405 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 406 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 407 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 408 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 409 | /* |
| 410 | * I2C |
| 411 | */ |
Heiko Schocher | 00f792e | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 412 | #define CONFIG_SYS_I2C |
| 413 | #define CONFIG_SYS_I2C_FSL |
| 414 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 415 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 416 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 417 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 418 | |
| 419 | /* |
| 420 | * General PCI |
| 421 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 422 | */ |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 423 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 424 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 425 | |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 426 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
| 427 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 428 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 429 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 430 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
| 431 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
| 432 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| 433 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 434 | |
| 435 | #ifdef CONFIG_PCIE1 |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 436 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
| 437 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
| 438 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 439 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 440 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
| 441 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 442 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
| 443 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | #ifdef CONFIG_RIO |
| 447 | /* |
| 448 | * RapidIO MMU |
| 449 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 450 | #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 |
| 451 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 452 | #endif |
| 453 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 454 | #if defined(CONFIG_PCI) |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 455 | #undef CONFIG_EEPRO100 |
| 456 | #undef CONFIG_TULIP |
| 457 | |
Paul Gortmaker | fdc7eb9 | 2009-09-20 20:36:05 -0400 | [diff] [blame] | 458 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 459 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 460 | #endif /* CONFIG_PCI */ |
| 461 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 462 | #if defined(CONFIG_TSEC_ENET) |
| 463 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 464 | #define CONFIG_MII 1 /* MII PHY management */ |
| 465 | #define CONFIG_TSEC1 1 |
| 466 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 467 | #define CONFIG_TSEC2 1 |
| 468 | #define CONFIG_TSEC2_NAME "eTSEC1" |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 469 | #undef CONFIG_MPC85XX_FEC |
| 470 | |
Paul Gortmaker | 58da889 | 2008-12-11 15:47:50 -0500 | [diff] [blame] | 471 | #define TSEC1_PHY_ADDR 0x19 |
| 472 | #define TSEC2_PHY_ADDR 0x1a |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 473 | |
| 474 | #define TSEC1_PHYIDX 0 |
| 475 | #define TSEC2_PHYIDX 0 |
Paul Gortmaker | bd93105 | 2008-12-11 15:47:49 -0500 | [diff] [blame] | 476 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 477 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 478 | #define TSEC2_FLAGS TSEC_GIGABIT |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 479 | |
| 480 | /* Options are: eTSEC[0-3] */ |
| 481 | #define CONFIG_ETHPRIME "eTSEC0" |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 482 | #endif /* CONFIG_TSEC_ENET */ |
| 483 | |
| 484 | /* |
| 485 | * Environment |
| 486 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 487 | #define CONFIG_ENV_SIZE 0x2000 |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 488 | #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ |
Paul Gortmaker | dd9ca98 | 2009-09-25 11:14:11 -0400 | [diff] [blame] | 489 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) |
| 490 | #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 491 | #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ |
Paul Gortmaker | dd9ca98 | 2009-09-25 11:14:11 -0400 | [diff] [blame] | 492 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 493 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 494 | #else |
| 495 | #warning undefined environment size/location. |
| 496 | #endif |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 497 | |
| 498 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 499 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 500 | |
| 501 | /* |
| 502 | * BOOTP options |
| 503 | */ |
| 504 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 505 | #define CONFIG_BOOTP_BOOTPATH |
| 506 | #define CONFIG_BOOTP_GATEWAY |
| 507 | #define CONFIG_BOOTP_HOSTNAME |
| 508 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 509 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 510 | |
| 511 | /* |
| 512 | * Miscellaneous configurable options |
| 513 | */ |
Paul Gortmaker | ad22f92 | 2008-12-11 15:47:51 -0500 | [diff] [blame] | 514 | #define CONFIG_CMDLINE_EDITING /* undef to save memory */ |
Kim Phillips | 5be58f5 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 515 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 516 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 517 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 518 | |
| 519 | /* |
| 520 | * For booting Linux, the board info and command line data |
| 521 | * have to be in the first 8 MB of memory, since this is |
| 522 | * the maximum mapped by the Linux kernel during initialization. |
| 523 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 524 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 525 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 526 | #if defined(CONFIG_CMD_KGDB) |
| 527 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 528 | #endif |
| 529 | |
| 530 | /* |
| 531 | * Environment Configuration |
| 532 | */ |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 533 | #if defined(CONFIG_TSEC_ENET) |
| 534 | #define CONFIG_HAS_ETH0 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 535 | #define CONFIG_HAS_ETH1 |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 536 | #endif |
| 537 | |
| 538 | #define CONFIG_IPADDR 192.168.0.55 |
| 539 | |
| 540 | #define CONFIG_HOSTNAME sbc8548 |
Joe Hershberger | 8b3637c | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 541 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" |
Joe Hershberger | b3f44c2 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 542 | #define CONFIG_BOOTFILE "/uImage" |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 543 | #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ |
| 544 | |
| 545 | #define CONFIG_SERVERIP 192.168.0.2 |
| 546 | #define CONFIG_GATEWAYIP 192.168.0.1 |
| 547 | #define CONFIG_NETMASK 255.255.255.0 |
| 548 | |
| 549 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
| 550 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 551 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 552 | "netdev=eth0\0" \ |
| 553 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 554 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 555 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 556 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 557 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ |
| 558 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 559 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ |
| 560 | "consoledev=ttyS0\0" \ |
| 561 | "ramdiskaddr=2000000\0" \ |
| 562 | "ramdiskfile=uRamdisk\0" \ |
Scott Wood | b24a4f6 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 563 | "fdtaddr=1e00000\0" \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 564 | "fdtfile=sbc8548.dtb\0" |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 565 | |
| 566 | #define CONFIG_NFSBOOTCOMMAND \ |
| 567 | "setenv bootargs root=/dev/nfs rw " \ |
| 568 | "nfsroot=$serverip:$rootpath " \ |
| 569 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 570 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 571 | "tftp $loadaddr $bootfile;" \ |
| 572 | "tftp $fdtaddr $fdtfile;" \ |
| 573 | "bootm $loadaddr - $fdtaddr" |
| 574 | |
Joe Hamman | 9e3ed39 | 2007-12-13 06:45:14 -0600 | [diff] [blame] | 575 | #define CONFIG_RAMBOOTCOMMAND \ |
| 576 | "setenv bootargs root=/dev/ram rw " \ |
| 577 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 578 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 579 | "tftp $loadaddr $bootfile;" \ |
| 580 | "tftp $fdtaddr $fdtfile;" \ |
| 581 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 582 | |
| 583 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
| 584 | |
| 585 | #endif /* __CONFIG_H */ |