blob: 7337f5374ba2f257aede2d19e50c4bf36b8feaf0 [file] [log] [blame]
wdenkab255f22002-09-18 09:04:55 +00001/*
stroese8b1ccd82004-09-16 12:34:51 +00002 * (C) Copyright 2001-2004
wdenkab255f22002-09-18 09:04:55 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_AR405 1 /* ...on a AR405 board */
wdenkab255f22002-09-18 09:04:55 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkab255f22002-09-18 09:04:55 +000043
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkab255f22002-09-18 09:04:55 +000045
stroese8b1ccd82004-09-16 12:34:51 +000046#define CONFIG_BOARD_TYPES 1 /* support board types */
47
wdenkab255f22002-09-18 09:04:55 +000048#define CONFIG_BAUDRATE 9600
49#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50
51#if 1
52#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
53#else
54#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
55#endif
56
57#if 0
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_BOOTARGS "root=/dev/nfs " \
59 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
wdenkab255f22002-09-18 09:04:55 +000060 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
61#else
62#define CONFIG_BOOTARGS "root=/dev/hda1 " \
63 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
64
65#endif
66
stroese8b1ccd82004-09-16 12:34:51 +000067#define CONFIG_PREBOOT /* enable preboot variable */
68
wdenkab255f22002-09-18 09:04:55 +000069#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkab255f22002-09-18 09:04:55 +000071
Ben Warren96e21f82008-10-27 23:50:15 -070072#define CONFIG_PPC4xx_EMAC
wdenkab255f22002-09-18 09:04:55 +000073#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000074#define CONFIG_PHY_ADDR 0 /* PHY address */
stroese8b1ccd82004-09-16 12:34:51 +000075#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
wdenkab255f22002-09-18 09:04:55 +000076
wdenkab255f22002-09-18 09:04:55 +000077
Jon Loeliger498ff9a2007-07-05 19:13:52 -050078/*
Jon Loeliger11799432007-07-10 09:02:57 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050088 * Command line configuration.
89 */
90#include <config_cmd_default.h>
91
92#define CONFIG_CMD_DHCP
93#define CONFIG_CMD_PCI
94#define CONFIG_CMD_IRQ
95#define CONFIG_CMD_ELF
96#define CONFIG_CMD_MII
Matthias Fuchs4710cee2010-02-01 13:54:09 +010097#undef CONFIG_CMD_NFS
Jon Loeliger498ff9a2007-07-05 19:13:52 -050098#define CONFIG_CMD_PING
99#define CONFIG_CMD_BSP
100
wdenkab255f22002-09-18 09:04:55 +0000101
102#undef CONFIG_WATCHDOG /* watchdog disabled */
103
wdenkc837dcb2004-01-20 23:12:12 +0000104#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkab255f22002-09-18 09:04:55 +0000105
106/*
107 * Miscellaneous configurable options
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_LONGHELP /* undef to save memory */
110#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500111#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +0000115#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkab255f22002-09-18 09:04:55 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese8b1ccd82004-09-16 12:34:51 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkab255f22002-09-18 09:04:55 +0000123
stroese8b1ccd82004-09-16 12:34:51 +0000124#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
stroesea20b27a2004-12-16 18:05:42 +0000125#define CONFIG_LOOPW 1 /* enable loopw command */
126#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
stroese8b1ccd82004-09-16 12:34:51 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkab255f22002-09-18 09:04:55 +0000130
Stefan Roese550650d2010-09-20 16:05:31 +0200131#define CONFIG_CONS_INDEX 1 /* Use UART0 */
132#define CONFIG_SYS_NS16550
133#define CONFIG_SYS_NS16550_SERIAL
134#define CONFIG_SYS_NS16550_REG_SIZE 1
135#define CONFIG_SYS_NS16550_CLK get_serial_clock()
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
wdenkab255f22002-09-18 09:04:55 +0000138
139/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000141 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
142 57600, 115200, 230400, 460800, 921600 }
wdenkab255f22002-09-18 09:04:55 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
145#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkab255f22002-09-18 09:04:55 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkab255f22002-09-18 09:04:55 +0000148
149#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
150
151/*-----------------------------------------------------------------------
152 * PCI stuff
153 *-----------------------------------------------------------------------
154 */
wdenkc837dcb2004-01-20 23:12:12 +0000155#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
156#define PCI_HOST_FORCE 1 /* configure as pci host */
157#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkab255f22002-09-18 09:04:55 +0000158
wdenkc837dcb2004-01-20 23:12:12 +0000159#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000160#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc837dcb2004-01-20 23:12:12 +0000161#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
162#define CONFIG_PCI_PNP /* do pci plug-and-play */
163 /* resource configuration */
wdenkab255f22002-09-18 09:04:55 +0000164
wdenkc837dcb2004-01-20 23:12:12 +0000165#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroesead10dd92003-02-14 11:21:23 +0000166
stroesea20b27a2004-12-16 18:05:42 +0000167#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
168
wdenkc837dcb2004-01-20 23:12:12 +0000169#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
stroesead10dd92003-02-14 11:21:23 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
172#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
173#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
174#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
175#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
176#define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */
177#define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
178#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkab255f22002-09-18 09:04:55 +0000179
180/*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkab255f22002-09-18 09:04:55 +0000184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchsf3dc7f12010-07-26 17:17:51 +0200186#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200187#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
188#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkab255f22002-09-18 09:04:55 +0000190
191/*
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkab255f22002-09-18 09:04:55 +0000197/*-----------------------------------------------------------------------
198 * FLASH organization
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
201#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkab255f22002-09-18 09:04:55 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkab255f22002-09-18 09:04:55 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
207#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
208#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkab255f22002-09-18 09:04:55 +0000209/*
210 * The following defines are added for buggy IOP480 byte interface.
211 * All other boards should use the standard values (CPCI405 etc.)
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
214#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
215#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkab255f22002-09-18 09:04:55 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkab255f22002-09-18 09:04:55 +0000218
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200219#define CONFIG_ENV_IS_IN_FLASH 1
Matthias Fuchsf3dc7f12010-07-26 17:17:51 +0200220#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
222#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
stroesea20b27a2004-12-16 18:05:42 +0000223
Matthias Fuchsf3dc7f12010-07-26 17:17:51 +0200224#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200225#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenkab255f22002-09-18 09:04:55 +0000226
wdenkab255f22002-09-18 09:04:55 +0000227/*
228 * Init Memory Controller:
229 *
230 * BR0/1 and OR0/1 (FLASH)
231 */
232
stroese8b1ccd82004-09-16 12:34:51 +0000233#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
wdenkab255f22002-09-18 09:04:55 +0000234
235/*-----------------------------------------------------------------------
236 * External Bus Controller (EBC) Setup
237 */
238
wdenkc837dcb2004-01-20 23:12:12 +0000239/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_EBC_PB0AP 0x92015480
241#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkab255f22002-09-18 09:04:55 +0000242
wdenkc837dcb2004-01-20 23:12:12 +0000243/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
245#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000246
wdenkc837dcb2004-01-20 23:12:12 +0000247/* Memory Bank 2 (Expension Bus) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
249#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000250
wdenkc837dcb2004-01-20 23:12:12 +0000251/* Memory Bank 3 (16552) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
253#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000254
wdenkc837dcb2004-01-20 23:12:12 +0000255/* Memory Bank 4 (FPGA regs) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
257#define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
wdenkab255f22002-09-18 09:04:55 +0000258
wdenkc837dcb2004-01-20 23:12:12 +0000259/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_EBC_PB5AP 0x92015480
261#define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkab255f22002-09-18 09:04:55 +0000262
263/*-----------------------------------------------------------------------
stroesec5d22902003-07-11 08:13:25 +0000264 * Definitions for initial stack pointer and data area (in data cache)
wdenkab255f22002-09-18 09:04:55 +0000265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkab255f22002-09-18 09:04:55 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200269#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200270#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkab255f22002-09-18 09:04:55 +0000272
wdenkab255f22002-09-18 09:04:55 +0000273#endif /* __CONFIG_H */