blob: 913cd975916253c8b1e304cbadb489f92c7af511 [file] [log] [blame]
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +01001/*
2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
3 *
4 * Developed for DENX Software Engineering GmbH
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010027#include <post.h>
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#if CONFIG_POST & CONFIG_SYS_POST_DSP
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010030#include <asm/io.h>
31
32/* This test verifies DSP status bits in FPGA */
33
34DECLARE_GLOBAL_DATA_PTR;
35
Sascha Lauef14ae412010-08-19 09:38:56 +020036#define DSP_STATUS_REG 0xC4000008
37#define FPGA_STATUS_REG 0xC400000C
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010038
39int dsp_post_test(int flags)
40{
Sascha Lauef14ae412010-08-19 09:38:56 +020041 uint old_value;
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010042 uint read_value;
43 int ret;
44
Sascha Lauef14ae412010-08-19 09:38:56 +020045 /* momorize fpga status */
46 old_value = in_be32((void *)FPGA_STATUS_REG);
47 /* enable outputs */
48 out_be32((void *)FPGA_STATUS_REG, 0x30);
49
50 /* generate sync signal */
51 out_be32((void *)DSP_STATUS_REG, 0x300);
52 udelay(5);
53 out_be32((void *)DSP_STATUS_REG, 0);
54 udelay(500);
55
56 /* read status */
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010057 ret = 0;
58 read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
Sascha Lauef14ae412010-08-19 09:38:56 +020059 if (read_value != 0x03) {
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010060 post_log("\nDSP status read %08X\n", read_value);
61 ret = 1;
62 }
63
Sascha Lauef14ae412010-08-19 09:38:56 +020064 /* restore fpga status */
65 out_be32((void *)FPGA_STATUS_REG, old_value);
66
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010067 return ret;
68}
69
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */