blob: 290647148de85c4abd467e903cec674d3944b8b2 [file] [log] [blame]
Masahiro Yamada7bdd1552016-03-18 16:41:48 +09001/*
Masahiro Yamada52159d22016-10-07 16:43:00 +09002 * Device Tree Source for UniPhier LD20 SoC
Masahiro Yamada7bdd1552016-03-18 16:41:48 +09003 *
Masahiro Yamada52159d22016-10-07 16:43:00 +09004 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada7bdd1552016-03-18 16:41:48 +09006 *
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +09007 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
Masahiro Yamada7bdd1552016-03-18 16:41:48 +090044 */
45
Masahiro Yamadacd622142016-12-05 18:31:39 +090046/memreserve/ 0x80000000 0x00080000;
Masahiro Yamadac4adc502016-06-29 19:38:56 +090047
Masahiro Yamada7bdd1552016-03-18 16:41:48 +090048/ {
Masahiro Yamada52159d22016-10-07 16:43:00 +090049 compatible = "socionext,uniphier-ld20";
Masahiro Yamada7bdd1552016-03-18 16:41:48 +090050 #address-cells = <2>;
51 #size-cells = <2>;
52 interrupt-parent = <&gic>;
53
54 cpus {
55 #address-cells = <2>;
56 #size-cells = <0>;
57
58 cpu-map {
59 cluster0 {
60 core0 {
61 cpu = <&cpu0>;
62 };
63 core1 {
64 cpu = <&cpu1>;
65 };
66 };
67
68 cluster1 {
69 core0 {
70 cpu = <&cpu2>;
71 };
72 core1 {
73 cpu = <&cpu3>;
74 };
75 };
76 };
77
78 cpu0: cpu@0 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a72", "arm,armv8";
81 reg = <0 0x000>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090082 clocks = <&sys_clk 32>;
83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +090085 };
86
87 cpu1: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a72", "arm,armv8";
90 reg = <0 0x001>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090091 clocks = <&sys_clk 32>;
92 enable-method = "psci";
93 operating-points-v2 = <&cluster0_opp>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +090094 };
95
96 cpu2: cpu@100 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a53", "arm,armv8";
99 reg = <0 0x100>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900100 clocks = <&sys_clk 33>;
101 enable-method = "psci";
102 operating-points-v2 = <&cluster1_opp>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900103 };
104
105 cpu3: cpu@101 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53", "arm,armv8";
108 reg = <0 0x101>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900109 clocks = <&sys_clk 33>;
110 enable-method = "psci";
111 operating-points-v2 = <&cluster1_opp>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900112 };
113 };
114
Masahiro Yamadacd622142016-12-05 18:31:39 +0900115 cluster0_opp: opp_table0 {
116 compatible = "operating-points-v2";
117 opp-shared;
118
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900119 opp-250000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900120 opp-hz = /bits/ 64 <250000000>;
121 clock-latency-ns = <300>;
122 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900123 opp-275000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900124 opp-hz = /bits/ 64 <275000000>;
125 clock-latency-ns = <300>;
126 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900127 opp-500000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900128 opp-hz = /bits/ 64 <500000000>;
129 clock-latency-ns = <300>;
130 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900131 opp-550000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900132 opp-hz = /bits/ 64 <550000000>;
133 clock-latency-ns = <300>;
134 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900135 opp-666667000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900136 opp-hz = /bits/ 64 <666667000>;
137 clock-latency-ns = <300>;
138 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900139 opp-733334000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900140 opp-hz = /bits/ 64 <733334000>;
141 clock-latency-ns = <300>;
142 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900143 opp-1000000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900144 opp-hz = /bits/ 64 <1000000000>;
145 clock-latency-ns = <300>;
146 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900147 opp-1100000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900148 opp-hz = /bits/ 64 <1100000000>;
149 clock-latency-ns = <300>;
150 };
151 };
152
153 cluster1_opp: opp_table1 {
154 compatible = "operating-points-v2";
155 opp-shared;
156
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900157 opp-250000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900158 opp-hz = /bits/ 64 <250000000>;
159 clock-latency-ns = <300>;
160 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900161 opp-275000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900162 opp-hz = /bits/ 64 <275000000>;
163 clock-latency-ns = <300>;
164 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900165 opp-500000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900166 opp-hz = /bits/ 64 <500000000>;
167 clock-latency-ns = <300>;
168 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900169 opp-550000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900170 opp-hz = /bits/ 64 <550000000>;
171 clock-latency-ns = <300>;
172 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900173 opp-666667000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900174 opp-hz = /bits/ 64 <666667000>;
175 clock-latency-ns = <300>;
176 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900177 opp-733334000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900178 opp-hz = /bits/ 64 <733334000>;
179 clock-latency-ns = <300>;
180 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900181 opp-1000000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900182 opp-hz = /bits/ 64 <1000000000>;
183 clock-latency-ns = <300>;
184 };
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900185 opp-1100000000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900186 opp-hz = /bits/ 64 <1100000000>;
187 clock-latency-ns = <300>;
188 };
189 };
190
191 psci {
192 compatible = "arm,psci-1.0";
193 method = "smc";
194 };
195
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900196 clocks {
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900197 refclk: ref {
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <25000000>;
201 };
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900202 };
203
204 timer {
205 compatible = "arm,armv8-timer";
Masahiro Yamada35343a22016-09-22 07:42:23 +0900206 interrupts = <1 13 4>,
207 <1 14 4>,
208 <1 11 4>,
209 <1 10 4>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900210 };
211
Masahiro Yamada7ad79c12017-03-13 00:16:40 +0900212 soc@0 {
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900213 compatible = "simple-bus";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges = <0 0 0 0xffffffff>;
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900217 u-boot,dm-pre-reloc;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900218
219 serial0: serial@54006800 {
220 compatible = "socionext,uniphier-uart";
221 status = "disabled";
222 reg = <0x54006800 0x40>;
223 interrupts = <0 33 4>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_uart0>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900226 clocks = <&peri_clk 0>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900227 clock-frequency = <58820000>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900228 };
229
230 serial1: serial@54006900 {
231 compatible = "socionext,uniphier-uart";
232 status = "disabled";
233 reg = <0x54006900 0x40>;
234 interrupts = <0 35 4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900237 clocks = <&peri_clk 1>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900238 clock-frequency = <58820000>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900239 };
240
241 serial2: serial@54006a00 {
242 compatible = "socionext,uniphier-uart";
243 status = "disabled";
244 reg = <0x54006a00 0x40>;
245 interrupts = <0 37 4>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900248 clocks = <&peri_clk 2>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900249 clock-frequency = <58820000>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900250 };
251
252 serial3: serial@54006b00 {
253 compatible = "socionext,uniphier-uart";
254 status = "disabled";
255 reg = <0x54006b00 0x40>;
256 interrupts = <0 177 4>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_uart3>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900259 clocks = <&peri_clk 3>;
Masahiro Yamadaf1494982016-03-28 21:39:17 +0900260 clock-frequency = <58820000>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900261 };
262
263 i2c0: i2c@58780000 {
264 compatible = "socionext,uniphier-fi2c";
265 status = "disabled";
266 reg = <0x58780000 0x80>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <0 41 4>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_i2c0>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900272 clocks = <&peri_clk 4>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900273 clock-frequency = <100000>;
274 };
275
276 i2c1: i2c@58781000 {
277 compatible = "socionext,uniphier-fi2c";
278 status = "disabled";
279 reg = <0x58781000 0x80>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <0 42 4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c1>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900285 clocks = <&peri_clk 5>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900286 clock-frequency = <100000>;
287 };
288
289 i2c2: i2c@58782000 {
290 compatible = "socionext,uniphier-fi2c";
291 reg = <0x58782000 0x80>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 interrupts = <0 43 4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900295 clocks = <&peri_clk 6>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900296 clock-frequency = <400000>;
297 };
298
299 i2c3: i2c@58783000 {
300 compatible = "socionext,uniphier-fi2c";
301 status = "disabled";
302 reg = <0x58783000 0x80>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 interrupts = <0 44 4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c3>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900308 clocks = <&peri_clk 7>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900309 clock-frequency = <100000>;
310 };
311
312 i2c4: i2c@58784000 {
313 compatible = "socionext,uniphier-fi2c";
314 status = "disabled";
315 reg = <0x58784000 0x80>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 interrupts = <0 45 4>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_i2c4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900321 clocks = <&peri_clk 8>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900322 clock-frequency = <100000>;
323 };
324
325 i2c5: i2c@58785000 {
326 compatible = "socionext,uniphier-fi2c";
327 reg = <0x58785000 0x80>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 interrupts = <0 25 4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900331 clocks = <&peri_clk 9>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900332 clock-frequency = <400000>;
333 };
334
335 system_bus: system-bus@58c00000 {
336 compatible = "socionext,uniphier-system-bus";
337 status = "disabled";
338 reg = <0x58c00000 0x400>;
339 #address-cells = <2>;
340 #size-cells = <1>;
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_system_bus>;
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900343 };
344
345 smpctrl@59800000 {
346 compatible = "socionext,uniphier-smpctrl";
347 reg = <0x59801000 0x400>;
348 };
349
Masahiro Yamadacd622142016-12-05 18:31:39 +0900350 sdctrl@59810000 {
351 compatible = "socionext,uniphier-ld20-sdctrl",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900352 "simple-mfd", "syscon";
Masahiro Yamada3d970872016-04-21 14:43:20 +0900353 reg = <0x59810000 0x800>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900354
Masahiro Yamadacd622142016-12-05 18:31:39 +0900355 sd_clk: clock {
356 compatible = "socionext,uniphier-ld20-sd-clock";
Masahiro Yamada35343a22016-09-22 07:42:23 +0900357 #clock-cells = <1>;
358 };
359
Masahiro Yamadacd622142016-12-05 18:31:39 +0900360 sd_rst: reset {
361 compatible = "socionext,uniphier-ld20-sd-reset";
Masahiro Yamada35343a22016-09-22 07:42:23 +0900362 #reset-cells = <1>;
363 };
364 };
365
366 perictrl@59820000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900367 compatible = "socionext,uniphier-ld20-perictrl",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900368 "simple-mfd", "syscon";
369 reg = <0x59820000 0x200>;
370
371 peri_clk: clock {
372 compatible = "socionext,uniphier-ld20-peri-clock";
373 #clock-cells = <1>;
374 };
375
376 peri_rst: reset {
377 compatible = "socionext,uniphier-ld20-peri-reset";
378 #reset-cells = <1>;
379 };
Masahiro Yamada3d970872016-04-21 14:43:20 +0900380 };
381
Masahiro Yamadacd622142016-12-05 18:31:39 +0900382 emmc: sdhc@5a000000 {
Masahiro Yamada7a6139c2017-01-04 20:08:37 +0900383 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900384 reg = <0x5a000000 0x400>;
385 interrupts = <0 78 4>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_emmc_1v8>;
388 clocks = <&sys_clk 4>;
389 bus-width = <8>;
390 mmc-ddr-1_8v;
391 mmc-hs200-1_8v;
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900392 cdns,phy-input-delay-legacy = <4>;
393 cdns,phy-input-delay-mmc-highspeed = <2>;
394 cdns,phy-input-delay-mmc-ddr = <3>;
395 cdns,phy-dll-delay-sdclk = <21>;
396 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900397 };
398
Masahiro Yamada3d970872016-04-21 14:43:20 +0900399 sd: sdhc@5a400000 {
400 compatible = "socionext,uniphier-sdhc";
401 status = "disabled";
402 reg = <0x5a400000 0x800>;
403 interrupts = <0 76 4>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_sd>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900406 clocks = <&sd_clk 0>;
Masahiro Yamada52159d22016-10-07 16:43:00 +0900407 reset-names = "host";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900408 resets = <&sd_rst 0>;
Masahiro Yamada3d970872016-04-21 14:43:20 +0900409 bus-width = <4>;
Masahiro Yamadacd622142016-12-05 18:31:39 +0900410 cap-sd-highspeed;
Masahiro Yamada3d970872016-04-21 14:43:20 +0900411 };
412
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900413 soc-glue@5f800000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900414 compatible = "socionext,uniphier-ld20-soc-glue",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900415 "simple-mfd", "syscon";
Masahiro Yamadac4adc502016-06-29 19:38:56 +0900416 reg = <0x5f800000 0x2000>;
417 u-boot,dm-pre-reloc;
418
419 pinctrl: pinctrl {
420 compatible = "socionext,uniphier-ld20-pinctrl";
421 u-boot,dm-pre-reloc;
422 };
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900423 };
424
Masahiro Yamada1013aef2016-06-29 19:39:02 +0900425 aidet@5fc20000 {
426 compatible = "simple-mfd", "syscon";
427 reg = <0x5fc20000 0x200>;
428 };
429
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900430 gic: interrupt-controller@5fe00000 {
431 compatible = "arm,gic-v3";
432 reg = <0x5fe00000 0x10000>, /* GICD */
433 <0x5fe80000 0x80000>; /* GICR */
434 interrupt-controller;
435 #interrupt-cells = <3>;
436 interrupts = <1 9 4>;
437 };
Masahiro Yamada35343a22016-09-22 07:42:23 +0900438
439 sysctrl@61840000 {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900440 compatible = "socionext,uniphier-ld20-sysctrl",
Masahiro Yamada35343a22016-09-22 07:42:23 +0900441 "simple-mfd", "syscon";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900442 reg = <0x61840000 0x10000>;
Masahiro Yamada35343a22016-09-22 07:42:23 +0900443
444 sys_clk: clock {
445 compatible = "socionext,uniphier-ld20-clock";
446 #clock-cells = <1>;
447 };
448
449 sys_rst: reset {
450 compatible = "socionext,uniphier-ld20-reset";
451 #reset-cells = <1>;
452 };
453 };
Masahiro Yamadacd622142016-12-05 18:31:39 +0900454
455 usb: usb@65b00000 {
456 compatible = "socionext,uniphier-ld20-dwc3";
457 reg = <0x65b00000 0x1000>;
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
463 <&pinctrl_usb2>, <&pinctrl_usb3>;
464 dwc3@65a00000 {
465 compatible = "snps,dwc3";
466 reg = <0x65a00000 0x10000>;
467 interrupts = <0 134 4>;
468 tx-fifo-resize;
469 };
470 };
471
472 nand: nand@68000000 {
Masahiro Yamada4e7f8de2017-04-20 16:54:44 +0900473 compatible = "socionext,uniphier-denali-nand-v5b";
Masahiro Yamadacd622142016-12-05 18:31:39 +0900474 status = "disabled";
475 reg-names = "nand_data", "denali_reg";
476 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
477 interrupts = <0 65 4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_nand>;
480 clocks = <&sys_clk 2>;
481 nand-ecc-strength = <8>;
482 };
Masahiro Yamada7bdd1552016-03-18 16:41:48 +0900483 };
484};
485
486/include/ "uniphier-pinctrl.dtsi"