Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the sh7753evb board |
| 4 | * |
| 5 | * Copyright (C) 2012 Renesas Solutions Corp. |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __SH7753EVB_H |
| 9 | #define __SH7753EVB_H |
| 10 | |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 11 | #define CONFIG_CPU_SH7753 1 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 12 | |
Vladimir Zapolskiy | 18a40e8 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 13 | #define CONFIG_DISPLAY_BOARDINFO |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 14 | |
| 15 | /* MEMORY */ |
| 16 | #define SH7753EVB_SDRAM_BASE (0x40000000) |
| 17 | #define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) |
| 18 | |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 19 | #define CONFIG_SYS_PBSIZE 256 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 20 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
| 21 | |
| 22 | /* SCIF */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 23 | #define CONFIG_CONS_SCIF2 1 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 24 | |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 25 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
| 26 | |
| 27 | #define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) |
| 28 | #define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) |
| 29 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 30 | 128 * 1024 * 1024) |
| 31 | |
| 32 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 |
| 33 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 34 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 35 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 36 | |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 37 | /* Ether */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 38 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 39 | #define CONFIG_SH_ETHER_PHY_ADDR 18 |
| 40 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 |
| 41 | #define CONFIG_SH_ETHER_USE_GETHER 1 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 42 | #define CONFIG_BITBANGMII_MULTI |
| 43 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 44 | |
| 45 | #define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 |
| 46 | #define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) |
| 47 | #define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI |
| 48 | #define SH7753EVB_ETHERNET_MAC_SIZE 17 |
| 49 | #define SH7753EVB_ETHERNET_NUM_CH 2 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 50 | |
| 51 | /* SPI */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 52 | #define CONFIG_SH_SPI_BASE 0xfe002000 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 53 | |
| 54 | /* MMCIF */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 55 | #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 |
| 56 | #define CONFIG_SH_MMCIF_CLK 48000000 |
| 57 | |
| 58 | /* ENV setting */ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 59 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 60 | "netboot=bootp; bootm\0" |
| 61 | |
| 62 | /* Board Clock */ |
| 63 | #define CONFIG_SYS_CLK_FREQ 48000000 |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 64 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Yoshihiro Shimoda | 320cf35 | 2013-12-18 16:03:44 +0900 | [diff] [blame] | 65 | #endif /* __SH7753EVB_H */ |