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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_PCI405 1 /* ...on a PCI405 board */
wdenkc6097192002-11-03 00:24:07 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000041#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
42
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000044
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_BOARD_TYPES 1 /* support board types */
wdenkc6097192002-11-03 00:24:07 +000046
stroesea20b27a2004-12-16 18:05:42 +000047#define CONFIG_BAUDRATE 115200
48#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
wdenkc6097192002-11-03 00:24:07 +000049
50#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000051#define CONFIG_EXTRA_ENV_SETTINGS \
52 "mem_linux=14336k\0" \
53 "optargs=panic=0\0" \
54 "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
55 "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
56 ""
57#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci"
58
59#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000060
61#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
62#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
63
64#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000065#define CONFIG_PHY_ADDR 0 /* PHY address */
wdenkc6097192002-11-03 00:24:07 +000066
67#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
68
69#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
70 CFG_CMD_PCI | \
71 CFG_CMD_IRQ | \
72 CFG_CMD_ELF | \
73 CFG_CMD_DATE | \
74 CFG_CMD_I2C | \
stroesed69b1002003-03-25 14:41:35 +000075 CFG_CMD_BSP | \
wdenkc837dcb2004-01-20 23:12:12 +000076 CFG_CMD_EEPROM )
wdenkc6097192002-11-03 00:24:07 +000077
78/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
79#include <cmd_confdefs.h>
80
wdenkc837dcb2004-01-20 23:12:12 +000081#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000082
wdenkc837dcb2004-01-20 23:12:12 +000083#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000084
wdenkc837dcb2004-01-20 23:12:12 +000085#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
stroesed69b1002003-03-25 14:41:35 +000086
wdenkc6097192002-11-03 00:24:07 +000087/*
88 * Miscellaneous configurable options
89 */
90#define CFG_LONGHELP /* undef to save memory */
91#define CFG_PROMPT "=> " /* Monitor Command Prompt */
92
wdenkc837dcb2004-01-20 23:12:12 +000093#define CFG_HUSH_PARSER /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +000094#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +000095#define CFG_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +000096#endif
97
98#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000099#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000100#else
wdenkc837dcb2004-01-20 23:12:12 +0000101#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000102#endif
103#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
104#define CFG_MAXARGS 16 /* max number of command args */
105#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
106
wdenkc837dcb2004-01-20 23:12:12 +0000107#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000108
wdenkc837dcb2004-01-20 23:12:12 +0000109#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000110
111#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
112#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
113
wdenkc837dcb2004-01-20 23:12:12 +0000114#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
115#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
116#define CFG_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000117
118/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000119#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000120 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
121 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000122
123#define CFG_LOAD_ADDR 0x100000 /* default load address */
124#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
125
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000127
stroesed69b1002003-03-25 14:41:35 +0000128#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
wdenkc6097192002-11-03 00:24:07 +0000129
wdenkc837dcb2004-01-20 23:12:12 +0000130#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese2853d292003-09-12 08:53:54 +0000131
wdenkc6097192002-11-03 00:24:07 +0000132/*-----------------------------------------------------------------------
133 * PCI stuff
134 *-----------------------------------------------------------------------
135 */
wdenkc837dcb2004-01-20 23:12:12 +0000136#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
137#define PCI_HOST_FORCE 1 /* configure as pci host */
138#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000139
wdenkc837dcb2004-01-20 23:12:12 +0000140#define CONFIG_PCI /* include pci support */
141#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
142#undef CONFIG_PCI_PNP /* no pci plug-and-play */
143 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000144
wdenkc837dcb2004-01-20 23:12:12 +0000145#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000146
wdenkc837dcb2004-01-20 23:12:12 +0000147#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
148#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
149#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
150#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
151#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
152#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000153
154#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
156#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
157#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000158#else
wdenkc837dcb2004-01-20 23:12:12 +0000159#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
160#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
161#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000162#endif
163
164/*-----------------------------------------------------------------------
165 * Start addresses for the final memory configuration
166 * (Set up by the startup code)
167 * Please note that CFG_SDRAM_BASE _must_ start at 0
168 */
169#define CFG_SDRAM_BASE 0x00000000
170#define CFG_FLASH_BASE 0xFFFD0000
171#define CFG_MONITOR_BASE CFG_FLASH_BASE
172#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
173#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
174
175/*
176 * For booting Linux, the board info and command line data
177 * have to be in the first 8 MB of memory, since this is
178 * the maximum mapped by the Linux kernel during initialization.
179 */
180#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
181/*-----------------------------------------------------------------------
182 * FLASH organization
183 */
184#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
185#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
186
187#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
188#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
189
wdenkc837dcb2004-01-20 23:12:12 +0000190#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
191#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
192#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000193/*
194 * The following defines are added for buggy IOP480 byte interface.
195 * All other boards should use the standard values (CPCI405 etc.)
196 */
wdenkc837dcb2004-01-20 23:12:12 +0000197#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
198#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
199#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000200
wdenkc837dcb2004-01-20 23:12:12 +0000201#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000202
203#if 0 /* Use NVRAM for environment variables */
204/*-----------------------------------------------------------------------
205 * NVRAM organization
206 */
207#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
208#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
209#define CFG_ENV_ADDR \
210 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
211
212#else /* Use EEPROM for environment variables */
213
wdenkc837dcb2004-01-20 23:12:12 +0000214#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
215#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
216#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000217 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000218#endif
219
220#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
221#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
222
223/*-----------------------------------------------------------------------
224 * I2C EEPROM (CAT24WC16) for environment
225 */
226#define CONFIG_HARD_I2C /* I2c with hardware support */
227#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
228#define CFG_I2C_SLAVE 0x7F
229
230#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000231#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
232/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000233#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
234#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
235 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000236 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000237#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
238#define CFG_EEPROM_PAGE_WRITE_ENABLE
239
240/*-----------------------------------------------------------------------
241 * Cache Configuration
242 */
243#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
244#define CFG_CACHELINE_SIZE 32 /* ... */
245#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
246#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
247#endif
248
249/*
250 * Init Memory Controller:
251 *
252 * BR0/1 and OR0/1 (FLASH)
253 */
254
255#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
256
257/*-----------------------------------------------------------------------
258 * External Bus Controller (EBC) Setup
259 */
260
wdenkc837dcb2004-01-20 23:12:12 +0000261/* Memory Bank 0 (Flash Bank 0) initialization */
262#define CFG_EBC_PB0AP 0x92015480
263#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000264
wdenkc837dcb2004-01-20 23:12:12 +0000265/* Memory Bank 1 (NVRAM/RTC) initialization */
266#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
267#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000268
wdenkc837dcb2004-01-20 23:12:12 +0000269/* Memory Bank 2 (CAN0, 1) initialization */
270#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
271/*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000273
wdenkc837dcb2004-01-20 23:12:12 +0000274/* Memory Bank 3 (FPGA internal) initialization */
275#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
276#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
277#define CFG_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000278
279/*-----------------------------------------------------------------------
280 * FPGA stuff
281 */
282/* FPGA internal regs */
wdenkc837dcb2004-01-20 23:12:12 +0000283#define CFG_FPGA_MODE 0x00
284#define CFG_FPGA_STATUS 0x02
285#define CFG_FPGA_TS 0x04
286#define CFG_FPGA_TS_LOW 0x06
287#define CFG_FPGA_TS_CAP0 0x10
288#define CFG_FPGA_TS_CAP0_LOW 0x12
289#define CFG_FPGA_TS_CAP1 0x14
290#define CFG_FPGA_TS_CAP1_LOW 0x16
291#define CFG_FPGA_TS_CAP2 0x18
292#define CFG_FPGA_TS_CAP2_LOW 0x1a
293#define CFG_FPGA_TS_CAP3 0x1c
294#define CFG_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000295
296/* FPGA Mode Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000297#define CFG_FPGA_MODE_CF_RESET 0x0001
wdenkc6097192002-11-03 00:24:07 +0000298#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
299#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
wdenkc837dcb2004-01-20 23:12:12 +0000300#define CFG_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000301
302/* FPGA Status Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000303#define CFG_FPGA_STATUS_DIP0 0x0001
304#define CFG_FPGA_STATUS_DIP1 0x0002
305#define CFG_FPGA_STATUS_DIP2 0x0004
306#define CFG_FPGA_STATUS_FLASH 0x0008
307#define CFG_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000308
wdenkc837dcb2004-01-20 23:12:12 +0000309#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
310#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000311
312/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000313#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
314#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
315#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
316#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
317#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000318/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
319#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
320#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000321
322/*-----------------------------------------------------------------------
323 * Definitions for initial stack pointer and data area (in data cache)
324 */
stroesea20b27a2004-12-16 18:05:42 +0000325#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000326#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
327#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
328#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenkc6097192002-11-03 00:24:07 +0000329#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
330#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000331#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000332#else
333/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
334#define CFG_TEMP_STACK_OCM 1
335/* On Chip Memory location */
336#define CFG_OCM_DATA_ADDR 0xF8000000
337#define CFG_OCM_DATA_SIZE 0x1000
338#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
339#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
340
341#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
342#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
343#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
344#endif
wdenkc6097192002-11-03 00:24:07 +0000345
wdenkc6097192002-11-03 00:24:07 +0000346/*
347 * Internal Definitions
348 *
349 * Boot Flags
350 */
351#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
352#define BOOTFLAG_WARM 0x02 /* Software reboot */
353
354#endif /* __CONFIG_H */