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TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -050030#include <asm/immap.h>
31#include <asm/rtc.h>
32
TsiChung Liewf3962d32008-10-21 13:47:54 +000033#if defined(CONFIG_CMD_NET)
34#include <config.h>
35#include <net.h>
36#include <asm/fec.h>
37#endif
38
TsiChungLiew8ae158c2007-08-16 15:05:11 -050039/*
40 * Breath some life into the CPU...
41 *
42 * Set up the memory map,
43 * initialize a bunch of registers,
44 * initialize the UPM's
45 */
46void cpu_init_f(void)
47{
48 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
49 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
50 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
51
52 scm1->mpr = 0x77777777;
53 scm1->pacra = 0;
54 scm1->pacrb = 0;
55 scm1->pacrc = 0;
56 scm1->pacrd = 0;
57 scm1->pacre = 0;
58 scm1->pacrf = 0;
59 scm1->pacrg = 0;
60
61 /* FlexBus */
62 gpio->par_be =
63 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
64 GPIO_PAR_BE_BE0_BE0;
65 gpio->par_fbctl =
66 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
67 GPIO_PAR_FBCTL_TS_TS;
68
TsiChung Liew9f751552008-07-23 20:38:53 -050069#if !defined(CONFIG_CF_SBF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
71 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
72 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
73 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -050074#endif
TsiChung Liew9f751552008-07-23 20:38:53 -050075#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -050076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
TsiChungLiew8ae158c2007-08-16 15:05:11 -050078 /* Latch chipselect */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
80 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
81 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -050082#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
85 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
86 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
87 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -050088#endif
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
91 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
92 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
93 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -050094#endif
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
97 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
98 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
99 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500100#endif
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
103 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
104 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
105 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500106#endif
107
108#ifdef CONFIG_FSL_I2C
109 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
110#endif
111
112 icache_enable();
113}
114
115/*
116 * initialize higher level parts of CPU like timers
117 */
118int cpu_init_r(void)
119{
TsiChung Liewbc3ccb12008-07-09 15:47:27 -0500120#ifdef CONFIG_MCFRTC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500122 volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
125 rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500126#endif
127
128 return (0);
129}
130
131void uart_port_conf(void)
132{
133 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
134
135 /* Setup Ports: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 switch (CONFIG_SYS_UART_PORT) {
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500137 case 0:
138 gpio->par_uart =
139 (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
140 break;
141 case 1:
142 gpio->par_uart =
143 (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
144 break;
145 }
146}
TsiChung Liewf3962d32008-10-21 13:47:54 +0000147
148#if defined(CONFIG_CMD_NET)
149int fecpin_setclear(struct eth_device *dev, int setclear)
150{
151 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
152 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
153
154 if (setclear) {
155 gpio->par_feci2c |=
156 (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
157
158 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
159 gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
160 else
161 gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
162 } else {
163 gpio->par_feci2c &=
164 ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
165
166 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
167 gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
168 else
169 gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
170 }
171 return 0;
172}
173#endif
TsiChung Liewee0a8462009-06-30 14:18:29 +0000174
175#ifdef CONFIG_CF_DSPI
176void cfspi_port_conf(void)
177{
178 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
179
180 gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
181 GPIO_PAR_DSPI_SCK_SCK;
182}
183
184int cfspi_claim_bus(uint bus, uint cs)
185{
186 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
187 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
188
189 if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
190 return -1;
191
192 /* Clear FIFO and resume transfer */
193 dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
194
195 switch (cs) {
196 case 0:
197 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
198 gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
199 break;
200 case 1:
201 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
202 gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
203 break;
204 case 2:
205 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
206 gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
207 break;
208 case 5:
209 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
210 gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
211 break;
212 }
213
214 return 0;
215}
216
217void cfspi_release_bus(uint bus, uint cs)
218{
219 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
220 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
221
222 dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
223
224 switch (cs) {
225 case 0:
226 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
227 break;
228 case 1:
229 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
230 break;
231 case 2:
232 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
233 break;
234 case 5:
235 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
236 break;
237 }
238}
239#endif