Blame - include/configs/lager.h - platform/external/u-boot

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Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	1	/*
				2	* include/configs/lager.h
				3	* This file is lager board configuration.
				4	*
Nobuhiro Iwamatsu	5ca6dfe	2014-11-10 14:34:07 +0900	[diff] [blame]	5	* Copyright (C) 2013, 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	6	*
				7	* SPDX-License-Identifier: GPL-2.0
				8	*/
				9
				10	#ifndef __LAGER_H
				11	#define __LAGER_H
				12
				13	#undef DEBUG
Nobuhiro Iwamatsu	1cc95f6	2015-10-10 05:58:28 +0900	[diff] [blame]	14	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	15
Nobuhiro Iwamatsu	5ca6dfe	2014-11-10 14:34:07 +0900	[diff] [blame]	16	#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu	d80149b	2014-03-31 15:22:31 +0900	[diff] [blame]	17
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	18	/* STACK */
Nobuhiro Iwamatsu	fb6f600	2014-10-31 16:16:26 +0900	[diff] [blame]	19	#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
				20	#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
				21	#else
				22	#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
				23	#endif
				24	#define STACK_AREA_SIZE 0xC000
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	25	#define LOW_LEVEL_MERAM_STACK \
				26	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
				27
				28	/* MEMORY */
Nobuhiro Iwamatsu	5ca6dfe	2014-11-10 14:34:07 +0900	[diff] [blame]	29	#define RCAR_GEN2_SDRAM_BASE 0x40000000
				30	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
				31	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	32
				33	/* SCIF */
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	34
Nobuhiro Iwamatsu	5ca6dfe	2014-11-10 14:34:07 +0900	[diff] [blame]	35	/* SPI */
Nobuhiro Iwamatsu	0e05b21	2014-01-08 10:32:22 +0900	[diff] [blame]	36	#define CONFIG_SPI
Nobuhiro Iwamatsu	0e05b21	2014-01-08 10:32:22 +0900	[diff] [blame]	37
Nobuhiro Iwamatsu	23565c6	2013-10-20 20:28:24 +0900	[diff] [blame]	38	/* SH Ether */
Nobuhiro Iwamatsu	23565c6	2013-10-20 20:28:24 +0900	[diff] [blame]	39	#define CONFIG_SH_ETHER_USE_PORT 0
				40	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
				41	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
				42	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
				43	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
				44	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Nobuhiro Iwamatsu	23565c6	2013-10-20 20:28:24 +0900	[diff] [blame]	45	#define CONFIG_BITBANGMII
				46	#define CONFIG_BITBANGMII_MULTI
				47
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	48	/* I2C */
				49	#define CONFIG_SYS_I2C
				50	#define CONFIG_SYS_I2C_RCAR
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	51	#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	52	#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	53	#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	54	#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
				55	#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
				56
Nobuhiro Iwamatsu	b9986be	2013-10-10 09:13:41 +0900	[diff] [blame]	57	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
				58
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	59	/* Board Clock */
Nobuhiro Iwamatsu	b1f78a2	2014-03-31 14:03:07 +0900	[diff] [blame]	60	#define RMOBILE_XTAL_CLK 20000000u
				61	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
				62	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
				63	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	64	#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
				65	#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
Nobuhiro Iwamatsu	b9107ad	2013-09-30 10:08:40 +0900	[diff] [blame]	66	#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	67
				68	#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	69
Nobuhiro Iwamatsu	5c4bb96	2014-03-27 14:14:58 +0900	[diff] [blame]	70	/* USB */
Nobuhiro Iwamatsu	5c4bb96	2014-03-27 14:14:58 +0900	[diff] [blame]	71	#define CONFIG_USB_EHCI_RMOBILE
Nobuhiro Iwamatsu	5906fad	2014-07-28 15:29:31 +0900	[diff] [blame]	72	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Nobuhiro Iwamatsu	5c4bb96	2014-03-27 14:14:58 +0900	[diff] [blame]	73
Nobuhiro Iwamatsu	d7916b1	2014-12-03 15:30:30 +0900	[diff] [blame]	74	/* MMC */
Nobuhiro Iwamatsu	d7916b1	2014-12-03 15:30:30 +0900	[diff] [blame]	75	#define CONFIG_SH_MMCIF
				76	#define CONFIG_SH_MMCIF_ADDR 0xEE220000
				77	#define CONFIG_SH_MMCIF_CLK 97500000
				78
Nobuhiro Iwamatsu	8e2e588	2014-12-02 16:52:24 +0900	[diff] [blame]	79	/* Module stop status bits */
				80	/* INTC-RT */
				81	#define CONFIG_SMSTP0_ENA 0x00400000
				82	/* MSIF */
				83	#define CONFIG_SMSTP2_ENA 0x00002000
				84	/* INTC-SYS, IRQC */
				85	#define CONFIG_SMSTP4_ENA 0x00000180
				86	/* SCIF0 */
				87	#define CONFIG_SMSTP7_ENA 0x00200000
				88
Nobuhiro Iwamatsu	acdfecb	2014-11-21 10:19:32 +0900	[diff] [blame]	89	/* SDHI */
				90	#define CONFIG_SH_SDHI_FREQ 97500000
				91
Nobuhiro Iwamatsu	f4ec452	2013-11-21 17:06:46 +0900	[diff] [blame]	92	#endif /* __LAGER_H */