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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <ppc_asm.tmpl>
Haiying Wanga52d2f82011-02-11 01:25:30 -060031#include <linux/compiler.h>
wdenk42d1f032003-10-15 23:53:47 +000032#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080033#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000034
Wolfgang Denkd87080b2006-03-31 18:32:53 +020035DECLARE_GLOBAL_DATA_PTR;
36
wdenk42d1f032003-10-15 23:53:47 +000037/* --------------------------------------------------------------- */
38
wdenk42d1f032003-10-15 23:53:47 +000039void get_sys_info (sys_info_t * sysInfo)
40{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala39aaca12009-03-19 02:46:19 -050042#ifdef CONFIG_FSL_CORENET
43 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabifbb9ecf2011-08-05 16:15:24 -050044 unsigned int cpu;
Kumar Gala39aaca12009-03-19 02:46:19 -050045
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
61 const u8 core_cplx_PLL_div[16] = {
62 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
75 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080076 uint ratio[4];
Kumar Gala39aaca12009-03-19 02:46:19 -050077 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080078 uint mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050079
80 sysInfo->freqSystemBus = sysclk;
81 sysInfo->freqDDRBus = sysclk;
Kumar Gala39aaca12009-03-19 02:46:19 -050082
James Yang93cedc72010-01-12 15:50:18 -060083 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080084 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
85 if (mem_pll_rat > 2)
86 sysInfo->freqDDRBus *= mem_pll_rat;
87 else
88 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050089
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080090 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
91 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
92 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
93 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
94 for (i = 0; i < 4; i++) {
95 if (ratio[i] > 4)
96 freqCC_PLL[i] = sysclk * ratio[i];
97 else
98 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
99 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500100 rcw_tmp = in_be32(&gur->rcwsr[3]);
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500101 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
102 u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
Kumar Gala39aaca12009-03-19 02:46:19 -0500103 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
104
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500105 sysInfo->freqProcessor[cpu] =
Kumar Gala39aaca12009-03-19 02:46:19 -0500106 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
107 }
108
109#define PME_CLK_SEL 0x80000000
110#define FM1_CLK_SEL 0x40000000
111#define FM2_CLK_SEL 0x20000000
Kumar Galab5c87532011-02-16 02:03:29 -0600112#define HWA_ASYNC_DIV 0x04000000
113#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
114#define HWA_CC_PLL 1
115#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denkcd6881b2011-05-19 22:21:41 +0200116#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600117#else
118#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
119#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500120 rcw_tmp = in_be32(&gur->rcwsr[7]);
121
122#ifdef CONFIG_SYS_DPAA_PME
Kumar Galab5c87532011-02-16 02:03:29 -0600123 if (rcw_tmp & PME_CLK_SEL) {
124 if (rcw_tmp & HWA_ASYNC_DIV)
125 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
126 else
127 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
128 } else {
Kumar Gala693416f2010-01-25 11:01:51 -0600129 sysInfo->freqPME = sysInfo->freqSystemBus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600130 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500131#endif
132
133#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Galab5c87532011-02-16 02:03:29 -0600134 if (rcw_tmp & FM1_CLK_SEL) {
135 if (rcw_tmp & HWA_ASYNC_DIV)
136 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
137 else
138 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
139 } else {
Kumar Gala693416f2010-01-25 11:01:51 -0600140 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600141 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500142#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Galab5c87532011-02-16 02:03:29 -0600143 if (rcw_tmp & FM2_CLK_SEL) {
144 if (rcw_tmp & HWA_ASYNC_DIV)
145 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
146 else
147 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
148 } else {
Kumar Gala693416f2010-01-25 11:01:51 -0600149 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600150 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500151#endif
152#endif
153
154#else
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500155 uint plat_ratio,e500_ratio,half_freqSystemBus;
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530156#if defined(CONFIG_FSL_LBC)
Trent Piephoada591d2008-12-03 15:16:37 -0800157 uint lcrr_div;
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530158#endif
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500159 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400160#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600161 __maybe_unused u32 qe_ratio;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400162#endif
wdenk42d1f032003-10-15 23:53:47 +0000163
164 plat_ratio = (gur->porpllsr) & 0x0000003e;
165 plat_ratio >>= 1;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500166 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500167
168 /* Divide before multiply to avoid integer
169 * overflow for processor speeds above 2GHz */
170 half_freqSystemBus = sysInfo->freqSystemBus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530171 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500172 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
173 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
174 }
James Yanga3e77fa2008-02-08 18:05:08 -0600175
176 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
Kumar Galad4357932007-12-07 04:59:26 -0600177 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
178
179#ifdef CONFIG_DDR_CLK_FREQ
180 {
Jason Jinc0391112008-09-27 14:40:57 +0800181 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
182 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600183 if (ddr_ratio != 0x7)
184 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
185 }
186#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800187
Haiying Wangb3d7f202009-05-20 12:30:29 -0400188#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600189#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
190 defined(CONFIG_P1021) || defined(CONFIG_P1025)
191 sysInfo->freqQE = sysInfo->freqSystemBus;
192#else
Haiying Wangb3d7f202009-05-20 12:30:29 -0400193 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
194 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
195 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
196#endif
Haiying Wanga52d2f82011-02-11 01:25:30 -0600197#endif
Haiying Wangb3d7f202009-05-20 12:30:29 -0400198
Haiying Wang24995d82011-01-20 22:26:31 +0000199#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Gala939cdcd2011-03-10 06:09:20 -0600200 sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
Haiying Wang24995d82011-01-20 22:26:31 +0000201#endif
202
203#endif /* CONFIG_FSL_CORENET */
204
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530205#if defined(CONFIG_FSL_LBC)
Trent Piephoada591d2008-12-03 15:16:37 -0800206#if defined(CONFIG_SYS_LBC_LCRR)
207 /* We will program LCRR to this value later */
208 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
209#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500210 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800211#endif
212 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800213#if defined(CONFIG_FSL_CORENET)
214 /* If this is corenet based SoC, bit-representation
215 * for four times the clock divider values.
216 */
217 lcrr_div *= 4;
218#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800219 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
220 /*
221 * Yes, the entire PQ38 family use the same
222 * bit-representation for twice the clock divider values.
223 */
224 lcrr_div *= 2;
225#endif
226 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
227 } else {
228 /* In case anyone cares what the unknown value is */
229 sysInfo->freqLocalBus = lcrr_div;
230 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530231#endif
wdenk42d1f032003-10-15 23:53:47 +0000232}
233
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500234
wdenk42d1f032003-10-15 23:53:47 +0000235int get_clocks (void)
236{
wdenk42d1f032003-10-15 23:53:47 +0000237 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500238#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500240#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500241#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000243 uint sccr, dfbrg;
244
245 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600246 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
247 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000248 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
249#endif
250 get_sys_info (&sys_info);
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500251 gd->cpu_clk = sys_info.freqProcessor[0];
wdenk42d1f032003-10-15 23:53:47 +0000252 gd->bus_clk = sys_info.freqSystemBus;
James Yanga3e77fa2008-02-08 18:05:08 -0600253 gd->mem_clk = sys_info.freqDDRBus;
Trent Piephoada591d2008-12-03 15:16:37 -0800254 gd->lbc_clk = sys_info.freqLocalBus;
Timur Tabi88353a92008-04-04 11:15:58 -0500255
Haiying Wangb3d7f202009-05-20 12:30:29 -0400256#ifdef CONFIG_QE
257 gd->qe_clk = sys_info.freqQE;
258 gd->brg_clk = gd->qe_clk / 2;
259#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500260 /*
261 * The base clock for I2C depends on the actual SOC. Unfortunately,
262 * there is no pattern that can be used to determine the frequency, so
263 * the only choice is to look up the actual SOC number and use the value
264 * for that SOC. This information is taken from application note
265 * AN2919.
266 */
267#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
268 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
Timur Tabi943afa22008-01-09 14:35:26 -0600269 gd->i2c1_clk = sys_info.freqSystemBus;
Timur Tabi88353a92008-04-04 11:15:58 -0500270#elif defined(CONFIG_MPC8544)
271 /*
272 * On the 8544, the I2C clock is the same as the SEC clock. This can be
273 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
274 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
275 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
276 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
277 */
278 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Wolfgang Grandeggerdffd2442008-09-30 10:55:57 +0200279 gd->i2c1_clk = sys_info.freqSystemBus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500280 else
281 gd->i2c1_clk = sys_info.freqSystemBus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500282#else
283 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
284 gd->i2c1_clk = sys_info.freqSystemBus / 2;
285#endif
286 gd->i2c2_clk = gd->i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600287
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530288#if defined(CONFIG_FSL_ESDHC)
Priyanka Jain7d640e92011-02-08 15:45:25 +0530289#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
290 defined(CONFIG_P1014)
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400291 gd->sdhc_clk = gd->bus_clk;
292#else
Kumar Galaef50d6c2008-08-12 11:14:19 -0500293 gd->sdhc_clk = gd->bus_clk / 2;
294#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400295#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500296
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500297#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000298 gd->vco_out = 2*sys_info.freqSystemBus;
299 gd->cpm_clk = gd->vco_out / 2;
300 gd->scc_clk = gd->vco_out / 4;
301 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
302#endif
303
304 if(gd->cpu_clk != 0) return (0);
305 else return (1);
306}
307
308
309/********************************************
310 * get_bus_freq
311 * return system bus freq in Hz
312 *********************************************/
313ulong get_bus_freq (ulong dummy)
314{
James Yanga3e77fa2008-02-08 18:05:08 -0600315 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000316}
Kumar Galad4357932007-12-07 04:59:26 -0600317
318/********************************************
319 * get_ddr_freq
320 * return ddr bus freq in Hz
321 *********************************************/
322ulong get_ddr_freq (ulong dummy)
323{
James Yanga3e77fa2008-02-08 18:05:08 -0600324 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600325}