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wdenk73a8b272003-06-05 19:27:42 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <mpc8xx.h>
27
28/* ------------------------------------------------------------------------- */
29
30static long int dram_size (long int, long int *, long int);
31
32/* ------------------------------------------------------------------------- */
33
34#define _NOT_USED_ 0xFFFFCC25
35
36const uint sdram_table[] =
37{
38 /*
39 * Single Read. (Offset 00h in UPMA RAM)
40 */
41 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
42 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
43
44 /*
45 * Burst Read. (Offset 08h in UPMA RAM)
46 */
47 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
48 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
51
52 /*
53 * Single Write. (Offset 18h in UPMA RAM)
54 */
55 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57
58 /*
59 * Burst Write. (Offset 20h in UPMA RAM)
60 */
61 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
62 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65
66 /*
67 * Refresh. (Offset 30h in UPMA RAM)
68 * (Initialization code at 0x36)
69 */
70 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
72 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
73
74 /*
75 * Exception. (Offset 3Ch in UPMA RAM)
76 */
77 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
78};
79
80/* ------------------------------------------------------------------------- */
81
82
83/*
84 * Check Board Identity:
85 */
86
87int checkboard (void)
88{
89 puts ("Board: RMU\n") ;
90 return (0) ;
91}
92
93/* ------------------------------------------------------------------------- */
94
95long int initdram (int board_type)
96{
wdenk5fa66df2003-10-29 23:18:55 +000097 volatile immap_t *immap = (immap_t *) CFG_IMMR;
98 volatile memctl8xx_t *memctl = &immap->im_memctl;
99 long int size9;
wdenk73a8b272003-06-05 19:27:42 +0000100
wdenk5fa66df2003-10-29 23:18:55 +0000101 upmconfig (UPMA, (uint *) sdram_table,
102 sizeof (sdram_table) / sizeof (uint));
wdenk73a8b272003-06-05 19:27:42 +0000103
104 /* Refresh clock prescalar */
wdenk5fa66df2003-10-29 23:18:55 +0000105 memctl->memc_mptpr = CFG_MPTPR;
wdenk73a8b272003-06-05 19:27:42 +0000106
wdenk5fa66df2003-10-29 23:18:55 +0000107 memctl->memc_mar = 0x00000088;
wdenk73a8b272003-06-05 19:27:42 +0000108
109 /* Map controller banks 1 to the SDRAM bank */
wdenk5fa66df2003-10-29 23:18:55 +0000110 memctl->memc_or1 = CFG_OR1_PRELIM;
111 memctl->memc_br1 = CFG_BR1_PRELIM;
wdenk73a8b272003-06-05 19:27:42 +0000112
wdenk5fa66df2003-10-29 23:18:55 +0000113 memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk73a8b272003-06-05 19:27:42 +0000114
wdenk5fa66df2003-10-29 23:18:55 +0000115 udelay (200);
wdenk73a8b272003-06-05 19:27:42 +0000116
wdenk5fa66df2003-10-29 23:18:55 +0000117 /* perform SDRAM initializsation sequence */
wdenk73a8b272003-06-05 19:27:42 +0000118
wdenk5fa66df2003-10-29 23:18:55 +0000119 memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
120 udelay (1);
wdenk73a8b272003-06-05 19:27:42 +0000121
wdenk5fa66df2003-10-29 23:18:55 +0000122 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
wdenk73a8b272003-06-05 19:27:42 +0000123
wdenk5fa66df2003-10-29 23:18:55 +0000124 udelay (1000);
wdenk73a8b272003-06-05 19:27:42 +0000125
wdenkd94f92c2003-08-28 09:41:22 +0000126 /* Check Bank 0 Memory Size,
127 * 9 column mode
wdenk73a8b272003-06-05 19:27:42 +0000128 */
129
wdenk5fa66df2003-10-29 23:18:55 +0000130 size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
131 SDRAM_MAX_SIZE);
wdenk73a8b272003-06-05 19:27:42 +0000132
wdenkd94f92c2003-08-28 09:41:22 +0000133 /*
134 * Final mapping:
135 */
136
137 memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
138 udelay (1000);
139
wdenk5fa66df2003-10-29 23:18:55 +0000140 return (size9);
wdenk73a8b272003-06-05 19:27:42 +0000141}
142
143/* ------------------------------------------------------------------------- */
144
145/*
146 * Check memory range for valid RAM. A simple memory test determines
147 * the actually available RAM size between addresses `base' and
148 * `base + maxsize'. Some (not all) hardware errors are detected:
149 * - short between address lines
150 * - short between data lines
151 */
152
wdenk5fa66df2003-10-29 23:18:55 +0000153static long int dram_size (long int mamr_value, long int *base,
154 long int maxsize)
wdenk73a8b272003-06-05 19:27:42 +0000155{
wdenk5fa66df2003-10-29 23:18:55 +0000156 volatile immap_t *immap = (immap_t *) CFG_IMMR;
157 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk73a8b272003-06-05 19:27:42 +0000158
wdenk5fa66df2003-10-29 23:18:55 +0000159 memctl->memc_mamr = mamr_value;
wdenk73a8b272003-06-05 19:27:42 +0000160
wdenkc83bf6a2004-01-06 22:38:14 +0000161 return (get_ram_size(base, maxsize));
wdenk73a8b272003-06-05 19:27:42 +0000162}