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Jason Liu938080d2011-05-13 01:58:55 +00001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/arch/imx-regs.h>
27#include <asm/arch/mx5x_pins.h>
28#include <asm/arch/sys_proto.h>
29#include <asm/arch/crm_regs.h>
Stefano Babicf92e4e62012-02-22 00:24:41 +000030#include <asm/arch/clock.h>
Jason Liu938080d2011-05-13 01:58:55 +000031#include <asm/arch/iomux.h>
32#include <asm/arch/clock.h>
33#include <asm/errno.h>
34#include <netdev.h>
35#include <i2c.h>
36#include <mmc.h>
37#include <fsl_esdhc.h>
Stefano Babic50410072011-08-21 10:59:33 +020038#include <asm/gpio.h>
Fabio Estevame7e33722012-04-30 08:12:04 +000039#include <pmic.h>
40#include <dialog_pmic.h>
Fabio Estevam5b547f32012-05-07 10:25:59 +000041#include <fsl_pmic.h>
Fabio Estevamf714b0a2012-05-10 15:07:35 +000042#include <linux/fb.h>
43#include <ipu_pixfmt.h>
44
Fabio Estevam3ef0a312012-08-21 10:01:56 +000045#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
Jason Liu938080d2011-05-13 01:58:55 +000046
47DECLARE_GLOBAL_DATA_PTR;
48
Jason Liu938080d2011-05-13 01:58:55 +000049int dram_init(void)
50{
51 u32 size1, size2;
52
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000053 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
54 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Jason Liu938080d2011-05-13 01:58:55 +000055
56 gd->ram_size = size1 + size2;
57
58 return 0;
59}
60void dram_init_banksize(void)
61{
62 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
63 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
64
65 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
66 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
67}
68
Fabio Estevam54cd1de2012-05-08 03:40:49 +000069u32 get_board_rev(void)
70{
71 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
72 struct fuse_bank *bank = &iim->bank[0];
73 struct fuse_bank0_regs *fuse =
74 (struct fuse_bank0_regs *)bank->fuse_regs;
75
76 int rev = readl(&fuse->gp[6]);
77
Fabio Estevameae08eb2012-05-29 05:54:39 +000078 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
79 rev = 0;
80
Fabio Estevam54cd1de2012-05-08 03:40:49 +000081 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
82}
83
Jason Liu938080d2011-05-13 01:58:55 +000084static void setup_iomux_uart(void)
85{
86 /* UART1 RXD */
87 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
88 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
89 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
90 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
91 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
92 PAD_CTL_ODE_OPENDRAIN_ENABLE);
93 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
94
95 /* UART1 TXD */
96 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
97 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
98 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
99 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
100 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
101 PAD_CTL_ODE_OPENDRAIN_ENABLE);
102}
103
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100104#ifdef CONFIG_USB_EHCI_MX5
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +0000105int board_ehci_hcd_init(int port)
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100106{
Fabio Estevam6ecaee82012-05-07 10:42:57 +0000107 /* request VBUS power enable pin, GPIO7_8 */
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100108 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
Fabio Estevam6ecaee82012-05-07 10:42:57 +0000109 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +0000110 return 0;
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +0100111}
112#endif
113
Jason Liu938080d2011-05-13 01:58:55 +0000114static void setup_iomux_fec(void)
115{
116 /*FEC_MDIO*/
117 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
118 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
119 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
120 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
121 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
122 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
123
124 /*FEC_MDC*/
125 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
126 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
127
128 /* FEC RXD1 */
129 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
130 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
131 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
132
133 /* FEC RXD0 */
134 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
135 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
136 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
137
138 /* FEC TXD1 */
139 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
140 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
141
142 /* FEC TXD0 */
143 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
144 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
145
146 /* FEC TX_EN */
147 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
148 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
149
150 /* FEC TX_CLK */
151 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
152 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
153 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
154
155 /* FEC RX_ER */
156 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
157 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
158 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
159
160 /* FEC CRS */
161 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
162 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
163 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
164}
165
166#ifdef CONFIG_FSL_ESDHC
167struct fsl_esdhc_cfg esdhc_cfg[2] = {
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000168 {MMC_SDHC1_BASE_ADDR},
169 {MMC_SDHC3_BASE_ADDR},
Jason Liu938080d2011-05-13 01:58:55 +0000170};
171
Thierry Reding314284b2012-01-02 01:15:36 +0000172int board_mmc_getcd(struct mmc *mmc)
Jason Liu938080d2011-05-13 01:58:55 +0000173{
174 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Thierry Reding314284b2012-01-02 01:15:36 +0000175 int ret;
Jason Liu938080d2011-05-13 01:58:55 +0000176
Fabio Estevam73128aa2011-11-15 05:51:29 +0000177 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530178 gpio_direction_input(IMX_GPIO_NR(3, 11));
Fabio Estevam73128aa2011-11-15 05:51:29 +0000179 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530180 gpio_direction_input(IMX_GPIO_NR(3, 13));
Fabio Estevam73128aa2011-11-15 05:51:29 +0000181
Jason Liu938080d2011-05-13 01:58:55 +0000182 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530183 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
Jason Liu938080d2011-05-13 01:58:55 +0000184 else
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530185 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
Jason Liu938080d2011-05-13 01:58:55 +0000186
Thierry Reding314284b2012-01-02 01:15:36 +0000187 return ret;
Jason Liu938080d2011-05-13 01:58:55 +0000188}
189
190int board_mmc_init(bd_t *bis)
191{
192 u32 index;
193 s32 status = 0;
194
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000195 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
196 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
197
Jason Liu938080d2011-05-13 01:58:55 +0000198 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
199 switch (index) {
200 case 0:
201 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
202 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
203 mxc_request_iomux(MX53_PIN_SD1_DATA0,
204 IOMUX_CONFIG_ALT0);
205 mxc_request_iomux(MX53_PIN_SD1_DATA1,
206 IOMUX_CONFIG_ALT0);
207 mxc_request_iomux(MX53_PIN_SD1_DATA2,
208 IOMUX_CONFIG_ALT0);
209 mxc_request_iomux(MX53_PIN_SD1_DATA3,
210 IOMUX_CONFIG_ALT0);
211 mxc_request_iomux(MX53_PIN_EIM_DA13,
212 IOMUX_CONFIG_ALT1);
213
214 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
215 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
216 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
217 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
218 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
219 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
220 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
221 PAD_CTL_DRV_HIGH);
222 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
223 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
224 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
225 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
226 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
227 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
228 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
229 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
230 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
231 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
232 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
233 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
234 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
235 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
236 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
237 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
238 break;
239 case 1:
240 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
241 IOMUX_CONFIG_ALT2);
242 mxc_request_iomux(MX53_PIN_ATA_IORDY,
243 IOMUX_CONFIG_ALT2);
244 mxc_request_iomux(MX53_PIN_ATA_DATA8,
245 IOMUX_CONFIG_ALT4);
246 mxc_request_iomux(MX53_PIN_ATA_DATA9,
247 IOMUX_CONFIG_ALT4);
248 mxc_request_iomux(MX53_PIN_ATA_DATA10,
249 IOMUX_CONFIG_ALT4);
250 mxc_request_iomux(MX53_PIN_ATA_DATA11,
251 IOMUX_CONFIG_ALT4);
252 mxc_request_iomux(MX53_PIN_ATA_DATA0,
253 IOMUX_CONFIG_ALT4);
254 mxc_request_iomux(MX53_PIN_ATA_DATA1,
255 IOMUX_CONFIG_ALT4);
256 mxc_request_iomux(MX53_PIN_ATA_DATA2,
257 IOMUX_CONFIG_ALT4);
258 mxc_request_iomux(MX53_PIN_ATA_DATA3,
259 IOMUX_CONFIG_ALT4);
260 mxc_request_iomux(MX53_PIN_EIM_DA11,
261 IOMUX_CONFIG_ALT1);
262
263 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
264 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
265 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
266 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
267 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
268 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
269 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
270 PAD_CTL_DRV_HIGH);
271 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
272 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
273 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
274 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
275 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
276 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
277 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
278 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
279 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
280 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
281 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
282 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
283 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
284 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
285 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
286 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
287 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
288 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
289 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
290 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
291 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
292 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
293 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
294 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
295 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
296 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
297 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
298 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
299 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
300 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
301 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
302 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
303
304 break;
305 default:
306 printf("Warning: you configured more ESDHC controller"
307 "(%d) as supported by the board(2)\n",
308 CONFIG_SYS_FSL_ESDHC_NUM);
309 return status;
310 }
311 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
312 }
313
314 return status;
315}
316#endif
317
Fabio Estevame7e33722012-04-30 08:12:04 +0000318static void setup_iomux_i2c(void)
319{
320 /* I2C1 SDA */
321 mxc_request_iomux(MX53_PIN_CSI0_D8,
322 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
323 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
324 INPUT_CTL_PATH0);
325 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
326 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
327 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
328 PAD_CTL_PUE_PULL |
329 PAD_CTL_ODE_OPENDRAIN_ENABLE);
330 /* I2C1 SCL */
331 mxc_request_iomux(MX53_PIN_CSI0_D9,
332 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
333 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
334 INPUT_CTL_PATH0);
335 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
336 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
337 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
338 PAD_CTL_PUE_PULL |
339 PAD_CTL_ODE_OPENDRAIN_ENABLE);
340}
341
342static int power_init(void)
343{
Fabio Estevam5b547f32012-05-07 10:25:59 +0000344 unsigned int val;
345 int ret = -1;
Fabio Estevame7e33722012-04-30 08:12:04 +0000346 struct pmic *p;
347
Fabio Estevam5b547f32012-05-07 10:25:59 +0000348 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
349 pmic_dialog_init();
350 p = get_pmic();
Fabio Estevame7e33722012-04-30 08:12:04 +0000351
Fabio Estevam5b547f32012-05-07 10:25:59 +0000352 /* Set VDDA to 1.25V */
353 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
354 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
Fabio Estevame7e33722012-04-30 08:12:04 +0000355
Fabio Estevam5b547f32012-05-07 10:25:59 +0000356 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
357 val |= DA9052_SUPPLY_VBCOREGO;
358 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
Fabio Estevame7e33722012-04-30 08:12:04 +0000359
Fabio Estevam5b547f32012-05-07 10:25:59 +0000360 /* Set Vcc peripheral to 1.30V */
361 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
362 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
363 }
364
365 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
366 pmic_init();
367 p = get_pmic();
368
369 /* Set VDDGP to 1.25V for 1GHz on SW1 */
370 pmic_reg_read(p, REG_SW_0, &val);
371 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
372 ret = pmic_reg_write(p, REG_SW_0, val);
373
374 /* Set VCC as 1.30V on SW2 */
375 pmic_reg_read(p, REG_SW_1, &val);
376 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
377 ret |= pmic_reg_write(p, REG_SW_1, val);
378
379 /* Set global reset timer to 4s */
380 pmic_reg_read(p, REG_POWER_CTL2, &val);
381 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
382 ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
Fabio Estevam768a0592012-05-07 10:26:00 +0000383
384 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
385 pmic_reg_read(p, REG_MODE_0, &val);
386 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
387 ret |= pmic_reg_write(p, REG_MODE_0, val);
388
389 /* Set SWBST to 5V in auto mode */
390 val = SWBST_AUTO;
391 ret |= pmic_reg_write(p, SWBST_CTRL, val);
Fabio Estevam5b547f32012-05-07 10:25:59 +0000392 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000393
394 return ret;
395}
396
397static void clock_1GHz(void)
398{
399 int ret;
Benoît Thébaudeau833b6432012-09-27 10:19:58 +0000400 u32 ref_clk = MXC_HCLK;
Fabio Estevame7e33722012-04-30 08:12:04 +0000401 /*
402 * After increasing voltage to 1.25V, we can switch
403 * CPU clock to 1GHz and DDR to 400MHz safely
404 */
405 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
406 if (ret)
407 printf("CPU: Switch CPU clock to 1GHZ failed\n");
408
409 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
410 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
411 if (ret)
412 printf("CPU: Switch DDR clock to 400MHz failed\n");
413}
414
Eric Nelson08fd6a32012-10-03 07:27:39 +0000415static struct fb_videomode const claa_wvga = {
Fabio Estevamf714b0a2012-05-10 15:07:35 +0000416 .name = "CLAA07LC0ACW",
417 .refresh = 57,
418 .xres = 800,
419 .yres = 480,
420 .pixclock = 37037,
421 .left_margin = 40,
422 .right_margin = 60,
423 .upper_margin = 10,
424 .lower_margin = 10,
425 .hsync_len = 20,
426 .vsync_len = 10,
427 .sync = 0,
428 .vmode = FB_VMODE_NONINTERLACED
429};
430
431void lcd_iomux(void)
432{
433 mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
434 mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
435 mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
436 mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
437 mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
438 mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
439 mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
440 mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
441 mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
442 mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
443 mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
444 mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
445 mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
446 mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
447 mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
448 mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
449 mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
450 mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
451 mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
452 mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
453 mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
454 mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
455 mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
456 mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
457 mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
458 mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
459 mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
460 mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
461
462 /* Turn on GPIO backlight */
463 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
464 gpio_direction_output(MX53LOCO_LCD_POWER, 1);
465
466 /* Turn on display contrast */
467 mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
468 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
469}
470
471void lcd_enable(void)
472{
473 int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
474 if (ret)
475 printf("LCD cannot be configured: %d\n", ret);
476}
477
Jason Liu938080d2011-05-13 01:58:55 +0000478int board_early_init_f(void)
479{
480 setup_iomux_uart();
481 setup_iomux_fec();
Fabio Estevamf714b0a2012-05-10 15:07:35 +0000482 lcd_iomux();
Jason Liu938080d2011-05-13 01:58:55 +0000483
484 return 0;
485}
486
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000487int print_cpuinfo(void)
488{
489 u32 cpurev;
490
491 cpurev = get_cpu_rev();
492 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
493 (cpurev & 0xFF000) >> 12,
494 (cpurev & 0x000F0) >> 4,
495 (cpurev & 0x0000F) >> 0,
496 mxc_get_clock(MXC_ARM_CLK) / 1000000);
497 printf("Reset cause: %s\n", get_reset_cause());
498 return 0;
499}
500
Stefano Babic3e077372012-08-05 00:18:53 +0000501/*
502 * Do not overwrite the console
503 * Use always serial for U-Boot console
504 */
505int overwrite_console(void)
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000506{
Stefano Babic3e077372012-08-05 00:18:53 +0000507 return 1;
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000508}
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000509
Jason Liu938080d2011-05-13 01:58:55 +0000510int board_init(void)
511{
Jason Liu938080d2011-05-13 01:58:55 +0000512 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
513
Stefano Babicf92e4e62012-02-22 00:24:41 +0000514 mxc_set_sata_internal_clock();
Fabio Estevameae08eb2012-05-29 05:54:39 +0000515 setup_iomux_i2c();
516 if (!power_init())
517 clock_1GHz();
518 print_cpuinfo();
Stefano Babicf92e4e62012-02-22 00:24:41 +0000519
Fabio Estevamf714b0a2012-05-10 15:07:35 +0000520 lcd_enable();
521
Jason Liu938080d2011-05-13 01:58:55 +0000522 return 0;
523}
524
525int checkboard(void)
526{
527 puts("Board: MX53 LOCO\n");
528
529 return 0;
530}