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wdenk10a36a92004-07-10 23:02:23 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
40#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
41
42
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050043#define CONFIG_CPM2 1 /* has CPM2 */
wdenk10a36a92004-07-10 23:02:23 +000044#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050045#define CONFIG_MPC8560 1
wdenk10a36a92004-07-10 23:02:23 +000046
47/* XXX flagging this as something I might want to delete */
48#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
49
50#define CONFIG_TSEC_ENET /* tsec ethernet support */
51#undef CONFIG_PCI /* pci ethernet support */
52#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
53
Kumar Galae2b159d2008-01-16 09:05:27 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk10a36a92004-07-10 23:02:23 +000055
56#define CONFIG_ENV_OVERWRITE
57
58/* Using Localbus SDRAM to emulate flash before we can program the flash,
59 * normally you need a flash-boot image(u-boot.bin), if so undef this.
60 */
61#undef CONFIG_RAM_AS_FLASH
62
63#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
64 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
65#else
66 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
67#endif
68
69/* below can be toggled for performance analysis. otherwise use default */
70#define CONFIG_L2_CACHE /* toggle L2 cache */
71#undef CONFIG_BTB /* toggle branch predition */
72#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
73
74#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
75
76#undef CFG_DRAM_TEST /* memory test, takes time */
77#define CFG_MEMTEST_START 0x00200000 /* memtest region */
78#define CFG_MEMTEST_END 0x00400000
79
80#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
81 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
82 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
83#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
84#endif
85
86/*
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
89 */
90#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91
92#if XXX
93 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
94#else
95 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
96#endif
Kumar Galaf69766e2008-01-30 14:55:14 -060097#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenk10a36a92004-07-10 23:02:23 +000098#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
99
100#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
101#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
102#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
103#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
104
105#undef CONFIG_DDR_ECC /* only for ECC DDR module */
106#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
107
108#if defined(CONFIG_MPC85xx_REV1)
109 #define CONFIG_DDR_DLL /* possible DLL fix needed */
110#endif
111
112#undef CONFIG_CLOCKS_IN_MHZ
113
114#if defined(CONFIG_RAM_AS_FLASH)
115 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
116 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
117 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
118 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
119#else /* Boot from real Flash */
120 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
121 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
122 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
123 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
124#endif
125#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
126
127/* local bus definitions */
128#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
129#define CFG_OR1_PRELIM 0xfc000ff7
130
131#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
132#define CFG_OR2_PRELIM 0x00000000
133
134#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
135#define CFG_OR3_PRELIM 0xfc000cc1
136
137#if defined(CONFIG_RAM_AS_FLASH)
138 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
139#else
140 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
141#endif
142#define CFG_OR4_PRELIM 0xfc000cc1
143
144#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
145#if 1
146 #define CFG_OR5_PRELIM 0xff000ff7
147#else
148 #define CFG_OR5_PRELIM 0xff0000f0
149#endif
150
151#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
152#define CFG_OR6_PRELIM 0xfc000ff7
153#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
154#define CFG_LBC_LBCR 0x00000000
155#define CFG_LBC_LSRT 0x20000000
156#define CFG_LBC_MRTPR 0x20000000
157#define CFG_LBC_LSDMR_1 0x2861b723
158#define CFG_LBC_LSDMR_2 0x0861b723
159#define CFG_LBC_LSDMR_3 0x0861b723
160#define CFG_LBC_LSDMR_4 0x1861b723
161#define CFG_LBC_LSDMR_5 0x4061b723
162
163/* just hijack the MOT BCSR def for SBC8560 misc devices */
164#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
165/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
166
167#define CONFIG_L1_INIT_RAM
168#define CFG_INIT_RAM_LOCK 1
169#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
170#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
171
172#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
173#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
177#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
178
179/* Serial Port */
180#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
181#undef CONFIG_CONS_NONE /* define if console on something else */
182
183#define CONFIG_CONS_INDEX 1
184#undef CONFIG_SERIAL_SOFTWARE_FIFO
185#define CFG_NS16550
186#define CFG_NS16550_SERIAL
187#define CFG_NS16550_REG_SIZE 1
188#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
189#define CONFIG_BAUDRATE 9600
190
191#define CFG_BAUDRATE_TABLE \
192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
193
194#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
195#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
196
197/* Use the HUSH parser */
198#define CFG_HUSH_PARSER
199#ifdef CFG_HUSH_PARSER
200#define CFG_PROMPT_HUSH_PS2 "> "
201#endif
202
Jon Loeliger20476722006-10-20 15:50:15 -0500203/*
204 * I2C
205 */
206#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
207#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk10a36a92004-07-10 23:02:23 +0000208#undef CONFIG_SOFT_I2C /* I2C bit-banged */
209#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
210#define CFG_I2C_SLAVE 0x7F
211#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500212#define CFG_I2C_OFFSET 0x3000
wdenk10a36a92004-07-10 23:02:23 +0000213
214#define CFG_PCI_MEM_BASE 0xC0000000
215#define CFG_PCI_MEM_PHYS 0xC0000000
216#define CFG_PCI_MEM_SIZE 0x10000000
217
218#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
219
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500220# define CONFIG_NET_MULTI 1
221# define CONFIG_MII 1 /* MII PHY management */
222# define CONFIG_MPC85xx_TSEC1
223# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
224# define TSEC1_PHY_ADDR 25
225# define TSEC1_PHYIDX 0
226/* Options are: TSEC0 */
227# define CONFIG_ETHPRIME "TSEC0"
wdenk10a36a92004-07-10 23:02:23 +0000228
229#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
230
231 #undef CONFIG_ETHER_NONE /* define if ether on something else */
232 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
233 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
234
235 #if (CONFIG_ETHER_INDEX == 2)
236 /*
237 * - Rx-CLK is CLK13
238 * - Tx-CLK is CLK14
239 * - Select bus for bd/buffers
240 * - Full duplex
241 */
242 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
243 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
244 #define CFG_CPMFCR_RAMTYPE 0
245 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
246
247 #elif (CONFIG_ETHER_INDEX == 3)
248 /* need more definitions here for FE3 */
249 #endif /* CONFIG_ETHER_INDEX */
250
251 #define CONFIG_MII /* MII PHY management */
252 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
253 /*
254 * GPIO pins used for bit-banged MII communications
255 */
256 #define MDIO_PORT 2 /* Port C */
257 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
258 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
259 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
260
261 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
262 else iop->pdat &= ~0x00400000
263
264 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
265 else iop->pdat &= ~0x00200000
266
267 #define MIIDELAY udelay(1)
268
269#endif
270
271/*-----------------------------------------------------------------------
272 * FLASH and environment organization
273 */
274
275#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
276#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
277#if 0
278#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
279#define CFG_FLASH_PROTECTION /* use hardware protection */
280#endif
281#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
282#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
283
284#undef CFG_FLASH_CHECKSUM
285#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
286#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
287
288#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
289
290#if 0
291/* XXX This doesn't work and I don't want to fix it */
292#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
293 #define CFG_RAMBOOT
294#else
295 #undef CFG_RAMBOOT
296#endif
297#endif
298
299/* Environment */
300#if !defined(CFG_RAMBOOT)
301 #if defined(CONFIG_RAM_AS_FLASH)
302 #define CFG_ENV_IS_NOWHERE
303 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
304 #define CFG_ENV_SIZE 0x2000
305 #else
306 #define CFG_ENV_IS_IN_FLASH 1
307 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
308 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
309 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
310 #endif
311#else
312 #define CFG_NO_FLASH 1 /* Flash is not usable now */
313 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
314 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
315 #define CFG_ENV_SIZE 0x2000
316#endif
317
318#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
319/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
320#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
321#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
322
323#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
324#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
325
Jon Loeliger2835e512007-06-13 13:22:08 -0500326
327/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500328 * BOOTP options
329 */
330#define CONFIG_BOOTP_BOOTFILESIZE
331#define CONFIG_BOOTP_BOOTPATH
332#define CONFIG_BOOTP_GATEWAY
333#define CONFIG_BOOTP_HOSTNAME
334
335
336/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500337 * Command line configuration.
338 */
339#include <config_cmd_default.h>
340
341#define CONFIG_CMD_PING
342#define CONFIG_CMD_I2C
343
344#if defined(CONFIG_PCI)
345 #define CONFIG_CMD_PCI
wdenk10a36a92004-07-10 23:02:23 +0000346#endif
347
Jon Loeliger2835e512007-06-13 13:22:08 -0500348#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
349 #define CONFIG_CMD_MII
350#endif
351
352#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
353 #undef CONFIG_CMD_ENV
354 #undef CONFIG_CMD_LOADS
355#endif
356
wdenk10a36a92004-07-10 23:02:23 +0000357
358#undef CONFIG_WATCHDOG /* watchdog disabled */
359
360/*
361 * Miscellaneous configurable options
362 */
363#define CFG_LONGHELP /* undef to save memory */
364#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500365#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000366 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
367#else
368 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
369#endif
370#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
371#define CFG_MAXARGS 16 /* max number of command args */
372#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
373#define CFG_LOAD_ADDR 0x1000000 /* default load address */
374#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
375
376/*
377 * For booting Linux, the board info and command line data
378 * have to be in the first 8 MB of memory, since this is
379 * the maximum mapped by the Linux kernel during initialization.
380 */
381#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
382
wdenk10a36a92004-07-10 23:02:23 +0000383/*
384 * Internal Definitions
385 *
386 * Boot Flags
387 */
388#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
389#define BOOTFLAG_WARM 0x02 /* Software reboot */
390
Jon Loeliger2835e512007-06-13 13:22:08 -0500391#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000392 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
393 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
394#endif
395
396/*Note: change below for your network setting!!! */
397#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000398# define CONFIG_ETHADDR 00:01:af:07:9b:8a
399# define CONFIG_HAS_ETH1
400# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
401# define CONFIG_HAS_ETH2
402# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
wdenk10a36a92004-07-10 23:02:23 +0000403#endif
404
405#define CONFIG_SERVERIP 192.168.0.131
406#define CONFIG_IPADDR 192.168.0.105
407#define CONFIG_GATEWAYIP 0.0.0.0
408#define CONFIG_NETMASK 255.255.255.0
409#define CONFIG_HOSTNAME SBC8560
410#define CONFIG_ROOTPATH /home/ppc
411#define CONFIG_BOOTFILE pImage
412
413#endif /* __CONFIG_H */