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Michal Simek76316a32007-03-11 13:42:58 +01001/*
2 * (C) Copyright 2007 Michal Simek
3 *
Michal Simekdb14d772007-09-24 00:18:46 +02004 * Michal SIMEK <monstr@monstr.eu>
Michal Simek76316a32007-03-11 13:42:58 +01005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Michal Simekfb05f6d2007-05-07 23:58:31 +020026#include <asm/asm.h>
Michal Simek76316a32007-03-11 13:42:58 +010027
Michal Simek76316a32007-03-11 13:42:58 +010028int dcache_status (void)
29{
30 int i = 0;
31 int mask = 0x80;
32 __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
33 /* i&=0x80 */
34 __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
35 return i;
36}
37
38int icache_status (void)
39{
40 int i = 0;
41 int mask = 0x20;
42 __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
43 /* i&=0x20 */
44 __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
45 return i;
46}
Michal Simekf3f001a2007-05-07 19:25:08 +020047
48void icache_enable (void) {
Michal Simekfb05f6d2007-05-07 23:58:31 +020049 MSRSET(0x20);
Michal Simekf3f001a2007-05-07 19:25:08 +020050}
51
52void icache_disable(void) {
Michal Simek8ff972c2010-04-16 12:56:33 +020053 /* we are not generate ICACHE size -> flush whole cache */
54 flush_cache(0, 32768);
Michal Simekfb05f6d2007-05-07 23:58:31 +020055 MSRCLR(0x20);
Michal Simekf3f001a2007-05-07 19:25:08 +020056}
57
58void dcache_enable (void) {
Michal Simekfb05f6d2007-05-07 23:58:31 +020059 MSRSET(0x80);
Michal Simekf3f001a2007-05-07 19:25:08 +020060}
61
62void dcache_disable(void) {
Michal Simek8ff972c2010-04-16 12:56:33 +020063#ifdef XILINX_USE_DCACHE
64#ifdef XILINX_DCACHE_BYTE_SIZE
65 flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
66#else
67#warning please rebuild BSPs and update configuration
68 flush_cache(0, 32768);
69#endif
70#endif
Michal Simekfb05f6d2007-05-07 23:58:31 +020071 MSRCLR(0x80);
Michal Simekf3f001a2007-05-07 19:25:08 +020072}
Michal Simek8ff972c2010-04-16 12:56:33 +020073
74void flush_cache (ulong addr, ulong size)
75{
76 int i;
77 for (i = 0; i < size; i += 4)
78 asm volatile (
79#ifdef CONFIG_ICACHE
80 "wic %0, r0;"
81#endif
82 "nop;"
83#ifdef CONFIG_DCACHE
84 "wdc.flush %0, r0;"
85#endif
86 "nop;"
87 :
88 : "r" (addr + i)
89 : "memory");
90}