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Dinh Nguyen3da42852015-06-02 22:52:49 -05001/*
2 * Copyright Altera Corporation (C) 2012-2015
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sdram.h>
Marek Vasut04372fb2015-07-18 02:46:56 +020010#include <errno.h>
Dinh Nguyen3da42852015-06-02 22:52:49 -050011#include "sequencer.h"
12#include "sequencer_auto.h"
13#include "sequencer_auto_ac_init.h"
14#include "sequencer_auto_inst_init.h"
15#include "sequencer_defines.h"
16
Dinh Nguyen3da42852015-06-02 22:52:49 -050017static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020018 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
Dinh Nguyen3da42852015-06-02 22:52:49 -050019
20static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020021 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050022
23static struct socfpga_sdr_reg_file *sdr_reg_file =
Marek Vasuta1c654a2015-07-12 18:31:05 +020024 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050025
26static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
Marek Vasute79025a2015-07-12 18:42:34 +020027 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050028
29static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
Marek Vasut1bc6f142015-07-12 18:54:37 +020030 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050031
32static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
Marek Vasut1bc6f142015-07-12 18:54:37 +020033 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
Dinh Nguyen3da42852015-06-02 22:52:49 -050034
35static struct socfpga_data_mgr *data_mgr =
Marek Vasutc4815f72015-07-12 19:03:33 +020036 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050037
Marek Vasut6cb9f162015-07-12 20:49:39 +020038static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
40
Dinh Nguyen3da42852015-06-02 22:52:49 -050041#define DELTA_D 1
Dinh Nguyen3da42852015-06-02 22:52:49 -050042
43/*
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
47 *
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
53 */
54
55#define DLEVEL 0
56#define STATIC_IN_RTL_SIM 0
57#define STATIC_SKIP_DELAY_LOOPS 0
58
59#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
61
62/* calibration steps requested by the rtl */
63uint16_t dyn_calib_steps;
64
65/*
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
69 *
70 * The mask is set to include all bits when not-skipping, but is
71 * zero when skipping
72 */
73
74uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75
76#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
78
79struct gbl_type *gbl;
80struct param_type *param;
81uint32_t curr_shadow_reg;
82
83static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86
Dinh Nguyen3da42852015-06-02 22:52:49 -050087static void set_failing_group_stage(uint32_t group, uint32_t stage,
88 uint32_t substage)
89{
90 /*
91 * Only set the global stage if there was not been any other
92 * failing group
93 */
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
98 }
99}
100
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200101static void reg_file_set_group(u16 set_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500102{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500104}
105
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200106static void reg_file_set_stage(u8 set_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500107{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500109}
110
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200111static void reg_file_set_sub_stage(u8 set_sub_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500112{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500115}
116
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200117/**
118 * phy_mgr_initialize() - Initialize PHY Manager
119 *
120 * Initialize PHY Manager.
121 */
Marek Vasut9fa9c902015-07-17 01:12:07 +0200122static void phy_mgr_initialize(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500123{
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200124 u32 ratio;
125
Dinh Nguyen3da42852015-06-02 22:52:49 -0500126 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200127 /* Calibration has control over path to memory */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500128 /*
129 * In Hard PHY this is a 2-bit control:
130 * 0: AFI Mux Select
131 * 1: DDIO Mux Select
132 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200133 writel(0x3, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500134
135 /* USER memory clock is not stable we begin initialization */
Marek Vasut1273dd92015-07-12 21:05:08 +0200136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500137
138 /* USER calibration status all set to zero */
Marek Vasut1273dd92015-07-12 21:05:08 +0200139 writel(0, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500140
Marek Vasut1273dd92015-07-12 21:05:08 +0200141 writel(0, &phy_mgr_cfg->cal_debug_info);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500142
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
145 return;
146
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500156}
157
Marek Vasut080bf642015-07-20 08:15:57 +0200158/**
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
160 * @rank: Rank mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
162 *
163 * Set Rank and ODT mask (On-Die Termination).
164 */
Marek Vasutb2dfd102015-07-20 08:03:11 +0200165static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500166{
Marek Vasutb2dfd102015-07-20 08:03:11 +0200167 u32 odt_mask_0 = 0;
168 u32 odt_mask_1 = 0;
169 u32 cs_and_odt_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500170
Marek Vasutb2dfd102015-07-20 08:03:11 +0200171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
172 odt_mask_0 = 0x0;
173 odt_mask_1 = 0x0;
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
Marek Vasut287cdf62015-07-20 08:09:05 +0200175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
176 case 1: /* 1 Rank */
177 /* Read: ODT = 0 ; Write: ODT = 1 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500178 odt_mask_0 = 0x0;
179 odt_mask_1 = 0x1;
Marek Vasut287cdf62015-07-20 08:09:05 +0200180 break;
181 case 2: /* 2 Ranks */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
Marek Vasut080bf642015-07-20 08:15:57 +0200183 /*
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
185 * OR
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
187 *
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
191 *
Dinh Nguyen3da42852015-06-02 22:52:49 -0500192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
194 */
195 odt_mask_0 = 0x3 & ~(1 << rank);
196 odt_mask_1 = 0x3;
197 } else {
198 /*
Marek Vasut080bf642015-07-20 08:15:57 +0200199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
200 *
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
Dinh Nguyen3da42852015-06-02 22:52:49 -0500203 */
204 odt_mask_0 = 0x0;
205 odt_mask_1 = 0x3 & (1 << rank);
206 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200207 break;
208 case 4: /* 4 Ranks */
209 /* Read:
Dinh Nguyen3da42852015-06-02 22:52:49 -0500210 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500211 * | ODT |
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
220 *
221 * Write:
222 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500223 * | ODT |
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
232 */
233 switch (rank) {
234 case 0:
235 odt_mask_0 = 0x4;
236 odt_mask_1 = 0x5;
237 break;
238 case 1:
239 odt_mask_0 = 0x8;
240 odt_mask_1 = 0xA;
241 break;
242 case 2:
243 odt_mask_0 = 0x1;
244 odt_mask_1 = 0x5;
245 break;
246 case 3:
247 odt_mask_0 = 0x2;
248 odt_mask_1 = 0xA;
249 break;
250 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200251 break;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500252 }
Dinh Nguyen3da42852015-06-02 22:52:49 -0500253 }
254
Marek Vasutb2dfd102015-07-20 08:03:11 +0200255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
Marek Vasut1273dd92015-07-12 21:05:08 +0200258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500260}
261
Marek Vasutc76976d2015-07-12 22:28:33 +0200262/**
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
267 *
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
269 */
270static void scc_mgr_set(u32 off, u32 grp, u32 val)
271{
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
273}
274
Marek Vasute893f4d2015-07-20 07:16:42 +0200275/**
276 * scc_mgr_initialize() - Initialize SCC Manager registers
277 *
278 * Initialize SCC Manager registers.
279 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500280static void scc_mgr_initialize(void)
281{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500282 /*
Marek Vasute893f4d2015-07-20 07:16:42 +0200283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500287 */
Marek Vasutc76976d2015-07-12 22:28:33 +0200288 int i;
Marek Vasute893f4d2015-07-20 07:16:42 +0200289
Dinh Nguyen3da42852015-06-02 22:52:49 -0500290 for (i = 0; i < 16; i++) {
Marek Vasut7ac40d22015-06-26 18:56:54 +0200291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -0500292 __func__, __LINE__, i);
Marek Vasutc76976d2015-07-12 22:28:33 +0200293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500294 }
295}
296
Marek Vasut5ff825b2015-07-12 22:11:55 +0200297static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
298{
Marek Vasutc76976d2015-07-12 22:28:33 +0200299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200300}
301
302static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500303{
Marek Vasutc76976d2015-07-12 22:28:33 +0200304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500305}
306
Dinh Nguyen3da42852015-06-02 22:52:49 -0500307static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
308{
Marek Vasutc76976d2015-07-12 22:28:33 +0200309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500310}
311
Marek Vasut5ff825b2015-07-12 22:11:55 +0200312static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
313{
Marek Vasutc76976d2015-07-12 22:28:33 +0200314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200315}
316
Marek Vasut32675242015-07-17 06:07:13 +0200317static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200318{
Marek Vasutc76976d2015-07-12 22:28:33 +0200319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
320 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200321}
322
323static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
324{
Marek Vasutc76976d2015-07-12 22:28:33 +0200325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200326}
327
328static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
329{
Marek Vasutc76976d2015-07-12 22:28:33 +0200330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200331}
332
Marek Vasut32675242015-07-17 06:07:13 +0200333static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200334{
Marek Vasutc76976d2015-07-12 22:28:33 +0200335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
336 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200337}
338
339static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
340{
Marek Vasutc76976d2015-07-12 22:28:33 +0200341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
343 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200344}
345
346/* load up dqs config settings */
347static void scc_mgr_load_dqs(uint32_t dqs)
348{
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
350}
351
352/* load up dqs io config settings */
353static void scc_mgr_load_dqs_io(void)
354{
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
356}
357
358/* load up dq config settings */
359static void scc_mgr_load_dq(uint32_t dq_in_group)
360{
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
362}
363
364/* load up dm config settings */
365static void scc_mgr_load_dm(uint32_t dm)
366{
367 writel(dm, &sdr_scc_mgr->dm_ena);
368}
369
Marek Vasut0b69b802015-07-12 23:25:21 +0200370/**
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
376 *
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
379 */
380static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 const int update)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500382{
Marek Vasut0b69b802015-07-12 23:25:21 +0200383 u32 r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500384
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut0b69b802015-07-12 23:25:21 +0200387 scc_mgr_set(off, grp, val);
Marek Vasut162d60e2015-07-12 23:14:33 +0200388
Marek Vasut0b69b802015-07-12 23:25:21 +0200389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
Marek Vasut1273dd92015-07-12 21:05:08 +0200391 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500392 }
393 }
394}
395
Marek Vasut0b69b802015-07-12 23:25:21 +0200396static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
397{
398 /*
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
404 * once to sr0.
405 */
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
408}
409
Dinh Nguyen3da42852015-06-02 22:52:49 -0500410static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
411 uint32_t phase)
412{
Marek Vasut0b69b802015-07-12 23:25:21 +0200413 /*
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
419 * once to sr0.
420 */
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500423}
424
Dinh Nguyen3da42852015-06-02 22:52:49 -0500425static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
426 uint32_t delay)
427{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500428 /*
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
434 * set to 0.
435 */
Marek Vasut0b69b802015-07-12 23:25:21 +0200436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
Marek Vasut1273dd92015-07-12 21:05:08 +0200438 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500439}
440
Marek Vasut5be355c2015-07-12 23:39:06 +0200441/**
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
445 *
446 * This function sets the OCT output delay in SCC manager.
447 */
448static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500449{
Marek Vasut5be355c2015-07-12 23:39:06 +0200450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
453 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500454 /*
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
460 */
Marek Vasut5be355c2015-07-12 23:39:06 +0200461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500463}
464
Marek Vasut37a37ca2015-07-19 01:32:55 +0200465/**
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
467 *
468 * Load the fixed setting in the SCC manager HHP extras.
469 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500470static void scc_mgr_set_hhp_extras(void)
471{
472 /*
473 * Load the fixed setting in the SCC manager
Marek Vasut37a37ca2015-07-19 01:32:55 +0200474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
Dinh Nguyen3da42852015-06-02 22:52:49 -0500480 */
Marek Vasut37a37ca2015-07-19 01:32:55 +0200481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500486
Marek Vasut37a37ca2015-07-19 01:32:55 +0200487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
488 __func__, __LINE__);
489 writel(value, addr);
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500492}
493
Marek Vasutf42af352015-07-20 04:41:53 +0200494/**
495 * scc_mgr_zero_all() - Zero all DQS config
496 *
497 * Zero all DQS config.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500498 */
499static void scc_mgr_zero_all(void)
500{
Marek Vasutf42af352015-07-20 04:41:53 +0200501 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500502
503 /*
504 * USER Zero all DQS config settings, across all groups and all
505 * shadow registers
506 */
Marek Vasutf42af352015-07-20 04:41:53 +0200507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -0500509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
510 /*
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
514 */
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
518 }
519
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
Marek Vasutf42af352015-07-20 04:41:53 +0200522 /* Arria V/Cyclone V don't have out2. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
524 }
525 }
526
Marek Vasutf42af352015-07-20 04:41:53 +0200527 /* Multicast to all DQS group enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500530}
531
Marek Vasutc5c5f532015-07-17 02:06:20 +0200532/**
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
535 *
536 * Set bypass mode and trigger SCC update.
537 */
538static void scc_set_bypass_mode(const u32 write_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500539{
Marek Vasutc5c5f532015-07-17 02:06:20 +0200540 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500543
Marek Vasutc5c5f532015-07-17 02:06:20 +0200544 /* Update current DQS IO enable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200545 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500546
Marek Vasutc5c5f532015-07-17 02:06:20 +0200547 /* Update the DQS logic. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200548 writel(write_group, &sdr_scc_mgr->dqs_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500549
Marek Vasutc5c5f532015-07-17 02:06:20 +0200550 /* Hit update. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200551 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500552}
553
Marek Vasut5e837892015-07-13 00:30:09 +0200554/**
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
557 *
558 * Load DQS settings for Write Group, do not trigger SCC update.
559 */
560static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200561{
Marek Vasut5e837892015-07-13 00:30:09 +0200562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
565 int i;
Marek Vasut5ff825b2015-07-12 22:11:55 +0200566 /*
Marek Vasut5e837892015-07-13 00:30:09 +0200567 * Load the setting in the SCC manager
Marek Vasut5ff825b2015-07-12 22:11:55 +0200568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
Marek Vasut5e837892015-07-13 00:30:09 +0200571 * the setting must be set multiple times.
Marek Vasut5ff825b2015-07-12 22:11:55 +0200572 */
Marek Vasut5e837892015-07-13 00:30:09 +0200573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200575}
576
Marek Vasutd41ea932015-07-20 08:41:04 +0200577/**
578 * scc_mgr_zero_group() - Zero all configs for a group
579 *
580 * Zero DQ, DM, DQS and OCT configs for a group.
581 */
582static void scc_mgr_zero_group(const u32 write_group, const int out_only)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500583{
Marek Vasutd41ea932015-07-20 08:41:04 +0200584 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500585
Marek Vasutd41ea932015-07-20 08:41:04 +0200586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200590 scc_mgr_set_dq_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500591 if (!out_only)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200592 scc_mgr_set_dq_in_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500593 }
594
Marek Vasutd41ea932015-07-20 08:41:04 +0200595 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200596 writel(0xff, &sdr_scc_mgr->dq_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500597
Marek Vasutd41ea932015-07-20 08:41:04 +0200598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200600 scc_mgr_set_dm_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500601
Marek Vasutd41ea932015-07-20 08:41:04 +0200602 /* Multicast to all DM enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200603 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500604
Marek Vasutd41ea932015-07-20 08:41:04 +0200605 /* Zero all DQS IO settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500606 if (!out_only)
Marek Vasut32675242015-07-17 06:07:13 +0200607 scc_mgr_set_dqs_io_in_delay(0);
Marek Vasutd41ea932015-07-20 08:41:04 +0200608
609 /* Arria V/Cyclone V don't have out2. */
Marek Vasut32675242015-07-17 06:07:13 +0200610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
613
Marek Vasutd41ea932015-07-20 08:41:04 +0200614 /* Multicast to all DQS IO enables (only 1 in total). */
Marek Vasut1273dd92015-07-12 21:05:08 +0200615 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500616
Marek Vasutd41ea932015-07-20 08:41:04 +0200617 /* Hit update to zero everything. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200618 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500619 }
620}
621
Dinh Nguyen3da42852015-06-02 22:52:49 -0500622/*
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
625 */
Marek Vasut32675242015-07-17 06:07:13 +0200626static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500627{
628 uint32_t i, p;
629
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200631 scc_mgr_set_dq_in_delay(p, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500632 scc_mgr_load_dq(p);
633 }
634}
635
Marek Vasut300c2e62015-07-17 05:42:49 +0200636/**
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
639 *
640 * Apply and load a particular output delay for the DQ pins in a group.
641 */
642static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500643{
Marek Vasut300c2e62015-07-17 05:42:49 +0200644 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500645
Marek Vasut300c2e62015-07-17 05:42:49 +0200646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500648 scc_mgr_load_dq(i);
649 }
650}
651
652/* apply and load a particular output delay for the DM pins in a group */
Marek Vasut32675242015-07-17 06:07:13 +0200653static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500654{
655 uint32_t i;
656
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200658 scc_mgr_set_dm_out1_delay(i, delay1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500659 scc_mgr_load_dm(i);
660 }
661}
662
663
664/* apply and load delay on both DQS and OCT out1 */
665static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
666 uint32_t delay)
667{
Marek Vasut32675242015-07-17 06:07:13 +0200668 scc_mgr_set_dqs_out1_delay(delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500669 scc_mgr_load_dqs_io();
670
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
673}
674
Marek Vasut5cb1b502015-07-17 05:33:28 +0200675/**
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
679 *
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
681 */
Marek Vasut8eccde32015-07-17 05:30:14 +0200682static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
Marek Vasut8eccde32015-07-17 05:30:14 +0200683 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500684{
Marek Vasut8eccde32015-07-17 05:30:14 +0200685 u32 i, new_delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500686
Marek Vasut8eccde32015-07-17 05:30:14 +0200687 /* DQ shift */
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500689 scc_mgr_load_dq(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500690
Marek Vasut8eccde32015-07-17 05:30:14 +0200691 /* DM shift */
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500693 scc_mgr_load_dm(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500694
Marek Vasut5cb1b502015-07-17 05:33:28 +0200695 /* DQS shift */
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500702 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500705 }
706
707 scc_mgr_load_dqs_io();
708
Marek Vasut5cb1b502015-07-17 05:33:28 +0200709 /* OCT shift */
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500716 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500719 }
720
721 scc_mgr_load_dqs_for_write_group(write_group);
722}
723
Marek Vasutf51a7d32015-07-19 02:18:21 +0200724/**
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
728 *
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500730 */
Marek Vasutf51a7d32015-07-19 02:18:21 +0200731static void
732scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500734{
Marek Vasutf51a7d32015-07-19 02:18:21 +0200735 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500736
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasutf51a7d32015-07-19 02:18:21 +0200738 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
Marek Vasut1273dd92015-07-12 21:05:08 +0200740 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500741 }
742}
743
Marek Vasutf936f942015-07-26 11:07:19 +0200744/**
745 * set_jump_as_return() - Return instruction optimization
746 *
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
749 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500750static void set_jump_as_return(void)
751{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500752 /*
Marek Vasutf936f942015-07-26 11:07:19 +0200753 * To save space, we replace return with jump to special shared
Dinh Nguyen3da42852015-06-02 22:52:49 -0500754 * RETURN instruction so we set the counter to large value so that
Marek Vasutf936f942015-07-26 11:07:19 +0200755 * we always jump.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500756 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500759}
760
761/*
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
764 */
765static void delay_for_n_mem_clocks(const uint32_t clocks)
766{
767 uint32_t afi_clocks;
768 uint8_t inner = 0;
769 uint8_t outer = 0;
770 uint16_t c_loop = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500771
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
773
774
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
777
778 /*
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
784 */
785 if (afi_clocks == 0) {
786 ;
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
789 outer = 0;
790 c_loop = 0;
791 } else if (afi_clocks <= 0x10000) {
792 inner = 0xff;
793 outer = (afi_clocks-1) >> 8;
794 c_loop = 0;
795 } else {
796 inner = 0xff;
797 outer = 0xff;
798 c_loop = (afi_clocks-1) >> 16;
799 }
800
801 /*
802 * rom instructions are structured as follows:
803 *
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
806 * return
807 *
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
810 *
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
813 *
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
816 * overhead
817 */
818 if (afi_clocks <= 0x100) {
Marek Vasut1273dd92015-07-12 21:05:08 +0200819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500821
Marek Vasut1273dd92015-07-12 21:05:08 +0200822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500824
Marek Vasut1273dd92015-07-12 21:05:08 +0200825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500827 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +0200828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500830
Marek Vasut1273dd92015-07-12 21:05:08 +0200831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500833
Marek Vasut1273dd92015-07-12 21:05:08 +0200834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500836
Marek Vasut1273dd92015-07-12 21:05:08 +0200837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500839
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
Marek Vasut1273dd92015-07-12 21:05:08 +0200843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500845 } else {
846 do {
Marek Vasut1273dd92015-07-12 21:05:08 +0200847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500850 } while (c_loop-- != 0);
851 }
852 }
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
854}
855
Marek Vasut944fe712015-07-13 00:44:30 +0200856/**
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
862 *
863 * Load instruction registers.
864 */
865static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
866{
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
869
870 /* Load counters */
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
877
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
882
883 /* Execute count instruction */
884 writel(jump, grpaddr);
885}
886
Marek Vasutecd23342015-07-13 00:51:05 +0200887/**
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
892 *
893 * Load user calibration values and optionally precharge the banks.
894 */
895static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
896 const int precharge)
897{
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
900 u32 r;
901
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
905 continue;
906 }
907
908 /* set rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
910
911 /* precharge all banks ... */
912 if (precharge)
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
914
915 /*
916 * USER Use Mirror-ed commands for odd ranks if address
917 * mirrorring is on
918 */
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
931 } else {
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
942 }
943
944 if (precharge)
945 continue;
946
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
949
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
952 }
953}
954
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200955/**
956 * rw_mgr_mem_initialize() - Initialize RW Manager
957 *
958 * Initialize RW Manager.
959 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500960static void rw_mgr_mem_initialize(void)
961{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500962 debug("%s:%d\n", __func__, __LINE__);
963
964 /* The reset / cke part of initialization is broadcasted to all ranks */
Marek Vasut1273dd92015-07-12 21:05:08 +0200965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500967
968 /*
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
975 * significant bits
976 */
977
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200978 /* Start with memory RESET activated */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500979
980 /* tINIT = 200us */
981
982 /*
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
989 * b = 6A
990 */
Marek Vasut944fe712015-07-13 00:44:30 +0200991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
992 SEQ_TINIT_CNTR2_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500994
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200995 /* Indicate that memory is stable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500997
998 /*
999 * transition the RESET to high
1000 * Wait for 500us
1001 */
1002
1003 /*
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010 * b = FF
1011 */
Marek Vasut944fe712015-07-13 00:44:30 +02001012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001015
Marek Vasut8e9d7d02015-07-26 10:57:06 +02001016 /* Bring up clock enable. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001017
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1020
Marek Vasutecd23342015-07-13 00:51:05 +02001021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001023}
1024
1025/*
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1028 */
1029static void rw_mgr_mem_handoff(void)
1030{
Marek Vasutecd23342015-07-13 00:51:05 +02001031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032 /*
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1036 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001037}
1038
Marek Vasutd844c7d2015-07-18 03:55:07 +02001039/**
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1044 *
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001047 */
Marek Vasutd844c7d2015-07-18 03:55:07 +02001048static int
1049rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001051{
Marek Vasutd844c7d2015-07-18 03:55:07 +02001052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001062
Marek Vasutd844c7d2015-07-18 03:55:07 +02001063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064 int vg, r;
1065 int ret = 0;
1066
1067 bit_chk = param->read_correct_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001068
1069 for (r = rank_bgn; r < rank_end; r++) {
Marek Vasutd844c7d2015-07-18 03:55:07 +02001070 /* Request to skip the rank */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001071 if (param->skip_ranks[r])
Dinh Nguyen3da42852015-06-02 22:52:49 -05001072 continue;
1073
Marek Vasutd844c7d2015-07-18 03:55:07 +02001074 /* Set rank */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077 /* Load up a constant bursts of read commands */
Marek Vasut1273dd92015-07-12 21:05:08 +02001078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001081
Marek Vasut1273dd92015-07-12 21:05:08 +02001082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001085
1086 tmp_bit_chk = 0;
Marek Vasutd844c7d2015-07-18 03:55:07 +02001087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088 vg >= 0; vg--) {
1089 /* Reset the FIFOs to get pointers to known state. */
Marek Vasut1273dd92015-07-12 21:05:08 +02001090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001095
Marek Vasut1273dd92015-07-12 21:05:08 +02001096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001099 }
Marek Vasutd844c7d2015-07-18 03:55:07 +02001100
1101 bit_chk &= tmp_bit_chk;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001102 }
1103
Marek Vasut17fdc912015-07-12 20:05:54 +02001104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001105
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001107
1108 if (bit_chk != param->read_correct_mask)
1109 ret = -EIO;
1110
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1115
1116 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001117}
1118
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001119/**
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1123 *
1124 * Load up the patterns we are going to use during a read test.
1125 */
1126static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001128{
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132 u32 r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001133
1134 debug("%s:%d\n", __func__, __LINE__);
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001135
Dinh Nguyen3da42852015-06-02 22:52:49 -05001136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1139 continue;
1140
1141 /* set rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144 /* Load up a constant bursts */
Marek Vasut1273dd92015-07-12 21:05:08 +02001145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001146
Marek Vasut1273dd92015-07-12 21:05:08 +02001147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001149
Marek Vasut1273dd92015-07-12 21:05:08 +02001150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001151
Marek Vasut1273dd92015-07-12 21:05:08 +02001152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001154
Marek Vasut1273dd92015-07-12 21:05:08 +02001155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001156
Marek Vasut1273dd92015-07-12 21:05:08 +02001157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001159
Marek Vasut1273dd92015-07-12 21:05:08 +02001160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001161
Marek Vasut1273dd92015-07-12 21:05:08 +02001162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001164
Marek Vasut1273dd92015-07-12 21:05:08 +02001165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001167 }
1168
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170}
1171
Marek Vasut783fcf52015-07-20 03:26:05 +02001172/**
1173 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1174 * @rank_bgn: Rank number
1175 * @group: Read/Write group
1176 * @num_tries: Number of retries of the test
1177 * @all_correct: All bits must be correct in the mask
1178 * @bit_chk: Resulting bit mask after the test
1179 * @all_groups: Test all R/W groups
1180 * @all_ranks: Test all ranks
1181 *
1182 * Try a read and see if it returns correct data back. Test has dummy reads
1183 * inserted into the mix used to align DQS enable. Test has more thorough
1184 * checks than the regular read test.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001185 */
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001186static int
1187rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1188 const u32 num_tries, const u32 all_correct,
1189 u32 *bit_chk,
1190 const u32 all_groups, const u32 all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001191{
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001192 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
Dinh Nguyen3da42852015-06-02 22:52:49 -05001193 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001194 const u32 quick_read_mode =
1195 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1196 ENABLE_SUPER_QUICK_CALIBRATION);
1197 u32 correct_mask_vg = param->read_correct_mask_vg;
1198 u32 tmp_bit_chk;
1199 u32 base_rw_mgr;
1200 u32 addr;
1201
1202 int r, vg, ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001203
1204 *bit_chk = param->read_correct_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001205
1206 for (r = rank_bgn; r < rank_end; r++) {
1207 if (param->skip_ranks[r])
1208 /* request to skip the rank */
1209 continue;
1210
1211 /* set rank */
1212 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1213
Marek Vasut1273dd92015-07-12 21:05:08 +02001214 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001215
Marek Vasut1273dd92015-07-12 21:05:08 +02001216 writel(RW_MGR_READ_B2B_WAIT1,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001218
Marek Vasut1273dd92015-07-12 21:05:08 +02001219 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1220 writel(RW_MGR_READ_B2B_WAIT2,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001222
Dinh Nguyen3da42852015-06-02 22:52:49 -05001223 if (quick_read_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02001224 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001225 /* need at least two (1+1) reads to capture failures */
1226 else if (all_groups)
Marek Vasut1273dd92015-07-12 21:05:08 +02001227 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001228 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001229 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001230
Marek Vasut1273dd92015-07-12 21:05:08 +02001231 writel(RW_MGR_READ_B2B,
1232 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001233 if (all_groups)
1234 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1235 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
Marek Vasut1273dd92015-07-12 21:05:08 +02001236 &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001237 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001238 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001239
Marek Vasut1273dd92015-07-12 21:05:08 +02001240 writel(RW_MGR_READ_B2B,
1241 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001242
1243 tmp_bit_chk = 0;
Marek Vasut7ce23bb2015-07-19 07:51:17 +02001244 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1245 vg--) {
Marek Vasutba522c72015-07-19 07:57:28 +02001246 /* Reset the FIFOs to get pointers to known state. */
Marek Vasut1273dd92015-07-12 21:05:08 +02001247 writel(0, &phy_mgr_cmd->fifo_reset);
1248 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1249 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001250
Marek Vasutba522c72015-07-19 07:57:28 +02001251 if (all_groups) {
1252 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1253 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1254 } else {
1255 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1256 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1257 }
Marek Vasutc4815f72015-07-12 19:03:33 +02001258
Marek Vasut17fdc912015-07-12 20:05:54 +02001259 writel(RW_MGR_READ_B2B, addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05001260 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1261 vg) << 2));
1262
Marek Vasut1273dd92015-07-12 21:05:08 +02001263 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Marek Vasutba522c72015-07-19 07:57:28 +02001264 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1265 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1266 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001267 }
Marek Vasut7ce23bb2015-07-19 07:51:17 +02001268
Dinh Nguyen3da42852015-06-02 22:52:49 -05001269 *bit_chk &= tmp_bit_chk;
1270 }
1271
Marek Vasutc4815f72015-07-12 19:03:33 +02001272 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001273 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001274
Marek Vasut3853d652015-07-19 07:44:21 +02001275 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1276
Dinh Nguyen3da42852015-06-02 22:52:49 -05001277 if (all_correct) {
Marek Vasut3853d652015-07-19 07:44:21 +02001278 ret = (*bit_chk == param->read_correct_mask);
1279 debug_cond(DLEVEL == 2,
1280 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1281 __func__, __LINE__, group, all_groups, *bit_chk,
1282 param->read_correct_mask, ret);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001283 } else {
Marek Vasut3853d652015-07-19 07:44:21 +02001284 ret = (*bit_chk != 0x00);
1285 debug_cond(DLEVEL == 2,
1286 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1287 __func__, __LINE__, group, all_groups, *bit_chk,
1288 0, ret);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001289 }
Marek Vasut3853d652015-07-19 07:44:21 +02001290
1291 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001292}
1293
Marek Vasut96df6032015-07-19 07:35:36 +02001294/**
1295 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1296 * @grp: Read/Write group
1297 * @num_tries: Number of retries of the test
1298 * @all_correct: All bits must be correct in the mask
1299 * @all_groups: Test all R/W groups
1300 *
1301 * Perform a READ test across all memory ranks.
1302 */
1303static int
1304rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1305 const u32 all_correct,
1306 const u32 all_groups)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001307{
Marek Vasut96df6032015-07-19 07:35:36 +02001308 u32 bit_chk;
1309 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1310 &bit_chk, all_groups, 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001311}
1312
Marek Vasut60bb8a82015-07-19 06:25:27 +02001313/**
1314 * rw_mgr_incr_vfifo() - Increase VFIFO value
1315 * @grp: Read/Write group
Marek Vasut60bb8a82015-07-19 06:25:27 +02001316 *
1317 * Increase VFIFO value.
1318 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001319static void rw_mgr_incr_vfifo(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001320{
Marek Vasut1273dd92015-07-12 21:05:08 +02001321 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001322}
1323
Marek Vasut60bb8a82015-07-19 06:25:27 +02001324/**
1325 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1326 * @grp: Read/Write group
Marek Vasut60bb8a82015-07-19 06:25:27 +02001327 *
1328 * Decrease VFIFO value.
1329 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001330static void rw_mgr_decr_vfifo(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001331{
Marek Vasut60bb8a82015-07-19 06:25:27 +02001332 u32 i;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001333
Marek Vasut60bb8a82015-07-19 06:25:27 +02001334 for (i = 0; i < VFIFO_SIZE - 1; i++)
Marek Vasut8c887b62015-07-19 06:37:51 +02001335 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001336}
1337
Marek Vasutd145ca92015-07-19 06:45:43 +02001338/**
1339 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1340 * @grp: Read/Write group
1341 *
1342 * Push VFIFO until a failing read happens.
1343 */
1344static int find_vfifo_failing_read(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001345{
Marek Vasut96df6032015-07-19 07:35:36 +02001346 u32 v, ret, fail_cnt = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001347
Marek Vasut8c887b62015-07-19 06:37:51 +02001348 for (v = 0; v < VFIFO_SIZE; v++) {
Marek Vasutd145ca92015-07-19 06:45:43 +02001349 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001350 __func__, __LINE__, v);
Marek Vasutd145ca92015-07-19 06:45:43 +02001351 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001352 PASS_ONE_BIT, 0);
Marek Vasutd145ca92015-07-19 06:45:43 +02001353 if (!ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05001354 fail_cnt++;
1355
1356 if (fail_cnt == 2)
Marek Vasutd145ca92015-07-19 06:45:43 +02001357 return v;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001358 }
1359
Marek Vasutd145ca92015-07-19 06:45:43 +02001360 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001361 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001362 }
1363
Marek Vasutd145ca92015-07-19 06:45:43 +02001364 /* No failing read found! Something must have gone wrong. */
1365 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1366 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001367}
1368
Marek Vasut192d6f92015-07-19 05:26:49 +02001369/**
Marek Vasut52e8f212015-07-19 07:27:06 +02001370 * sdr_find_phase_delay() - Find DQS enable phase or delay
1371 * @working: If 1, look for working phase/delay, if 0, look for non-working
1372 * @delay: If 1, look for delay, if 0, look for phase
1373 * @grp: Read/Write group
1374 * @work: Working window position
1375 * @work_inc: Working window increment
1376 * @pd: DQS Phase/Delay Iterator
1377 *
1378 * Find working or non-working DQS enable phase setting.
1379 */
1380static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1381 u32 *work, const u32 work_inc, u32 *pd)
1382{
1383 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
Marek Vasut96df6032015-07-19 07:35:36 +02001384 u32 ret;
Marek Vasut52e8f212015-07-19 07:27:06 +02001385
1386 for (; *pd <= max; (*pd)++) {
1387 if (delay)
1388 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1389 else
1390 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1391
1392 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001393 PASS_ONE_BIT, 0);
Marek Vasut52e8f212015-07-19 07:27:06 +02001394 if (!working)
1395 ret = !ret;
1396
1397 if (ret)
1398 return 0;
1399
1400 if (work)
1401 *work += work_inc;
1402 }
1403
1404 return -EINVAL;
1405}
1406/**
Marek Vasut192d6f92015-07-19 05:26:49 +02001407 * sdr_find_phase() - Find DQS enable phase
1408 * @working: If 1, look for working phase, if 0, look for non-working phase
1409 * @grp: Read/Write group
Marek Vasut192d6f92015-07-19 05:26:49 +02001410 * @work: Working window position
1411 * @i: Iterator
1412 * @p: DQS Phase Iterator
Marek Vasut192d6f92015-07-19 05:26:49 +02001413 *
1414 * Find working or non-working DQS enable phase setting.
1415 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001416static int sdr_find_phase(int working, const u32 grp, u32 *work,
Marek Vasut86a39dc2015-07-19 05:35:40 +02001417 u32 *i, u32 *p)
Marek Vasut192d6f92015-07-19 05:26:49 +02001418{
Marek Vasut192d6f92015-07-19 05:26:49 +02001419 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
Marek Vasut52e8f212015-07-19 07:27:06 +02001420 int ret;
Marek Vasut192d6f92015-07-19 05:26:49 +02001421
1422 for (; *i < end; (*i)++) {
1423 if (working)
1424 *p = 0;
1425
Marek Vasut52e8f212015-07-19 07:27:06 +02001426 ret = sdr_find_phase_delay(working, 0, grp, work,
1427 IO_DELAY_PER_OPA_TAP, p);
1428 if (!ret)
1429 return 0;
Marek Vasut192d6f92015-07-19 05:26:49 +02001430
1431 if (*p > IO_DQS_EN_PHASE_MAX) {
1432 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001433 rw_mgr_incr_vfifo(grp);
Marek Vasut192d6f92015-07-19 05:26:49 +02001434 if (!working)
1435 *p = 0;
1436 }
1437 }
1438
1439 return -EINVAL;
1440}
1441
Marek Vasut4c5e5842015-07-19 06:04:00 +02001442/**
1443 * sdr_working_phase() - Find working DQS enable phase
1444 * @grp: Read/Write group
1445 * @work_bgn: Working window start position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001446 * @d: dtaps output value
1447 * @p: DQS Phase Iterator
1448 * @i: Iterator
1449 *
1450 * Find working DQS enable phase setting.
1451 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001452static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
Marek Vasut4c5e5842015-07-19 06:04:00 +02001453 u32 *p, u32 *i)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001454{
Marek Vasut35ee8672015-07-19 05:40:06 +02001455 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1456 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Marek Vasut192d6f92015-07-19 05:26:49 +02001457 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001458
Marek Vasut192d6f92015-07-19 05:26:49 +02001459 *work_bgn = 0;
1460
1461 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1462 *i = 0;
Marek Vasut521fe392015-07-19 04:34:12 +02001463 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
Marek Vasut8c887b62015-07-19 06:37:51 +02001464 ret = sdr_find_phase(1, grp, work_bgn, i, p);
Marek Vasut192d6f92015-07-19 05:26:49 +02001465 if (!ret)
1466 return 0;
1467 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001468 }
1469
Marek Vasut38ed6922015-07-19 05:01:12 +02001470 /* Cannot find working solution */
Marek Vasut192d6f92015-07-19 05:26:49 +02001471 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1472 __func__, __LINE__);
1473 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001474}
1475
Marek Vasut4c5e5842015-07-19 06:04:00 +02001476/**
1477 * sdr_backup_phase() - Find DQS enable backup phase
1478 * @grp: Read/Write group
1479 * @work_bgn: Working window start position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001480 * @p: DQS Phase Iterator
1481 *
1482 * Find DQS enable backup phase setting.
1483 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001484static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001485{
Marek Vasut96df6032015-07-19 07:35:36 +02001486 u32 tmp_delay, d;
Marek Vasut4c5e5842015-07-19 06:04:00 +02001487 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001488
1489 /* Special case code for backing up a phase */
1490 if (*p == 0) {
1491 *p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001492 rw_mgr_decr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001493 } else {
1494 (*p)--;
1495 }
1496 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
Marek Vasut521fe392015-07-19 04:34:12 +02001497 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001498
Marek Vasut49891df62015-07-19 05:48:30 +02001499 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1500 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001501
Marek Vasut4c5e5842015-07-19 06:04:00 +02001502 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001503 PASS_ONE_BIT, 0);
Marek Vasut4c5e5842015-07-19 06:04:00 +02001504 if (ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05001505 *work_bgn = tmp_delay;
1506 break;
1507 }
Marek Vasut49891df62015-07-19 05:48:30 +02001508
1509 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001510 }
1511
Marek Vasut4c5e5842015-07-19 06:04:00 +02001512 /* Restore VFIFO to old state before we decremented it (if needed). */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001513 (*p)++;
1514 if (*p > IO_DQS_EN_PHASE_MAX) {
1515 *p = 0;
Marek Vasut8c887b62015-07-19 06:37:51 +02001516 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001517 }
1518
Marek Vasut521fe392015-07-19 04:34:12 +02001519 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001520}
1521
Marek Vasut4c5e5842015-07-19 06:04:00 +02001522/**
1523 * sdr_nonworking_phase() - Find non-working DQS enable phase
1524 * @grp: Read/Write group
1525 * @work_end: Working window end position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001526 * @p: DQS Phase Iterator
1527 * @i: Iterator
1528 *
1529 * Find non-working DQS enable phase setting.
1530 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001531static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001532{
Marek Vasut192d6f92015-07-19 05:26:49 +02001533 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001534
1535 (*p)++;
1536 *work_end += IO_DELAY_PER_OPA_TAP;
1537 if (*p > IO_DQS_EN_PHASE_MAX) {
Marek Vasut192d6f92015-07-19 05:26:49 +02001538 /* Fiddle with FIFO. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001539 *p = 0;
Marek Vasut8c887b62015-07-19 06:37:51 +02001540 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001541 }
1542
Marek Vasut8c887b62015-07-19 06:37:51 +02001543 ret = sdr_find_phase(0, grp, work_end, i, p);
Marek Vasut192d6f92015-07-19 05:26:49 +02001544 if (ret) {
1545 /* Cannot see edge of failing read. */
1546 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1547 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001548 }
1549
Marek Vasut192d6f92015-07-19 05:26:49 +02001550 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001551}
1552
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001553/**
1554 * sdr_find_window_center() - Find center of the working DQS window.
1555 * @grp: Read/Write group
1556 * @work_bgn: First working settings
1557 * @work_end: Last working settings
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001558 *
1559 * Find center of the working DQS enable window.
1560 */
1561static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
Marek Vasut8c887b62015-07-19 06:37:51 +02001562 const u32 work_end)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001563{
Marek Vasut96df6032015-07-19 07:35:36 +02001564 u32 work_mid;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001565 int tmp_delay = 0;
Marek Vasut28fd2422015-07-19 02:56:59 +02001566 int i, p, d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001567
Marek Vasut28fd2422015-07-19 02:56:59 +02001568 work_mid = (work_bgn + work_end) / 2;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001569
1570 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
Marek Vasut28fd2422015-07-19 02:56:59 +02001571 work_bgn, work_end, work_mid);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001572 /* Get the middle delay to be less than a VFIFO delay */
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001573 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
Marek Vasut28fd2422015-07-19 02:56:59 +02001574
Dinh Nguyen3da42852015-06-02 22:52:49 -05001575 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001576 work_mid %= tmp_delay;
Marek Vasut28fd2422015-07-19 02:56:59 +02001577 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001578
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001579 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1580 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1581 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1582 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001583
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001584 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1585
1586 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1587 if (d > IO_DQS_EN_DELAY_MAX)
1588 d = IO_DQS_EN_DELAY_MAX;
1589 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1590
Marek Vasut28fd2422015-07-19 02:56:59 +02001591 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1592
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001593 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
Marek Vasut28fd2422015-07-19 02:56:59 +02001594 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001595
1596 /*
1597 * push vfifo until we can successfully calibrate. We can do this
1598 * because the largest possible margin in 1 VFIFO cycle.
1599 */
1600 for (i = 0; i < VFIFO_SIZE; i++) {
Marek Vasut8c887b62015-07-19 06:37:51 +02001601 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
Marek Vasut28fd2422015-07-19 02:56:59 +02001602 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Dinh Nguyen3da42852015-06-02 22:52:49 -05001603 PASS_ONE_BIT,
Marek Vasut96df6032015-07-19 07:35:36 +02001604 0)) {
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001605 debug_cond(DLEVEL == 2,
Marek Vasut8c887b62015-07-19 06:37:51 +02001606 "%s:%d center: found: ptap=%u dtap=%u\n",
1607 __func__, __LINE__, p, d);
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001608 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001609 }
1610
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001611 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001612 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001613 }
1614
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001615 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1616 __func__, __LINE__);
1617 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001618}
1619
Marek Vasut33756892015-07-20 09:11:09 +02001620/**
1621 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1622 * @grp: Read/Write Group
1623 *
1624 * Find a good DQS enable to use.
1625 */
Marek Vasut914546e2015-07-20 09:20:42 +02001626static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001627{
Marek Vasut57355402015-07-20 09:20:20 +02001628 u32 d, p, i;
1629 u32 dtaps_per_ptap;
1630 u32 work_bgn, work_end;
1631 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1632 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001633
1634 debug("%s:%d %u\n", __func__, __LINE__, grp);
1635
1636 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1637
1638 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1639 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1640
Marek Vasut2f3589c2015-07-19 02:42:21 +02001641 /* Step 0: Determine number of delay taps for each phase tap. */
1642 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001643
Marek Vasut2f3589c2015-07-19 02:42:21 +02001644 /* Step 1: First push vfifo until we get a failing read. */
Marek Vasutd145ca92015-07-19 06:45:43 +02001645 find_vfifo_failing_read(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001646
Marek Vasut2f3589c2015-07-19 02:42:21 +02001647 /* Step 2: Find first working phase, increment in ptaps. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001648 work_bgn = 0;
Marek Vasut914546e2015-07-20 09:20:42 +02001649 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1650 if (ret)
1651 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001652
1653 work_end = work_bgn;
1654
1655 /*
Marek Vasut2f3589c2015-07-19 02:42:21 +02001656 * If d is 0 then the working window covers a phase tap and we can
1657 * follow the old procedure. Otherwise, we've found the beginning
Dinh Nguyen3da42852015-06-02 22:52:49 -05001658 * and we need to increment the dtaps until we find the end.
1659 */
1660 if (d == 0) {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001661 /*
1662 * Step 3a: If we have room, back off by one and
1663 * increment in dtaps.
1664 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001665 sdr_backup_phase(grp, &work_bgn, &p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001666
Marek Vasut2f3589c2015-07-19 02:42:21 +02001667 /*
1668 * Step 4a: go forward from working phase to non working
1669 * phase, increment in ptaps.
1670 */
Marek Vasut914546e2015-07-20 09:20:42 +02001671 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1672 if (ret)
1673 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001674
Marek Vasut2f3589c2015-07-19 02:42:21 +02001675 /* Step 5a: Back off one from last, increment in dtaps. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001676
1677 /* Special case code for backing up a phase */
1678 if (p == 0) {
1679 p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001680 rw_mgr_decr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001681 } else {
1682 p = p - 1;
1683 }
1684
1685 work_end -= IO_DELAY_PER_OPA_TAP;
1686 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1687
Dinh Nguyen3da42852015-06-02 22:52:49 -05001688 d = 0;
1689
Marek Vasut2f3589c2015-07-19 02:42:21 +02001690 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1691 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001692 }
1693
Marek Vasut2f3589c2015-07-19 02:42:21 +02001694 /* The dtap increment to find the failing edge is done here. */
Marek Vasut52e8f212015-07-19 07:27:06 +02001695 sdr_find_phase_delay(0, 1, grp, &work_end,
1696 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001697
1698 /* Go back to working dtap */
1699 if (d != 0)
1700 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1701
Marek Vasut2f3589c2015-07-19 02:42:21 +02001702 debug_cond(DLEVEL == 2,
1703 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1704 __func__, __LINE__, p, d - 1, work_end);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001705
1706 if (work_end < work_bgn) {
1707 /* nil range */
Marek Vasut2f3589c2015-07-19 02:42:21 +02001708 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1709 __func__, __LINE__);
Marek Vasut914546e2015-07-20 09:20:42 +02001710 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001711 }
1712
Marek Vasut2f3589c2015-07-19 02:42:21 +02001713 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001714 __func__, __LINE__, work_bgn, work_end);
1715
Dinh Nguyen3da42852015-06-02 22:52:49 -05001716 /*
Marek Vasut2f3589c2015-07-19 02:42:21 +02001717 * We need to calculate the number of dtaps that equal a ptap.
1718 * To do that we'll back up a ptap and re-find the edge of the
1719 * window using dtaps
Dinh Nguyen3da42852015-06-02 22:52:49 -05001720 */
Marek Vasut2f3589c2015-07-19 02:42:21 +02001721 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1722 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001723
1724 /* Special case code for backing up a phase */
1725 if (p == 0) {
1726 p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001727 rw_mgr_decr_vfifo(grp);
Marek Vasut2f3589c2015-07-19 02:42:21 +02001728 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1729 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001730 } else {
1731 p = p - 1;
Marek Vasut2f3589c2015-07-19 02:42:21 +02001732 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1733 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001734 }
1735
1736 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1737
1738 /*
1739 * Increase dtap until we first see a passing read (in case the
Marek Vasut2f3589c2015-07-19 02:42:21 +02001740 * window is smaller than a ptap), and then a failing read to
1741 * mark the edge of the window again.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001742 */
1743
Marek Vasut2f3589c2015-07-19 02:42:21 +02001744 /* Find a passing read. */
1745 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001746 __func__, __LINE__);
Marek Vasut52e8f212015-07-19 07:27:06 +02001747
Dinh Nguyen3da42852015-06-02 22:52:49 -05001748 initial_failing_dtap = d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001749
Marek Vasut52e8f212015-07-19 07:27:06 +02001750 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001751 if (found_passing_read) {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001752 /* Find a failing read. */
1753 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1754 __func__, __LINE__);
Marek Vasut52e8f212015-07-19 07:27:06 +02001755 d++;
1756 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1757 &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001758 } else {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001759 debug_cond(DLEVEL == 1,
1760 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1761 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001762 }
1763
1764 /*
1765 * The dynamically calculated dtaps_per_ptap is only valid if we
1766 * found a passing/failing read. If we didn't, it means d hit the max
1767 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1768 * statically calculated value.
1769 */
1770 if (found_passing_read && found_failing_read)
1771 dtaps_per_ptap = d - initial_failing_dtap;
1772
Marek Vasut1273dd92015-07-12 21:05:08 +02001773 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
Marek Vasut2f3589c2015-07-19 02:42:21 +02001774 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1775 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001776
Marek Vasut2f3589c2015-07-19 02:42:21 +02001777 /* Step 6: Find the centre of the window. */
Marek Vasut914546e2015-07-20 09:20:42 +02001778 ret = sdr_find_window_center(grp, work_bgn, work_end);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001779
Marek Vasut914546e2015-07-20 09:20:42 +02001780 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001781}
1782
Marek Vasutc4907892015-07-13 02:11:02 +02001783/**
Marek Vasut901dc362015-07-13 02:48:34 +02001784 * search_stop_check() - Check if the detected edge is valid
1785 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1786 * @d: DQS delay
1787 * @rank_bgn: Rank number
1788 * @write_group: Write Group
1789 * @read_group: Read Group
1790 * @bit_chk: Resulting bit mask after the test
1791 * @sticky_bit_chk: Resulting sticky bit mask after the test
1792 * @use_read_test: Perform read test
1793 *
1794 * Test if the found edge is valid.
1795 */
1796static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1797 const u32 write_group, const u32 read_group,
1798 u32 *bit_chk, u32 *sticky_bit_chk,
1799 const u32 use_read_test)
1800{
1801 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
1802 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
1803 const u32 correct_mask = write ? param->write_correct_mask :
1804 param->read_correct_mask;
1805 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1806 RW_MGR_MEM_DQ_PER_READ_DQS;
1807 u32 ret;
1808 /*
1809 * Stop searching when the read test doesn't pass AND when
1810 * we've seen a passing read on every bit.
1811 */
1812 if (write) { /* WRITE-ONLY */
1813 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1814 0, PASS_ONE_BIT,
1815 bit_chk, 0);
1816 } else if (use_read_test) { /* READ-ONLY */
1817 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
1818 NUM_READ_PB_TESTS,
1819 PASS_ONE_BIT, bit_chk,
1820 0, 0);
1821 } else { /* READ-ONLY */
1822 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
1823 PASS_ONE_BIT, bit_chk, 0);
1824 *bit_chk = *bit_chk >> (per_dqs *
1825 (read_group - (write_group * ratio)));
1826 ret = (*bit_chk == 0);
1827 }
1828 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
1829 ret = ret && (*sticky_bit_chk == correct_mask);
1830 debug_cond(DLEVEL == 2,
1831 "%s:%d center(left): dtap=%u => %u == %u && %u",
1832 __func__, __LINE__, d,
1833 *sticky_bit_chk, correct_mask, ret);
1834 return ret;
1835}
1836
1837/**
Marek Vasut71120772015-07-13 02:38:15 +02001838 * search_left_edge() - Find left edge of DQ/DQS working phase
1839 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1840 * @rank_bgn: Rank number
1841 * @write_group: Write Group
1842 * @read_group: Read Group
1843 * @test_bgn: Rank number to begin the test
1844 * @bit_chk: Resulting bit mask after the test
1845 * @sticky_bit_chk: Resulting sticky bit mask after the test
1846 * @left_edge: Left edge of the DQ/DQS phase
1847 * @right_edge: Right edge of the DQ/DQS phase
1848 * @use_read_test: Perform read test
1849 *
1850 * Find left edge of DQ/DQS working phase.
1851 */
1852static void search_left_edge(const int write, const int rank_bgn,
1853 const u32 write_group, const u32 read_group, const u32 test_bgn,
1854 u32 *bit_chk, u32 *sticky_bit_chk,
1855 int *left_edge, int *right_edge, const u32 use_read_test)
1856{
Marek Vasut71120772015-07-13 02:38:15 +02001857 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1858 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1859 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1860 RW_MGR_MEM_DQ_PER_READ_DQS;
1861 u32 stop;
1862 int i, d;
1863
1864 for (d = 0; d <= dqs_max; d++) {
1865 if (write)
1866 scc_mgr_apply_group_dq_out1_delay(d);
1867 else
1868 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
1869
1870 writel(0, &sdr_scc_mgr->update);
1871
Marek Vasut901dc362015-07-13 02:48:34 +02001872 stop = search_stop_check(write, d, rank_bgn, write_group,
1873 read_group, bit_chk, sticky_bit_chk,
1874 use_read_test);
Marek Vasut71120772015-07-13 02:38:15 +02001875 if (stop == 1)
1876 break;
1877
1878 /* stop != 1 */
1879 for (i = 0; i < per_dqs; i++) {
1880 if (*bit_chk & 1) {
1881 /*
1882 * Remember a passing test as
1883 * the left_edge.
1884 */
1885 left_edge[i] = d;
1886 } else {
1887 /*
1888 * If a left edge has not been seen
1889 * yet, then a future passing test
1890 * will mark this edge as the right
1891 * edge.
1892 */
1893 if (left_edge[i] == delay_max + 1)
1894 right_edge[i] = -(d + 1);
1895 }
1896 *bit_chk = *bit_chk >> 1;
1897 }
1898 }
1899
1900 /* Reset DQ delay chains to 0 */
1901 if (write)
1902 scc_mgr_apply_group_dq_out1_delay(0);
1903 else
1904 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1905
1906 *sticky_bit_chk = 0;
1907 for (i = per_dqs - 1; i >= 0; i--) {
1908 debug_cond(DLEVEL == 2,
1909 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
1910 __func__, __LINE__, i, left_edge[i],
1911 i, right_edge[i]);
1912
1913 /*
1914 * Check for cases where we haven't found the left edge,
1915 * which makes our assignment of the the right edge invalid.
1916 * Reset it to the illegal value.
1917 */
1918 if ((left_edge[i] == delay_max + 1) &&
1919 (right_edge[i] != delay_max + 1)) {
1920 right_edge[i] = delay_max + 1;
1921 debug_cond(DLEVEL == 2,
1922 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
1923 __func__, __LINE__, i, right_edge[i]);
1924 }
1925
1926 /*
1927 * Reset sticky bit
1928 * READ: except for bits where we have seen both
1929 * the left and right edge.
1930 * WRITE: except for bits where we have seen the
1931 * left edge.
1932 */
1933 *sticky_bit_chk <<= 1;
1934 if (write) {
1935 if (left_edge[i] != delay_max + 1)
1936 *sticky_bit_chk |= 1;
1937 } else {
1938 if ((left_edge[i] != delay_max + 1) &&
1939 (right_edge[i] != delay_max + 1))
1940 *sticky_bit_chk |= 1;
1941 }
1942 }
1943
1944
1945}
1946
1947/**
Marek Vasutc4907892015-07-13 02:11:02 +02001948 * search_right_edge() - Find right edge of DQ/DQS working phase
1949 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1950 * @rank_bgn: Rank number
1951 * @write_group: Write Group
1952 * @read_group: Read Group
1953 * @start_dqs: DQS start phase
1954 * @start_dqs_en: DQS enable start phase
1955 * @bit_chk: Resulting bit mask after the test
1956 * @sticky_bit_chk: Resulting sticky bit mask after the test
1957 * @left_edge: Left edge of the DQ/DQS phase
1958 * @right_edge: Right edge of the DQ/DQS phase
1959 * @use_read_test: Perform read test
1960 *
1961 * Find right edge of DQ/DQS working phase.
1962 */
1963static int search_right_edge(const int write, const int rank_bgn,
1964 const u32 write_group, const u32 read_group,
1965 const int start_dqs, const int start_dqs_en,
1966 u32 *bit_chk, u32 *sticky_bit_chk,
1967 int *left_edge, int *right_edge, const u32 use_read_test)
1968{
Marek Vasutc4907892015-07-13 02:11:02 +02001969 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1970 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1971 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1972 RW_MGR_MEM_DQ_PER_READ_DQS;
1973 u32 stop;
1974 int i, d;
1975
1976 for (d = 0; d <= dqs_max - start_dqs; d++) {
1977 if (write) { /* WRITE-ONLY */
1978 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
1979 d + start_dqs);
1980 } else { /* READ-ONLY */
1981 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1982 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1983 uint32_t delay = d + start_dqs_en;
1984 if (delay > IO_DQS_EN_DELAY_MAX)
1985 delay = IO_DQS_EN_DELAY_MAX;
1986 scc_mgr_set_dqs_en_delay(read_group, delay);
1987 }
1988 scc_mgr_load_dqs(read_group);
1989 }
1990
1991 writel(0, &sdr_scc_mgr->update);
1992
Marek Vasut901dc362015-07-13 02:48:34 +02001993 stop = search_stop_check(write, d, rank_bgn, write_group,
1994 read_group, bit_chk, sticky_bit_chk,
1995 use_read_test);
Marek Vasutc4907892015-07-13 02:11:02 +02001996 if (stop == 1) {
1997 if (write && (d == 0)) { /* WRITE-ONLY */
1998 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
1999 /*
2000 * d = 0 failed, but it passed when
2001 * testing the left edge, so it must be
2002 * marginal, set it to -1
2003 */
2004 if (right_edge[i] == delay_max + 1 &&
2005 left_edge[i] != delay_max + 1)
2006 right_edge[i] = -1;
2007 }
2008 }
2009 break;
2010 }
2011
2012 /* stop != 1 */
2013 for (i = 0; i < per_dqs; i++) {
2014 if (*bit_chk & 1) {
2015 /*
2016 * Remember a passing test as
2017 * the right_edge.
2018 */
2019 right_edge[i] = d;
2020 } else {
2021 if (d != 0) {
2022 /*
2023 * If a right edge has not
2024 * been seen yet, then a future
2025 * passing test will mark this
2026 * edge as the left edge.
2027 */
2028 if (right_edge[i] == delay_max + 1)
2029 left_edge[i] = -(d + 1);
2030 } else {
2031 /*
2032 * d = 0 failed, but it passed
2033 * when testing the left edge,
2034 * so it must be marginal, set
2035 * it to -1
2036 */
2037 if (right_edge[i] == delay_max + 1 &&
2038 left_edge[i] != delay_max + 1)
2039 right_edge[i] = -1;
2040 /*
2041 * If a right edge has not been
2042 * seen yet, then a future
2043 * passing test will mark this
2044 * edge as the left edge.
2045 */
2046 else if (right_edge[i] == delay_max + 1)
2047 left_edge[i] = -(d + 1);
2048 }
2049 }
2050
2051 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2052 __func__, __LINE__, d);
2053 debug_cond(DLEVEL == 2,
2054 "bit_chk_test=%i left_edge[%u]: %d ",
2055 *bit_chk & 1, i, left_edge[i]);
2056 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2057 right_edge[i]);
2058 *bit_chk = *bit_chk >> 1;
2059 }
2060 }
2061
2062 /* Check that all bits have a window */
2063 for (i = 0; i < per_dqs; i++) {
2064 debug_cond(DLEVEL == 2,
2065 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2066 __func__, __LINE__, i, left_edge[i],
2067 i, right_edge[i]);
2068 if ((left_edge[i] == dqs_max + 1) ||
2069 (right_edge[i] == dqs_max + 1))
2070 return i + 1; /* FIXME: If we fail, retval > 0 */
2071 }
2072
2073 return 0;
2074}
2075
Dinh Nguyen3da42852015-06-02 22:52:49 -05002076/* per-bit deskew DQ and center */
2077static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
2078 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
2079 uint32_t use_read_test, uint32_t update_fom)
2080{
Marek Vasutf0712c32015-07-18 08:01:45 +02002081 uint32_t p, min_index;
2082 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002083 /*
2084 * Store these as signed since there are comparisons with
2085 * signed numbers.
2086 */
2087 uint32_t bit_chk;
2088 uint32_t sticky_bit_chk;
2089 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2090 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2091 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
2092 int32_t mid;
2093 int32_t orig_mid_min, mid_min;
2094 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
2095 final_dqs_en;
2096 int32_t dq_margin, dqs_margin;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002097 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
2098 uint32_t addr;
Marek Vasutc4907892015-07-13 02:11:02 +02002099 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002100
2101 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
2102
Marek Vasutc4815f72015-07-12 19:03:33 +02002103 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002104 start_dqs = readl(addr + (read_group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002105 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
Marek Vasut17fdc912015-07-12 20:05:54 +02002106 start_dqs_en = readl(addr + ((read_group << 2)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002107 - IO_DQS_EN_DELAY_OFFSET));
2108
2109 /* set the left and right edge of each bit to an illegal value */
2110 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2111 sticky_bit_chk = 0;
2112 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2113 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2114 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2115 }
2116
Dinh Nguyen3da42852015-06-02 22:52:49 -05002117 /* Search for the left edge of the window for each bit */
Marek Vasut71120772015-07-13 02:38:15 +02002118 search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
2119 &bit_chk, &sticky_bit_chk,
2120 left_edge, right_edge, use_read_test);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002121
Marek Vasutf0712c32015-07-18 08:01:45 +02002122
Dinh Nguyen3da42852015-06-02 22:52:49 -05002123 /* Search for the right edge of the window for each bit */
Marek Vasutc4907892015-07-13 02:11:02 +02002124 ret = search_right_edge(0, rank_bgn, write_group, read_group,
2125 start_dqs, start_dqs_en,
2126 &bit_chk, &sticky_bit_chk,
2127 left_edge, right_edge, use_read_test);
2128 if (ret) {
2129 /*
2130 * Restore delay chain settings before letting the loop
2131 * in rw_mgr_mem_calibrate_vfifo to retry different
2132 * dqs/ck relationships.
2133 */
2134 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2135 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2136 scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002137
Marek Vasutc4907892015-07-13 02:11:02 +02002138 scc_mgr_load_dqs(read_group);
Marek Vasut1273dd92015-07-12 21:05:08 +02002139 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002140
Marek Vasutc4907892015-07-13 02:11:02 +02002141 debug_cond(DLEVEL == 1,
2142 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2143 __func__, __LINE__, i, left_edge[i], right_edge[i]);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002144 if (use_read_test) {
Marek Vasutc4907892015-07-13 02:11:02 +02002145 set_failing_group_stage(read_group *
2146 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2147 CAL_STAGE_VFIFO,
2148 CAL_SUBSTAGE_VFIFO_CENTER);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002149 } else {
Marek Vasutc4907892015-07-13 02:11:02 +02002150 set_failing_group_stage(read_group *
2151 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2152 CAL_STAGE_VFIFO_AFTER_WRITES,
2153 CAL_SUBSTAGE_VFIFO_CENTER);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002154 }
Marek Vasutc4907892015-07-13 02:11:02 +02002155 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002156 }
2157
2158 /* Find middle of window for each DQ bit */
2159 mid_min = left_edge[0] - right_edge[0];
2160 min_index = 0;
2161 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2162 mid = left_edge[i] - right_edge[i];
2163 if (mid < mid_min) {
2164 mid_min = mid;
2165 min_index = i;
2166 }
2167 }
2168
2169 /*
2170 * -mid_min/2 represents the amount that we need to move DQS.
2171 * If mid_min is odd and positive we'll need to add one to
2172 * make sure the rounding in further calculations is correct
2173 * (always bias to the right), so just add 1 for all positive values.
2174 */
2175 if (mid_min > 0)
2176 mid_min++;
2177
2178 mid_min = mid_min / 2;
2179
2180 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2181 __func__, __LINE__, mid_min, min_index);
2182
2183 /* Determine the amount we can change DQS (which is -mid_min) */
2184 orig_mid_min = mid_min;
2185 new_dqs = start_dqs - mid_min;
2186 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2187 new_dqs = IO_DQS_IN_DELAY_MAX;
2188 else if (new_dqs < 0)
2189 new_dqs = 0;
2190
2191 mid_min = start_dqs - new_dqs;
2192 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2193 mid_min, new_dqs);
2194
2195 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2196 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2197 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2198 else if (start_dqs_en - mid_min < 0)
2199 mid_min += start_dqs_en - mid_min;
2200 }
2201 new_dqs = start_dqs - mid_min;
2202
Marek Vasutf0712c32015-07-18 08:01:45 +02002203 debug_cond(DLEVEL == 1,
2204 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2205 start_dqs,
Dinh Nguyen3da42852015-06-02 22:52:49 -05002206 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2207 new_dqs, mid_min);
2208
2209 /* Initialize data for export structures */
2210 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2211 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2212
Dinh Nguyen3da42852015-06-02 22:52:49 -05002213 /* add delay to bring centre of all DQ windows to the same "level" */
2214 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2215 /* Use values before divide by 2 to reduce round off error */
2216 shift_dq = (left_edge[i] - right_edge[i] -
2217 (left_edge[min_index] - right_edge[min_index]))/2 +
2218 (orig_mid_min - mid_min);
2219
Marek Vasutf0712c32015-07-18 08:01:45 +02002220 debug_cond(DLEVEL == 2,
2221 "vfifo_center: before: shift_dq[%u]=%d\n",
2222 i, shift_dq);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002223
Marek Vasut1273dd92015-07-12 21:05:08 +02002224 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002225 temp_dq_in_delay1 = readl(addr + (p << 2));
2226 temp_dq_in_delay2 = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002227
Marek Vasutf0712c32015-07-18 08:01:45 +02002228 if (shift_dq + temp_dq_in_delay1 > IO_IO_IN_DELAY_MAX)
2229 shift_dq = IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2230 else if (shift_dq + temp_dq_in_delay1 < 0)
2231 shift_dq = -temp_dq_in_delay1;
2232
2233 debug_cond(DLEVEL == 2,
2234 "vfifo_center: after: shift_dq[%u]=%d\n",
2235 i, shift_dq);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002236 final_dq[i] = temp_dq_in_delay1 + shift_dq;
Marek Vasut07aee5b2015-07-12 22:07:33 +02002237 scc_mgr_set_dq_in_delay(p, final_dq[i]);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002238 scc_mgr_load_dq(p);
2239
Marek Vasutf0712c32015-07-18 08:01:45 +02002240 debug_cond(DLEVEL == 2,
2241 "vfifo_center: margin[%u]=[%d,%d]\n", i,
Dinh Nguyen3da42852015-06-02 22:52:49 -05002242 left_edge[i] - shift_dq + (-mid_min),
2243 right_edge[i] + shift_dq - (-mid_min));
Marek Vasutf0712c32015-07-18 08:01:45 +02002244
Dinh Nguyen3da42852015-06-02 22:52:49 -05002245 /* To determine values for export structures */
2246 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2247 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2248
2249 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2250 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2251 }
2252
2253 final_dqs = new_dqs;
2254 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2255 final_dqs_en = start_dqs_en - mid_min;
2256
2257 /* Move DQS-en */
2258 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2259 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2260 scc_mgr_load_dqs(read_group);
2261 }
2262
2263 /* Move DQS */
2264 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2265 scc_mgr_load_dqs(read_group);
Marek Vasutf0712c32015-07-18 08:01:45 +02002266 debug_cond(DLEVEL == 2,
2267 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2268 __func__, __LINE__, dq_margin, dqs_margin);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002269
2270 /*
2271 * Do not remove this line as it makes sure all of our decisions
2272 * have been applied. Apply the update bit.
2273 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002274 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002275
2276 return (dq_margin >= 0) && (dqs_margin >= 0);
2277}
2278
Marek Vasutbce24ef2015-07-17 03:16:45 +02002279/**
Marek Vasut04372fb2015-07-18 02:46:56 +02002280 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2281 * @rw_group: Read/Write Group
2282 * @phase: DQ/DQS phase
2283 *
2284 * Because initially no communication ca be reliably performed with the memory
2285 * device, the sequencer uses a guaranteed write mechanism to write data into
2286 * the memory device.
2287 */
2288static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2289 const u32 phase)
2290{
Marek Vasut04372fb2015-07-18 02:46:56 +02002291 int ret;
2292
2293 /* Set a particular DQ/DQS phase. */
2294 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2295
2296 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2297 __func__, __LINE__, rw_group, phase);
2298
2299 /*
2300 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2301 * Load up the patterns used by read calibration using the
2302 * current DQDQS phase.
2303 */
2304 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2305
2306 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2307 return 0;
2308
2309 /*
2310 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2311 * Back-to-Back reads of the patterns used for calibration.
2312 */
Marek Vasutd844c7d2015-07-18 03:55:07 +02002313 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2314 if (ret)
Marek Vasut04372fb2015-07-18 02:46:56 +02002315 debug_cond(DLEVEL == 1,
2316 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2317 __func__, __LINE__, rw_group, phase);
Marek Vasutd844c7d2015-07-18 03:55:07 +02002318 return ret;
Marek Vasut04372fb2015-07-18 02:46:56 +02002319}
2320
2321/**
Marek Vasutf09da112015-07-18 02:57:32 +02002322 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2323 * @rw_group: Read/Write Group
2324 * @test_bgn: Rank at which the test begins
2325 *
2326 * DQS enable calibration ensures reliable capture of the DQ signal without
2327 * glitches on the DQS line.
2328 */
2329static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2330 const u32 test_bgn)
2331{
Marek Vasutf09da112015-07-18 02:57:32 +02002332 /*
2333 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2334 * DQS and DQS Eanble Signal Relationships.
2335 */
Marek Vasut28ea8272015-07-18 04:28:42 +02002336
2337 /* We start at zero, so have one less dq to devide among */
2338 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2339 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
Marek Vasut914546e2015-07-20 09:20:42 +02002340 int ret;
Marek Vasut28ea8272015-07-18 04:28:42 +02002341 u32 i, p, d, r;
2342
2343 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2344
2345 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2346 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2347 r += NUM_RANKS_PER_SHADOW_REG) {
2348 for (i = 0, p = test_bgn, d = 0;
2349 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2350 i++, p++, d += delay_step) {
2351 debug_cond(DLEVEL == 1,
2352 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2353 __func__, __LINE__, rw_group, r, i, p, d);
2354
2355 scc_mgr_set_dq_in_delay(p, d);
2356 scc_mgr_load_dq(p);
2357 }
2358
2359 writel(0, &sdr_scc_mgr->update);
2360 }
2361
2362 /*
2363 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2364 * dq_in_delay values
2365 */
Marek Vasut914546e2015-07-20 09:20:42 +02002366 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
Marek Vasut28ea8272015-07-18 04:28:42 +02002367
2368 debug_cond(DLEVEL == 1,
2369 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
Marek Vasut914546e2015-07-20 09:20:42 +02002370 __func__, __LINE__, rw_group, !ret);
Marek Vasut28ea8272015-07-18 04:28:42 +02002371
2372 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2373 r += NUM_RANKS_PER_SHADOW_REG) {
2374 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2375 writel(0, &sdr_scc_mgr->update);
2376 }
2377
Marek Vasut914546e2015-07-20 09:20:42 +02002378 return ret;
Marek Vasutf09da112015-07-18 02:57:32 +02002379}
2380
2381/**
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002382 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2383 * @rw_group: Read/Write Group
2384 * @test_bgn: Rank at which the test begins
2385 * @use_read_test: Perform a read test
2386 * @update_fom: Update FOM
2387 *
2388 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2389 * within a group.
2390 */
2391static int
2392rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2393 const int use_read_test,
2394 const int update_fom)
2395
2396{
2397 int ret, grp_calibrated;
2398 u32 rank_bgn, sr;
2399
2400 /*
2401 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2402 * Read per-bit deskew can be done on a per shadow register basis.
2403 */
2404 grp_calibrated = 1;
2405 for (rank_bgn = 0, sr = 0;
2406 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2407 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2408 /* Check if this set of ranks should be skipped entirely. */
2409 if (param->skip_shadow_regs[sr])
2410 continue;
2411
2412 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2413 rw_group, test_bgn,
2414 use_read_test,
2415 update_fom);
2416 if (ret)
2417 continue;
2418
2419 grp_calibrated = 0;
2420 }
2421
2422 if (!grp_calibrated)
2423 return -EIO;
2424
2425 return 0;
2426}
2427
2428/**
Marek Vasutbce24ef2015-07-17 03:16:45 +02002429 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2430 * @rw_group: Read/Write Group
2431 * @test_bgn: Rank at which the test begins
Dinh Nguyen3da42852015-06-02 22:52:49 -05002432 *
Marek Vasutbce24ef2015-07-17 03:16:45 +02002433 * Stage 1: Calibrate the read valid prediction FIFO.
2434 *
2435 * This function implements UniPHY calibration Stage 1, as explained in
2436 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2437 *
2438 * - read valid prediction will consist of finding:
2439 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2440 * - DQS input phase and DQS input delay (DQ/DQS Centering)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002441 * - we also do a per-bit deskew on the DQ lines.
2442 */
Marek Vasutc336ca32015-07-17 04:24:18 +02002443static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002444{
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002445 uint32_t p, d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002446 uint32_t dtaps_per_ptap;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002447 uint32_t failed_substage;
2448
Marek Vasut04372fb2015-07-18 02:46:56 +02002449 int ret;
2450
Marek Vasutc336ca32015-07-17 04:24:18 +02002451 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002452
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002453 /* Update info for sims */
2454 reg_file_set_group(rw_group);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002455 reg_file_set_stage(CAL_STAGE_VFIFO);
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002456 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002457
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002458 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2459
2460 /* USER Determine number of delay taps for each phase tap. */
Marek Vasutd32badb2015-07-17 03:11:06 +02002461 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2462 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002463
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002464 for (d = 0; d <= dtaps_per_ptap; d += 2) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002465 /*
2466 * In RLDRAMX we may be messing the delay of pins in
Marek Vasutc336ca32015-07-17 04:24:18 +02002467 * the same write rw_group but outside of the current read
2468 * the rw_group, but that's ok because we haven't calibrated
Marek Vasutac70d2f2015-07-17 03:44:26 +02002469 * output side yet.
Dinh Nguyen3da42852015-06-02 22:52:49 -05002470 */
2471 if (d > 0) {
Marek Vasutf51a7d32015-07-19 02:18:21 +02002472 scc_mgr_apply_group_all_out_delay_add_all_ranks(
Marek Vasutc336ca32015-07-17 04:24:18 +02002473 rw_group, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002474 }
2475
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002476 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
Marek Vasut04372fb2015-07-18 02:46:56 +02002477 /* 1) Guaranteed Write */
2478 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2479 if (ret)
2480 break;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002481
Marek Vasutf09da112015-07-18 02:57:32 +02002482 /* 2) DQS Enable Calibration */
2483 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2484 test_bgn);
2485 if (ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002486 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002487 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002488 }
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002489
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002490 /* 3) Centering DQ/DQS */
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002491 /*
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002492 * If doing read after write calibration, do not update
2493 * FOM now. Do it then.
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002494 */
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002495 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2496 test_bgn, 1, 0);
2497 if (ret) {
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002498 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002499 continue;
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002500 }
2501
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002502 /* All done. */
2503 goto cal_done_ok;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002504 }
2505 }
2506
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002507 /* Calibration Stage 1 failed. */
Marek Vasutc336ca32015-07-17 04:24:18 +02002508 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002509 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002510
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002511 /* Calibration Stage 1 completed OK. */
2512cal_done_ok:
Dinh Nguyen3da42852015-06-02 22:52:49 -05002513 /*
2514 * Reset the delay chains back to zero if they have moved > 1
2515 * (check for > 1 because loop will increase d even when pass in
2516 * first case).
2517 */
2518 if (d > 2)
Marek Vasutc336ca32015-07-17 04:24:18 +02002519 scc_mgr_zero_group(rw_group, 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002520
2521 return 1;
2522}
2523
2524/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2525static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2526 uint32_t test_bgn)
2527{
2528 uint32_t rank_bgn, sr;
2529 uint32_t grp_calibrated;
2530 uint32_t write_group;
2531
2532 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2533
2534 /* update info for sims */
2535
2536 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2537 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2538
2539 write_group = read_group;
2540
2541 /* update info for sims */
2542 reg_file_set_group(read_group);
2543
2544 grp_calibrated = 1;
2545 /* Read per-bit deskew can be done on a per shadow register basis */
2546 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2547 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2548 /* Determine if this set of ranks should be skipped entirely */
2549 if (!param->skip_shadow_regs[sr]) {
2550 /* This is the last calibration round, update FOM here */
2551 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2552 write_group,
2553 read_group,
2554 test_bgn, 0,
2555 1)) {
2556 grp_calibrated = 0;
2557 }
2558 }
2559 }
2560
2561
2562 if (grp_calibrated == 0) {
2563 set_failing_group_stage(write_group,
2564 CAL_STAGE_VFIFO_AFTER_WRITES,
2565 CAL_SUBSTAGE_VFIFO_CENTER);
2566 return 0;
2567 }
2568
2569 return 1;
2570}
2571
2572/* Calibrate LFIFO to find smallest read latency */
2573static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2574{
2575 uint32_t found_one;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002576
2577 debug("%s:%d\n", __func__, __LINE__);
2578
2579 /* update info for sims */
2580 reg_file_set_stage(CAL_STAGE_LFIFO);
2581 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2582
2583 /* Load up the patterns used by read calibration for all ranks */
2584 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2585 found_one = 0;
2586
Dinh Nguyen3da42852015-06-02 22:52:49 -05002587 do {
Marek Vasut1273dd92015-07-12 21:05:08 +02002588 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002589 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2590 __func__, __LINE__, gbl->curr_read_lat);
2591
2592 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2593 NUM_READ_TESTS,
2594 PASS_ALL_BITS,
Marek Vasut96df6032015-07-19 07:35:36 +02002595 1)) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002596 break;
2597 }
2598
2599 found_one = 1;
2600 /* reduce read latency and see if things are working */
2601 /* correctly */
2602 gbl->curr_read_lat--;
2603 } while (gbl->curr_read_lat > 0);
2604
2605 /* reset the fifos to get pointers to known state */
2606
Marek Vasut1273dd92015-07-12 21:05:08 +02002607 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002608
2609 if (found_one) {
2610 /* add a fudge factor to the read latency that was determined */
2611 gbl->curr_read_lat += 2;
Marek Vasut1273dd92015-07-12 21:05:08 +02002612 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002613 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2614 read_lat=%u\n", __func__, __LINE__,
2615 gbl->curr_read_lat);
2616 return 1;
2617 } else {
2618 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2619 CAL_SUBSTAGE_READ_LATENCY);
2620
2621 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2622 read_lat=%u\n", __func__, __LINE__,
2623 gbl->curr_read_lat);
2624 return 0;
2625 }
2626}
2627
2628/*
2629 * issue write test command.
2630 * two variants are provided. one that just tests a write pattern and
2631 * another that tests datamask functionality.
2632 */
2633static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2634 uint32_t test_dm)
2635{
2636 uint32_t mcc_instruction;
2637 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2638 ENABLE_SUPER_QUICK_CALIBRATION);
2639 uint32_t rw_wl_nop_cycles;
2640 uint32_t addr;
2641
2642 /*
2643 * Set counter and jump addresses for the right
2644 * number of NOP cycles.
2645 * The number of supported NOP cycles can range from -1 to infinity
2646 * Three different cases are handled:
2647 *
2648 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2649 * mechanism will be used to insert the right number of NOPs
2650 *
2651 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2652 * issuing the write command will jump straight to the
2653 * micro-instruction that turns on DQS (for DDRx), or outputs write
2654 * data (for RLD), skipping
2655 * the NOP micro-instruction all together
2656 *
2657 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2658 * turned on in the same micro-instruction that issues the write
2659 * command. Then we need
2660 * to directly jump to the micro-instruction that sends out the data
2661 *
2662 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2663 * (2 and 3). One jump-counter (0) is used to perform multiple
2664 * write-read operations.
2665 * one counter left to issue this command in "multiple-group" mode
2666 */
2667
2668 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2669
2670 if (rw_wl_nop_cycles == -1) {
2671 /*
2672 * CNTR 2 - We want to execute the special write operation that
2673 * turns on DQS right away and then skip directly to the
2674 * instruction that sends out the data. We set the counter to a
2675 * large number so that the jump is always taken.
2676 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002677 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002678
2679 /* CNTR 3 - Not used */
2680 if (test_dm) {
2681 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002682 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
Marek Vasut1273dd92015-07-12 21:05:08 +02002683 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002684 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
Marek Vasut1273dd92015-07-12 21:05:08 +02002685 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002686 } else {
2687 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
Marek Vasut1273dd92015-07-12 21:05:08 +02002688 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2689 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2690 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2691 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002692 }
2693 } else if (rw_wl_nop_cycles == 0) {
2694 /*
2695 * CNTR 2 - We want to skip the NOP operation and go straight
2696 * to the DQS enable instruction. We set the counter to a large
2697 * number so that the jump is always taken.
2698 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002699 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002700
2701 /* CNTR 3 - Not used */
2702 if (test_dm) {
2703 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002704 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
Marek Vasut1273dd92015-07-12 21:05:08 +02002705 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002706 } else {
2707 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002708 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2709 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002710 }
2711 } else {
2712 /*
2713 * CNTR 2 - In this case we want to execute the next instruction
2714 * and NOT take the jump. So we set the counter to 0. The jump
2715 * address doesn't count.
2716 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002717 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2718 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002719
2720 /*
2721 * CNTR 3 - Set the nop counter to the number of cycles we
2722 * need to loop for, minus 1.
2723 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002724 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002725 if (test_dm) {
2726 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002727 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2728 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002729 } else {
2730 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002731 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2732 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002733 }
2734 }
2735
Marek Vasut1273dd92015-07-12 21:05:08 +02002736 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2737 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002738
Dinh Nguyen3da42852015-06-02 22:52:49 -05002739 if (quick_write_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02002740 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002741 else
Marek Vasut1273dd92015-07-12 21:05:08 +02002742 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002743
Marek Vasut1273dd92015-07-12 21:05:08 +02002744 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002745
2746 /*
2747 * CNTR 1 - This is used to ensure enough time elapses
2748 * for read data to come back.
2749 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002750 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002751
Dinh Nguyen3da42852015-06-02 22:52:49 -05002752 if (test_dm) {
Marek Vasut1273dd92015-07-12 21:05:08 +02002753 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2754 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002755 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +02002756 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2757 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002758 }
2759
Marek Vasutc4815f72015-07-12 19:03:33 +02002760 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002761 writel(mcc_instruction, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002762}
2763
2764/* Test writes, can check for a single bit pass or multiple bit pass */
2765static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2766 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2767 uint32_t *bit_chk, uint32_t all_ranks)
2768{
Dinh Nguyen3da42852015-06-02 22:52:49 -05002769 uint32_t r;
2770 uint32_t correct_mask_vg;
2771 uint32_t tmp_bit_chk;
2772 uint32_t vg;
2773 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2774 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2775 uint32_t addr_rw_mgr;
2776 uint32_t base_rw_mgr;
2777
2778 *bit_chk = param->write_correct_mask;
2779 correct_mask_vg = param->write_correct_mask_vg;
2780
2781 for (r = rank_bgn; r < rank_end; r++) {
2782 if (param->skip_ranks[r]) {
2783 /* request to skip the rank */
2784 continue;
2785 }
2786
2787 /* set rank */
2788 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2789
2790 tmp_bit_chk = 0;
Marek Vasuta4bfa462015-07-12 17:52:36 +02002791 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002792 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2793 /* reset the fifos to get pointers to known state */
Marek Vasut1273dd92015-07-12 21:05:08 +02002794 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002795
2796 tmp_bit_chk = tmp_bit_chk <<
2797 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2798 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2799 rw_mgr_mem_calibrate_write_test_issue(write_group *
2800 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2801 use_dm);
2802
Marek Vasut17fdc912015-07-12 20:05:54 +02002803 base_rw_mgr = readl(addr_rw_mgr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002804 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2805 if (vg == 0)
2806 break;
2807 }
2808 *bit_chk &= tmp_bit_chk;
2809 }
2810
2811 if (all_correct) {
2812 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2813 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2814 %u => %lu", write_group, use_dm,
2815 *bit_chk, param->write_correct_mask,
2816 (long unsigned int)(*bit_chk ==
2817 param->write_correct_mask));
2818 return *bit_chk == param->write_correct_mask;
2819 } else {
2820 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2821 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2822 write_group, use_dm, *bit_chk);
2823 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2824 (long unsigned int)(*bit_chk != 0));
2825 return *bit_chk != 0x00;
2826 }
2827}
2828
2829/*
2830 * center all windows. do per-bit-deskew to possibly increase size of
2831 * certain windows.
2832 */
2833static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2834 uint32_t write_group, uint32_t test_bgn)
2835{
2836 uint32_t i, p, min_index;
2837 int32_t d;
2838 /*
2839 * Store these as signed since there are comparisons with
2840 * signed numbers.
2841 */
2842 uint32_t bit_chk;
2843 uint32_t sticky_bit_chk;
2844 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2845 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2846 int32_t mid;
2847 int32_t mid_min, orig_mid_min;
2848 int32_t new_dqs, start_dqs, shift_dq;
2849 int32_t dq_margin, dqs_margin, dm_margin;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002850 uint32_t temp_dq_out1_delay;
2851 uint32_t addr;
2852
Marek Vasutc4907892015-07-13 02:11:02 +02002853 int ret;
2854
Dinh Nguyen3da42852015-06-02 22:52:49 -05002855 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2856
2857 dm_margin = 0;
2858
Marek Vasutc4815f72015-07-12 19:03:33 +02002859 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002860 start_dqs = readl(addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05002861 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2862
2863 /* per-bit deskew */
2864
2865 /*
2866 * set the left and right edge of each bit to an illegal value
2867 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2868 */
2869 sticky_bit_chk = 0;
2870 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2871 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2872 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2873 }
2874
2875 /* Search for the left edge of the window for each bit */
Marek Vasut71120772015-07-13 02:38:15 +02002876 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
2877 &bit_chk, &sticky_bit_chk,
2878 left_edge, right_edge, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002879
2880 /* Search for the right edge of the window for each bit */
Marek Vasutc4907892015-07-13 02:11:02 +02002881 ret = search_right_edge(1, rank_bgn, write_group, 0,
2882 start_dqs, 0,
2883 &bit_chk, &sticky_bit_chk,
2884 left_edge, right_edge, 0);
2885 if (ret) {
2886 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
2887 CAL_SUBSTAGE_WRITES_CENTER);
2888 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002889 }
2890
2891 /* Find middle of window for each DQ bit */
2892 mid_min = left_edge[0] - right_edge[0];
2893 min_index = 0;
2894 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2895 mid = left_edge[i] - right_edge[i];
2896 if (mid < mid_min) {
2897 mid_min = mid;
2898 min_index = i;
2899 }
2900 }
2901
2902 /*
2903 * -mid_min/2 represents the amount that we need to move DQS.
2904 * If mid_min is odd and positive we'll need to add one to
2905 * make sure the rounding in further calculations is correct
2906 * (always bias to the right), so just add 1 for all positive values.
2907 */
2908 if (mid_min > 0)
2909 mid_min++;
2910 mid_min = mid_min / 2;
2911 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2912 __LINE__, mid_min);
2913
2914 /* Determine the amount we can change DQS (which is -mid_min) */
2915 orig_mid_min = mid_min;
2916 new_dqs = start_dqs;
2917 mid_min = 0;
2918 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2919 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2920 /* Initialize data for export structures */
2921 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2922 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2923
2924 /* add delay to bring centre of all DQ windows to the same "level" */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002925 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2926 /* Use values before divide by 2 to reduce round off error */
2927 shift_dq = (left_edge[i] - right_edge[i] -
2928 (left_edge[min_index] - right_edge[min_index]))/2 +
2929 (orig_mid_min - mid_min);
2930
2931 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2932 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2933
Marek Vasut1273dd92015-07-12 21:05:08 +02002934 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002935 temp_dq_out1_delay = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002936 if (shift_dq + (int32_t)temp_dq_out1_delay >
2937 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2938 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2939 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2940 shift_dq = -(int32_t)temp_dq_out1_delay;
2941 }
2942 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2943 i, shift_dq);
Marek Vasut07aee5b2015-07-12 22:07:33 +02002944 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002945 scc_mgr_load_dq(i);
2946
2947 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2948 left_edge[i] - shift_dq + (-mid_min),
2949 right_edge[i] + shift_dq - (-mid_min));
2950 /* To determine values for export structures */
2951 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2952 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2953
2954 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2955 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2956 }
2957
2958 /* Move DQS */
2959 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
Marek Vasut1273dd92015-07-12 21:05:08 +02002960 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002961
2962 /* Centre DM */
2963 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2964
2965 /*
2966 * set the left and right edge of each bit to an illegal value,
2967 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2968 */
2969 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2970 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2971 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2972 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2973 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2974 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2975 int32_t win_best = 0;
2976
2977 /* Search for the/part of the window with DM shift */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002978 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
Marek Vasut32675242015-07-17 06:07:13 +02002979 scc_mgr_apply_group_dm_out1_delay(d);
Marek Vasut1273dd92015-07-12 21:05:08 +02002980 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002981
2982 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2983 PASS_ALL_BITS, &bit_chk,
2984 0)) {
2985 /* USE Set current end of the window */
2986 end_curr = -d;
2987 /*
2988 * If a starting edge of our window has not been seen
2989 * this is our current start of the DM window.
2990 */
2991 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2992 bgn_curr = -d;
2993
2994 /*
2995 * If current window is bigger than best seen.
2996 * Set best seen to be current window.
2997 */
2998 if ((end_curr-bgn_curr+1) > win_best) {
2999 win_best = end_curr-bgn_curr+1;
3000 bgn_best = bgn_curr;
3001 end_best = end_curr;
3002 }
3003 } else {
3004 /* We just saw a failing test. Reset temp edge */
3005 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3006 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3007 }
3008 }
3009
3010
3011 /* Reset DM delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02003012 scc_mgr_apply_group_dm_out1_delay(0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003013
3014 /*
3015 * Check to see if the current window nudges up aganist 0 delay.
3016 * If so we need to continue the search by shifting DQS otherwise DQS
3017 * search begins as a new search. */
3018 if (end_curr != 0) {
3019 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3020 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3021 }
3022
3023 /* Search for the/part of the window with DQS shifts */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003024 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3025 /*
3026 * Note: This only shifts DQS, so are we limiting ourselve to
3027 * width of DQ unnecessarily.
3028 */
3029 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3030 d + new_dqs);
3031
Marek Vasut1273dd92015-07-12 21:05:08 +02003032 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003033 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3034 PASS_ALL_BITS, &bit_chk,
3035 0)) {
3036 /* USE Set current end of the window */
3037 end_curr = d;
3038 /*
3039 * If a beginning edge of our window has not been seen
3040 * this is our current begin of the DM window.
3041 */
3042 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3043 bgn_curr = d;
3044
3045 /*
3046 * If current window is bigger than best seen. Set best
3047 * seen to be current window.
3048 */
3049 if ((end_curr-bgn_curr+1) > win_best) {
3050 win_best = end_curr-bgn_curr+1;
3051 bgn_best = bgn_curr;
3052 end_best = end_curr;
3053 }
3054 } else {
3055 /* We just saw a failing test. Reset temp edge */
3056 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3057 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3058
3059 /* Early exit optimization: if ther remaining delay
3060 chain space is less than already seen largest window
3061 we can exit */
3062 if ((win_best-1) >
3063 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3064 break;
3065 }
3066 }
3067 }
3068
3069 /* assign left and right edge for cal and reporting; */
3070 left_edge[0] = -1*bgn_best;
3071 right_edge[0] = end_best;
3072
3073 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3074 __LINE__, left_edge[0], right_edge[0]);
3075
3076 /* Move DQS (back to orig) */
3077 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3078
3079 /* Move DM */
3080
3081 /* Find middle of window for the DM bit */
3082 mid = (left_edge[0] - right_edge[0]) / 2;
3083
3084 /* only move right, since we are not moving DQS/DQ */
3085 if (mid < 0)
3086 mid = 0;
3087
3088 /* dm_marign should fail if we never find a window */
3089 if (win_best == 0)
3090 dm_margin = -1;
3091 else
3092 dm_margin = left_edge[0] - mid;
3093
Marek Vasut32675242015-07-17 06:07:13 +02003094 scc_mgr_apply_group_dm_out1_delay(mid);
Marek Vasut1273dd92015-07-12 21:05:08 +02003095 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003096
3097 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3098 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3099 right_edge[0], mid, dm_margin);
3100 /* Export values */
3101 gbl->fom_out += dq_margin + dqs_margin;
3102
3103 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3104 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3105 dq_margin, dqs_margin, dm_margin);
3106
3107 /*
3108 * Do not remove this line as it makes sure all of our
3109 * decisions have been applied.
3110 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003111 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003112 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3113}
3114
Marek Vasutdb3a6062015-07-18 07:23:25 +02003115/**
3116 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3117 * @rank_bgn: Rank number
3118 * @group: Read/Write Group
3119 * @test_bgn: Rank at which the test begins
3120 *
3121 * Stage 2: Write Calibration Part One.
3122 *
3123 * This function implements UniPHY calibration Stage 2, as explained in
3124 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3125 */
3126static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3127 const u32 test_bgn)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003128{
Marek Vasutdb3a6062015-07-18 07:23:25 +02003129 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003130
Marek Vasutdb3a6062015-07-18 07:23:25 +02003131 /* Update info for sims */
3132 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3133
3134 reg_file_set_group(group);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003135 reg_file_set_stage(CAL_STAGE_WRITES);
3136 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3137
Marek Vasutdb3a6062015-07-18 07:23:25 +02003138 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3139 if (!ret) {
3140 set_failing_group_stage(group, CAL_STAGE_WRITES,
Dinh Nguyen3da42852015-06-02 22:52:49 -05003141 CAL_SUBSTAGE_WRITES_CENTER);
Marek Vasutdb3a6062015-07-18 07:23:25 +02003142 return -EIO;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003143 }
3144
Marek Vasutdb3a6062015-07-18 07:23:25 +02003145 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003146}
3147
Marek Vasut4b0ac262015-07-20 07:33:33 +02003148/**
3149 * mem_precharge_and_activate() - Precharge all banks and activate
3150 *
3151 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3152 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003153static void mem_precharge_and_activate(void)
3154{
Marek Vasut4b0ac262015-07-20 07:33:33 +02003155 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003156
3157 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
Marek Vasut4b0ac262015-07-20 07:33:33 +02003158 /* Test if the rank should be skipped. */
3159 if (param->skip_ranks[r])
Dinh Nguyen3da42852015-06-02 22:52:49 -05003160 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003161
Marek Vasut4b0ac262015-07-20 07:33:33 +02003162 /* Set rank. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003163 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3164
Marek Vasut4b0ac262015-07-20 07:33:33 +02003165 /* Precharge all banks. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003166 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3167 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003168
Marek Vasut1273dd92015-07-12 21:05:08 +02003169 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3170 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3171 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003172
Marek Vasut1273dd92015-07-12 21:05:08 +02003173 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3174 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3175 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003176
Marek Vasut4b0ac262015-07-20 07:33:33 +02003177 /* Activate rows. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003178 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3179 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003180 }
3181}
3182
Marek Vasut16502a02015-07-17 01:57:41 +02003183/**
3184 * mem_init_latency() - Configure memory RLAT and WLAT settings
3185 *
3186 * Configure memory RLAT and WLAT parameters.
3187 */
3188static void mem_init_latency(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003189{
Marek Vasut16502a02015-07-17 01:57:41 +02003190 /*
3191 * For AV/CV, LFIFO is hardened and always runs at full rate
3192 * so max latency in AFI clocks, used here, is correspondingly
3193 * smaller.
3194 */
3195 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3196 u32 rlat, wlat;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003197
3198 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut16502a02015-07-17 01:57:41 +02003199
3200 /*
3201 * Read in write latency.
3202 * WL for Hard PHY does not include additive latency.
3203 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003204 wlat = readl(&data_mgr->t_wl_add);
3205 wlat += readl(&data_mgr->mem_t_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003206
Marek Vasut16502a02015-07-17 01:57:41 +02003207 gbl->rw_wl_nop_cycles = wlat - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003208
Marek Vasut16502a02015-07-17 01:57:41 +02003209 /* Read in readl latency. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003210 rlat = readl(&data_mgr->t_rl_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003211
Marek Vasut16502a02015-07-17 01:57:41 +02003212 /* Set a pretty high read latency initially. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003213 gbl->curr_read_lat = rlat + 16;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003214 if (gbl->curr_read_lat > max_latency)
3215 gbl->curr_read_lat = max_latency;
3216
Marek Vasut1273dd92015-07-12 21:05:08 +02003217 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003218
Marek Vasut16502a02015-07-17 01:57:41 +02003219 /* Advertise write latency. */
3220 writel(wlat, &phy_mgr_cfg->afi_wlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003221}
3222
Marek Vasut51cea0b2015-07-26 10:54:15 +02003223/**
3224 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3225 *
3226 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3227 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003228static void mem_skip_calibrate(void)
3229{
3230 uint32_t vfifo_offset;
3231 uint32_t i, j, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003232
3233 debug("%s:%d\n", __func__, __LINE__);
3234 /* Need to update every shadow register set used by the interface */
3235 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003236 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05003237 /*
3238 * Set output phase alignment settings appropriate for
3239 * skip calibration.
3240 */
3241 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3242 scc_mgr_set_dqs_en_phase(i, 0);
3243#if IO_DLL_CHAIN_LENGTH == 6
3244 scc_mgr_set_dqdqs_output_phase(i, 6);
3245#else
3246 scc_mgr_set_dqdqs_output_phase(i, 7);
3247#endif
3248 /*
3249 * Case:33398
3250 *
3251 * Write data arrives to the I/O two cycles before write
3252 * latency is reached (720 deg).
3253 * -> due to bit-slip in a/c bus
3254 * -> to allow board skew where dqs is longer than ck
3255 * -> how often can this happen!?
3256 * -> can claim back some ptaps for high freq
3257 * support if we can relax this, but i digress...
3258 *
3259 * The write_clk leads mem_ck by 90 deg
3260 * The minimum ptap of the OPA is 180 deg
3261 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3262 * The write_clk is always delayed by 2 ptaps
3263 *
3264 * Hence, to make DQS aligned to CK, we need to delay
3265 * DQS by:
3266 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3267 *
3268 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3269 * gives us the number of ptaps, which simplies to:
3270 *
3271 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3272 */
Marek Vasut51cea0b2015-07-26 10:54:15 +02003273 scc_mgr_set_dqdqs_output_phase(i,
3274 1.25 * IO_DLL_CHAIN_LENGTH - 2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003275 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003276 writel(0xff, &sdr_scc_mgr->dqs_ena);
3277 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003278
Dinh Nguyen3da42852015-06-02 22:52:49 -05003279 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003280 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3281 SCC_MGR_GROUP_COUNTER_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003282 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003283 writel(0xff, &sdr_scc_mgr->dq_ena);
3284 writel(0xff, &sdr_scc_mgr->dm_ena);
3285 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003286 }
3287
3288 /* Compensate for simulation model behaviour */
3289 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3290 scc_mgr_set_dqs_bus_in_delay(i, 10);
3291 scc_mgr_load_dqs(i);
3292 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003293 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003294
3295 /*
3296 * ArriaV has hard FIFOs that can only be initialized by incrementing
3297 * in sequencer.
3298 */
3299 vfifo_offset = CALIB_VFIFO_OFFSET;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003300 for (j = 0; j < vfifo_offset; j++)
Marek Vasut1273dd92015-07-12 21:05:08 +02003301 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
Marek Vasut1273dd92015-07-12 21:05:08 +02003302 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003303
3304 /*
Marek Vasut51cea0b2015-07-26 10:54:15 +02003305 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3306 * setting from generation-time constant.
Dinh Nguyen3da42852015-06-02 22:52:49 -05003307 */
3308 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
Marek Vasut1273dd92015-07-12 21:05:08 +02003309 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003310}
3311
Marek Vasut3589fbf2015-07-20 04:34:51 +02003312/**
3313 * mem_calibrate() - Memory calibration entry point.
3314 *
3315 * Perform memory calibration.
3316 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003317static uint32_t mem_calibrate(void)
3318{
3319 uint32_t i;
3320 uint32_t rank_bgn, sr;
3321 uint32_t write_group, write_test_bgn;
3322 uint32_t read_group, read_test_bgn;
3323 uint32_t run_groups, current_run;
3324 uint32_t failing_groups = 0;
3325 uint32_t group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003326
Marek Vasut33c42bb2015-07-17 02:21:47 +02003327 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3328 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3329
Dinh Nguyen3da42852015-06-02 22:52:49 -05003330 debug("%s:%d\n", __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003331
Marek Vasut16502a02015-07-17 01:57:41 +02003332 /* Initialize the data settings */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003333 gbl->error_substage = CAL_SUBSTAGE_NIL;
3334 gbl->error_stage = CAL_STAGE_NIL;
3335 gbl->error_group = 0xff;
3336 gbl->fom_in = 0;
3337 gbl->fom_out = 0;
3338
Marek Vasut16502a02015-07-17 01:57:41 +02003339 /* Initialize WLAT and RLAT. */
3340 mem_init_latency();
3341
3342 /* Initialize bit slips. */
3343 mem_precharge_and_activate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003344
Dinh Nguyen3da42852015-06-02 22:52:49 -05003345 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003346 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3347 SCC_MGR_GROUP_COUNTER_OFFSET);
Marek Vasutfa5d8212015-07-19 01:34:43 +02003348 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3349 if (i == 0)
3350 scc_mgr_set_hhp_extras();
3351
Marek Vasutc5c5f532015-07-17 02:06:20 +02003352 scc_set_bypass_mode(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003353 }
3354
Marek Vasut722c9682015-07-17 02:07:12 +02003355 /* Calibration is skipped. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003356 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3357 /*
3358 * Set VFIFO and LFIFO to instant-on settings in skip
3359 * calibration mode.
3360 */
3361 mem_skip_calibrate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003362
Marek Vasut722c9682015-07-17 02:07:12 +02003363 /*
3364 * Do not remove this line as it makes sure all of our
3365 * decisions have been applied.
3366 */
3367 writel(0, &sdr_scc_mgr->update);
3368 return 1;
3369 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003370
Marek Vasut722c9682015-07-17 02:07:12 +02003371 /* Calibration is not skipped. */
3372 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3373 /*
3374 * Zero all delay chain/phase settings for all
3375 * groups and all shadow register sets.
3376 */
3377 scc_mgr_zero_all();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003378
Marek Vasut722c9682015-07-17 02:07:12 +02003379 run_groups = ~param->skip_groups;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003380
Marek Vasut722c9682015-07-17 02:07:12 +02003381 for (write_group = 0, write_test_bgn = 0; write_group
3382 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3383 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
Marek Vasutc452dcd2015-07-17 02:50:56 +02003384
3385 /* Initialize the group failure */
Marek Vasut722c9682015-07-17 02:07:12 +02003386 group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003387
Marek Vasut722c9682015-07-17 02:07:12 +02003388 current_run = run_groups & ((1 <<
3389 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3390 run_groups = run_groups >>
3391 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003392
Marek Vasut722c9682015-07-17 02:07:12 +02003393 if (current_run == 0)
3394 continue;
3395
3396 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3397 SCC_MGR_GROUP_COUNTER_OFFSET);
3398 scc_mgr_zero_group(write_group, 0);
3399
Marek Vasut33c42bb2015-07-17 02:21:47 +02003400 for (read_group = write_group * rwdqs_ratio,
3401 read_test_bgn = 0;
Marek Vasutc452dcd2015-07-17 02:50:56 +02003402 read_group < (write_group + 1) * rwdqs_ratio;
Marek Vasut33c42bb2015-07-17 02:21:47 +02003403 read_group++,
3404 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3405 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3406 continue;
Marek Vasut722c9682015-07-17 02:07:12 +02003407
Marek Vasut33c42bb2015-07-17 02:21:47 +02003408 /* Calibrate the VFIFO */
3409 if (rw_mgr_mem_calibrate_vfifo(read_group,
3410 read_test_bgn))
3411 continue;
3412
Marek Vasutc452dcd2015-07-17 02:50:56 +02003413 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3414 return 0;
3415
3416 /* The group failed, we're done. */
3417 goto grp_failed;
3418 }
3419
3420 /* Calibrate the output side */
3421 for (rank_bgn = 0, sr = 0;
3422 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3423 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3424 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3425 continue;
3426
3427 /* Not needed in quick mode! */
3428 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3429 continue;
3430
3431 /*
3432 * Determine if this set of ranks
3433 * should be skipped entirely.
3434 */
3435 if (param->skip_shadow_regs[sr])
3436 continue;
3437
3438 /* Calibrate WRITEs */
Marek Vasutdb3a6062015-07-18 07:23:25 +02003439 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
Marek Vasutc452dcd2015-07-17 02:50:56 +02003440 write_group, write_test_bgn))
3441 continue;
3442
Marek Vasut33c42bb2015-07-17 02:21:47 +02003443 group_failed = 1;
3444 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3445 return 0;
Marek Vasut722c9682015-07-17 02:07:12 +02003446 }
3447
Marek Vasutc452dcd2015-07-17 02:50:56 +02003448 /* Some group failed, we're done. */
3449 if (group_failed)
3450 goto grp_failed;
Marek Vasut4ac21612015-07-17 02:31:04 +02003451
Marek Vasutc452dcd2015-07-17 02:50:56 +02003452 for (read_group = write_group * rwdqs_ratio,
3453 read_test_bgn = 0;
3454 read_group < (write_group + 1) * rwdqs_ratio;
3455 read_group++,
3456 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3457 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3458 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003459
Marek Vasutc452dcd2015-07-17 02:50:56 +02003460 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3461 read_test_bgn))
3462 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003463
Marek Vasutc452dcd2015-07-17 02:50:56 +02003464 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3465 return 0;
Marek Vasut4ac21612015-07-17 02:31:04 +02003466
Marek Vasutc452dcd2015-07-17 02:50:56 +02003467 /* The group failed, we're done. */
3468 goto grp_failed;
Marek Vasut722c9682015-07-17 02:07:12 +02003469 }
3470
Marek Vasutc452dcd2015-07-17 02:50:56 +02003471 /* No group failed, continue as usual. */
3472 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003473
Marek Vasutc452dcd2015-07-17 02:50:56 +02003474grp_failed: /* A group failed, increment the counter. */
3475 failing_groups++;
Marek Vasut722c9682015-07-17 02:07:12 +02003476 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003477
Marek Vasut722c9682015-07-17 02:07:12 +02003478 /*
3479 * USER If there are any failing groups then report
3480 * the failure.
3481 */
3482 if (failing_groups != 0)
3483 return 0;
3484
Marek Vasutc50ae302015-07-17 02:40:21 +02003485 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3486 continue;
3487
3488 /*
3489 * If we're skipping groups as part of debug,
3490 * don't calibrate LFIFO.
3491 */
3492 if (param->skip_groups != 0)
3493 continue;
3494
Marek Vasut722c9682015-07-17 02:07:12 +02003495 /* Calibrate the LFIFO */
Marek Vasutc50ae302015-07-17 02:40:21 +02003496 if (!rw_mgr_mem_calibrate_lfifo())
3497 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003498 }
3499
3500 /*
3501 * Do not remove this line as it makes sure all of our decisions
3502 * have been applied.
3503 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003504 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003505 return 1;
3506}
3507
Marek Vasut23a040c2015-07-17 01:20:21 +02003508/**
3509 * run_mem_calibrate() - Perform memory calibration
3510 *
3511 * This function triggers the entire memory calibration procedure.
3512 */
3513static int run_mem_calibrate(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003514{
Marek Vasut23a040c2015-07-17 01:20:21 +02003515 int pass;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003516
3517 debug("%s:%d\n", __func__, __LINE__);
3518
3519 /* Reset pass/fail status shown on afi_cal_success/fail */
Marek Vasut1273dd92015-07-12 21:05:08 +02003520 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003521
Marek Vasut23a040c2015-07-17 01:20:21 +02003522 /* Stop tracking manager. */
3523 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003524
Marek Vasut9fa9c902015-07-17 01:12:07 +02003525 phy_mgr_initialize();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003526 rw_mgr_mem_initialize();
3527
Marek Vasut23a040c2015-07-17 01:20:21 +02003528 /* Perform the actual memory calibration. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003529 pass = mem_calibrate();
3530
3531 mem_precharge_and_activate();
Marek Vasut1273dd92015-07-12 21:05:08 +02003532 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003533
Marek Vasut23a040c2015-07-17 01:20:21 +02003534 /* Handoff. */
3535 rw_mgr_mem_handoff();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003536 /*
Marek Vasut23a040c2015-07-17 01:20:21 +02003537 * In Hard PHY this is a 2-bit control:
3538 * 0: AFI Mux Select
3539 * 1: DDIO Mux Select
Dinh Nguyen3da42852015-06-02 22:52:49 -05003540 */
Marek Vasut23a040c2015-07-17 01:20:21 +02003541 writel(0x2, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003542
Marek Vasut23a040c2015-07-17 01:20:21 +02003543 /* Start tracking manager. */
3544 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3545
3546 return pass;
3547}
3548
3549/**
3550 * debug_mem_calibrate() - Report result of memory calibration
3551 * @pass: Value indicating whether calibration passed or failed
3552 *
3553 * This function reports the results of the memory calibration
3554 * and writes debug information into the register file.
3555 */
3556static void debug_mem_calibrate(int pass)
3557{
3558 uint32_t debug_info;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003559
3560 if (pass) {
3561 printf("%s: CALIBRATION PASSED\n", __FILE__);
3562
3563 gbl->fom_in /= 2;
3564 gbl->fom_out /= 2;
3565
3566 if (gbl->fom_in > 0xff)
3567 gbl->fom_in = 0xff;
3568
3569 if (gbl->fom_out > 0xff)
3570 gbl->fom_out = 0xff;
3571
3572 /* Update the FOM in the register file */
3573 debug_info = gbl->fom_in;
3574 debug_info |= gbl->fom_out << 8;
Marek Vasut1273dd92015-07-12 21:05:08 +02003575 writel(debug_info, &sdr_reg_file->fom);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003576
Marek Vasut1273dd92015-07-12 21:05:08 +02003577 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3578 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003579 } else {
3580 printf("%s: CALIBRATION FAILED\n", __FILE__);
3581
3582 debug_info = gbl->error_stage;
3583 debug_info |= gbl->error_substage << 8;
3584 debug_info |= gbl->error_group << 16;
3585
Marek Vasut1273dd92015-07-12 21:05:08 +02003586 writel(debug_info, &sdr_reg_file->failing_stage);
3587 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3588 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003589
3590 /* Update the failing group/stage in the register file */
3591 debug_info = gbl->error_stage;
3592 debug_info |= gbl->error_substage << 8;
3593 debug_info |= gbl->error_group << 16;
Marek Vasut1273dd92015-07-12 21:05:08 +02003594 writel(debug_info, &sdr_reg_file->failing_stage);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003595 }
3596
Marek Vasut23a040c2015-07-17 01:20:21 +02003597 printf("%s: Calibration complete\n", __FILE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003598}
3599
Marek Vasutbb064342015-07-19 06:12:42 +02003600/**
3601 * hc_initialize_rom_data() - Initialize ROM data
3602 *
3603 * Initialize ROM data.
3604 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003605static void hc_initialize_rom_data(void)
3606{
Marek Vasutbb064342015-07-19 06:12:42 +02003607 u32 i, addr;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003608
Marek Vasutc4815f72015-07-12 19:03:33 +02003609 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003610 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3611 writel(inst_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003612
Marek Vasutc4815f72015-07-12 19:03:33 +02003613 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003614 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3615 writel(ac_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003616}
3617
Marek Vasut9c1ab2c2015-07-19 06:13:37 +02003618/**
3619 * initialize_reg_file() - Initialize SDR register file
3620 *
3621 * Initialize SDR register file.
3622 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003623static void initialize_reg_file(void)
3624{
Dinh Nguyen3da42852015-06-02 22:52:49 -05003625 /* Initialize the register file with the correct data */
Marek Vasut1273dd92015-07-12 21:05:08 +02003626 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3627 writel(0, &sdr_reg_file->debug_data_addr);
3628 writel(0, &sdr_reg_file->cur_stage);
3629 writel(0, &sdr_reg_file->fom);
3630 writel(0, &sdr_reg_file->failing_stage);
3631 writel(0, &sdr_reg_file->debug1);
3632 writel(0, &sdr_reg_file->debug2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003633}
3634
Marek Vasut2ca151f2015-07-19 06:14:04 +02003635/**
3636 * initialize_hps_phy() - Initialize HPS PHY
3637 *
3638 * Initialize HPS PHY.
3639 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003640static void initialize_hps_phy(void)
3641{
3642 uint32_t reg;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003643 /*
3644 * Tracking also gets configured here because it's in the
3645 * same register.
3646 */
3647 uint32_t trk_sample_count = 7500;
3648 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3649 /*
3650 * Format is number of outer loops in the 16 MSB, sample
3651 * count in 16 LSB.
3652 */
3653
3654 reg = 0;
3655 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3656 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3657 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3658 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3659 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3660 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3661 /*
3662 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3663 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3664 */
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3666 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3667 trk_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003668 writel(reg, &sdr_ctrl->phy_ctrl0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003669
3670 reg = 0;
3671 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3672 trk_sample_count >>
3673 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3674 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3675 trk_long_idle_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003676 writel(reg, &sdr_ctrl->phy_ctrl1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003677
3678 reg = 0;
3679 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3680 trk_long_idle_sample_count >>
3681 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003682 writel(reg, &sdr_ctrl->phy_ctrl2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003683}
3684
Marek Vasut880e46f2015-07-17 00:45:11 +02003685/**
3686 * initialize_tracking() - Initialize tracking
3687 *
3688 * Initialize the register file with usable initial data.
3689 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003690static void initialize_tracking(void)
3691{
Marek Vasut880e46f2015-07-17 00:45:11 +02003692 /*
3693 * Initialize the register file with the correct data.
3694 * Compute usable version of value in case we skip full
3695 * computation later.
3696 */
3697 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3698 &sdr_reg_file->dtaps_per_ptap);
3699
3700 /* trk_sample_count */
3701 writel(7500, &sdr_reg_file->trk_sample_count);
3702
3703 /* longidle outer loop [15:0] */
3704 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003705
3706 /*
Marek Vasut880e46f2015-07-17 00:45:11 +02003707 * longidle sample count [31:24]
3708 * trfc, worst case of 933Mhz 4Gb [23:16]
3709 * trcd, worst case [15:8]
3710 * vfifo wait [7:0]
Dinh Nguyen3da42852015-06-02 22:52:49 -05003711 */
Marek Vasut880e46f2015-07-17 00:45:11 +02003712 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3713 &sdr_reg_file->delays);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003714
Marek Vasut880e46f2015-07-17 00:45:11 +02003715 /* mux delay */
3716 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3717 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3718 &sdr_reg_file->trk_rw_mgr_addr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003719
Marek Vasut880e46f2015-07-17 00:45:11 +02003720 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3721 &sdr_reg_file->trk_read_dqs_width);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003722
Marek Vasut880e46f2015-07-17 00:45:11 +02003723 /* trefi [7:0] */
3724 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3725 &sdr_reg_file->trk_rfsh);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003726}
3727
3728int sdram_calibration_full(void)
3729{
3730 struct param_type my_param;
3731 struct gbl_type my_gbl;
3732 uint32_t pass;
Marek Vasut84e0b0c2015-07-17 01:05:36 +02003733
3734 memset(&my_param, 0, sizeof(my_param));
3735 memset(&my_gbl, 0, sizeof(my_gbl));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003736
3737 param = &my_param;
3738 gbl = &my_gbl;
3739
Dinh Nguyen3da42852015-06-02 22:52:49 -05003740 /* Set the calibration enabled by default */
3741 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3742 /*
3743 * Only sweep all groups (regardless of fail state) by default
3744 * Set enabled read test by default.
3745 */
3746#if DISABLE_GUARANTEED_READ
3747 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3748#endif
3749 /* Initialize the register file */
3750 initialize_reg_file();
3751
3752 /* Initialize any PHY CSR */
3753 initialize_hps_phy();
3754
3755 scc_mgr_initialize();
3756
3757 initialize_tracking();
3758
Dinh Nguyen3da42852015-06-02 22:52:49 -05003759 printf("%s: Preparing to start memory calibration\n", __FILE__);
3760
3761 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut23f62b32015-07-13 01:05:27 +02003762 debug_cond(DLEVEL == 1,
3763 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3764 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3765 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3766 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3767 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3768 debug_cond(DLEVEL == 1,
3769 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3770 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3771 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3772 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3773 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3774 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3775 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3776 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3777 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3778 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3779 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3780 IO_IO_OUT2_DELAY_MAX);
3781 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3782 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003783
3784 hc_initialize_rom_data();
3785
3786 /* update info for sims */
3787 reg_file_set_stage(CAL_STAGE_NIL);
3788 reg_file_set_group(0);
3789
3790 /*
3791 * Load global needed for those actions that require
3792 * some dynamic calibration support.
3793 */
3794 dyn_calib_steps = STATIC_CALIB_STEPS;
3795 /*
3796 * Load global to allow dynamic selection of delay loop settings
3797 * based on calibration mode.
3798 */
3799 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3800 skip_delay_mask = 0xff;
3801 else
3802 skip_delay_mask = 0x0;
3803
3804 pass = run_mem_calibrate();
Marek Vasut23a040c2015-07-17 01:20:21 +02003805 debug_mem_calibrate(pass);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003806 return pass;
3807}