blob: 9dba55adaa7efe06bdc0127476f9901ac524e19c [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05302/*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05305 */
6
7/*
Simon Glass64dcd252015-04-05 16:07:40 -06008 * Designware ethernet IP driver for U-Boot
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05309 */
10
11#include <common.h>
Patrice Chotardba1f9662017-11-29 09:06:11 +010012#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070013#include <cpu_func.h>
Simon Glass75577ba2015-04-05 16:07:41 -060014#include <dm.h>
Simon Glass64dcd252015-04-05 16:07:40 -060015#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053017#include <miiphy.h>
18#include <malloc.h>
Simon Glass90526e92020-05-10 11:39:56 -060019#include <net.h>
Bin Meng8b7ee662015-09-11 03:24:35 -070020#include <pci.h>
Ley Foon Tan495c70f2018-06-14 18:45:23 +080021#include <reset.h>
Simon Glass90526e92020-05-10 11:39:56 -060022#include <asm/cache.h>
Simon Glass336d4612020-02-03 07:36:16 -070023#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070024#include <dm/devres.h>
Stefan Roeseef760252012-05-07 12:04:25 +020025#include <linux/compiler.h>
Simon Glassc05ed002020-05-10 11:40:11 -060026#include <linux/delay.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053027#include <linux/err.h>
Florian Fainelli7a9ca9d2017-12-09 14:59:55 -080028#include <linux/kernel.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053029#include <asm/io.h>
Jacob Chen6ec922f2017-03-27 16:54:17 +080030#include <power/regulator.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053031#include "designware.h"
32
Alexey Brodkin92a190a2014-01-22 20:54:06 +040033static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
34{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010035#ifdef CONFIG_DM_ETH
36 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
37 struct eth_mac_regs *mac_p = priv->mac_regs_p;
38#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040039 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010040#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040041 ulong start;
42 u16 miiaddr;
43 int timeout = CONFIG_MDIO_TIMEOUT;
44
45 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
46 ((reg << MIIREGSHIFT) & MII_REGMSK);
47
48 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
49
50 start = get_timer(0);
51 while (get_timer(start) < timeout) {
52 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
53 return readl(&mac_p->miidata);
54 udelay(10);
55 };
56
Simon Glass64dcd252015-04-05 16:07:40 -060057 return -ETIMEDOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040058}
59
60static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
61 u16 val)
62{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010063#ifdef CONFIG_DM_ETH
64 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
65 struct eth_mac_regs *mac_p = priv->mac_regs_p;
66#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040067 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010068#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040069 ulong start;
70 u16 miiaddr;
Simon Glass64dcd252015-04-05 16:07:40 -060071 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040072
73 writel(val, &mac_p->miidata);
74 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
75 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
76
77 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
78
79 start = get_timer(0);
80 while (get_timer(start) < timeout) {
81 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
82 ret = 0;
83 break;
84 }
85 udelay(10);
86 };
87
88 return ret;
89}
90
Simon Glassbcee8d62019-12-06 21:41:35 -070091#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010092static int dw_mdio_reset(struct mii_dev *bus)
93{
94 struct udevice *dev = bus->priv;
95 struct dw_eth_dev *priv = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -070096 struct dw_eth_pdata *pdata = dev_get_plat(dev);
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010097 int ret;
98
99 if (!dm_gpio_is_valid(&priv->reset_gpio))
100 return 0;
101
102 /* reset the phy */
103 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
104 if (ret)
105 return ret;
106
107 udelay(pdata->reset_delays[0]);
108
109 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
110 if (ret)
111 return ret;
112
113 udelay(pdata->reset_delays[1]);
114
115 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
116 if (ret)
117 return ret;
118
119 udelay(pdata->reset_delays[2]);
120
121 return 0;
122}
123#endif
124
125static int dw_mdio_init(const char *name, void *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400126{
127 struct mii_dev *bus = mdio_alloc();
128
129 if (!bus) {
130 printf("Failed to allocate MDIO bus\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600131 return -ENOMEM;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400132 }
133
134 bus->read = dw_mdio_read;
135 bus->write = dw_mdio_write;
Ben Whitten192bc692015-12-30 13:05:58 +0000136 snprintf(bus->name, sizeof(bus->name), "%s", name);
Simon Glassbcee8d62019-12-06 21:41:35 -0700137#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100138 bus->reset = dw_mdio_reset;
139#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400140
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100141 bus->priv = priv;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400142
143 return mdio_register(bus);
144}
Vipin Kumar13edd172012-03-26 00:09:56 +0000145
Simon Glass64dcd252015-04-05 16:07:40 -0600146static void tx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530147{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530148 struct eth_dma_regs *dma_p = priv->dma_regs_p;
149 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
150 char *txbuffs = &priv->txbuffs[0];
151 struct dmamacdescr *desc_p;
152 u32 idx;
153
154 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
155 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200156 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
157 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530158
159#if defined(CONFIG_DW_ALTDESCRIPTOR)
160 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
Marek Vasut2b261092015-12-20 03:59:23 +0100161 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
162 DESC_TXSTS_TXCHECKINSCTRL |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530163 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
164
165 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
166 desc_p->dmamac_cntl = 0;
167 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
168#else
169 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
170 desc_p->txrx_status = 0;
171#endif
172 }
173
174 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200175 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530176
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400177 /* Flush all Tx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200178 flush_dcache_range((ulong)priv->tx_mac_descrtable,
179 (ulong)priv->tx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400180 sizeof(priv->tx_mac_descrtable));
181
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530182 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400183 priv->tx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530184}
185
Simon Glass64dcd252015-04-05 16:07:40 -0600186static void rx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530187{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530188 struct eth_dma_regs *dma_p = priv->dma_regs_p;
189 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
190 char *rxbuffs = &priv->rxbuffs[0];
191 struct dmamacdescr *desc_p;
192 u32 idx;
193
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400194 /* Before passing buffers to GMAC we need to make sure zeros
195 * written there right after "priv" structure allocation were
196 * flushed into RAM.
197 * Otherwise there's a chance to get some of them flushed in RAM when
198 * GMAC is already pushing data to RAM via DMA. This way incoming from
199 * GMAC data will be corrupted. */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200200 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400201
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530202 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
203 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200204 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
205 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530206
207 desc_p->dmamac_cntl =
Marek Vasut2b261092015-12-20 03:59:23 +0100208 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530209 DESC_RXCTRL_RXCHAIN;
210
211 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
212 }
213
214 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200215 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530216
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400217 /* Flush all Rx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200218 flush_dcache_range((ulong)priv->rx_mac_descrtable,
219 (ulong)priv->rx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400220 sizeof(priv->rx_mac_descrtable));
221
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530222 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400223 priv->rx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530224}
225
Simon Glass64dcd252015-04-05 16:07:40 -0600226static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530227{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530228 struct eth_mac_regs *mac_p = priv->mac_regs_p;
229 u32 macid_lo, macid_hi;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530230
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400231 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
232 (mac_id[3] << 24);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530233 macid_hi = mac_id[4] + (mac_id[5] << 8);
234
235 writel(macid_hi, &mac_p->macaddr0hi);
236 writel(macid_lo, &mac_p->macaddr0lo);
237
238 return 0;
239}
240
Simon Glass0ea38db2017-01-11 11:46:08 +0100241static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
242 struct phy_device *phydev)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400243{
244 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
245
246 if (!phydev->link) {
247 printf("%s: No link.\n", phydev->dev->name);
Simon Glass0ea38db2017-01-11 11:46:08 +0100248 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400249 }
250
251 if (phydev->speed != 1000)
252 conf |= MII_PORTSELECT;
Alexey Brodkinb884c3f2016-01-13 16:59:36 +0300253 else
254 conf &= ~MII_PORTSELECT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400255
256 if (phydev->speed == 100)
257 conf |= FES_100;
258
259 if (phydev->duplex)
260 conf |= FULLDPLXMODE;
261
262 writel(conf, &mac_p->conf);
263
264 printf("Speed: %d, %s duplex%s\n", phydev->speed,
265 (phydev->duplex) ? "full" : "half",
266 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Simon Glass0ea38db2017-01-11 11:46:08 +0100267
268 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400269}
270
Simon Glass64dcd252015-04-05 16:07:40 -0600271static void _dw_eth_halt(struct dw_eth_dev *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400272{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400273 struct eth_mac_regs *mac_p = priv->mac_regs_p;
274 struct eth_dma_regs *dma_p = priv->dma_regs_p;
275
276 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
277 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
278
279 phy_shutdown(priv->phydev);
280}
281
Simon Glasse72ced22017-01-11 11:46:10 +0100282int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530283{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530284 struct eth_mac_regs *mac_p = priv->mac_regs_p;
285 struct eth_dma_regs *dma_p = priv->dma_regs_p;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400286 unsigned int start;
Simon Glass64dcd252015-04-05 16:07:40 -0600287 int ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530288
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400289 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
Vipin Kumar13edd172012-03-26 00:09:56 +0000290
Quentin Schulzc6122192018-06-04 12:17:33 +0200291 /*
292 * When a MII PHY is used, we must set the PS bit for the DMA
293 * reset to succeed.
294 */
295 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
296 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
297 else
298 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
299
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400300 start = get_timer(0);
301 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
Alexey Brodkin875143f2015-01-13 17:10:24 +0300302 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
303 printf("DMA reset timeout\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600304 return -ETIMEDOUT;
Alexey Brodkin875143f2015-01-13 17:10:24 +0300305 }
Stefan Roeseef760252012-05-07 12:04:25 +0200306
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400307 mdelay(100);
308 };
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530309
Bin Mengf3edfd32015-06-15 18:40:19 +0800310 /*
311 * Soft reset above clears HW address registers.
312 * So we have to set it here once again.
313 */
314 _dw_write_hwaddr(priv, enetaddr);
315
Simon Glass64dcd252015-04-05 16:07:40 -0600316 rx_descs_init(priv);
317 tx_descs_init(priv);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530318
Ian Campbell49692c52014-05-08 22:26:35 +0100319 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530320
Sonic Zhangd2279222015-01-29 14:38:50 +0800321#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400322 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
323 &dma_p->opmode);
Sonic Zhangd2279222015-01-29 14:38:50 +0800324#else
325 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
326 &dma_p->opmode);
327#endif
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530328
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400329 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530330
Sonic Zhang2ddaf132015-01-29 13:37:31 +0800331#ifdef CONFIG_DW_AXI_BURST_LEN
332 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
333#endif
334
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400335 /* Start up the PHY */
Simon Glass64dcd252015-04-05 16:07:40 -0600336 ret = phy_startup(priv->phydev);
337 if (ret) {
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400338 printf("Could not initialize PHY %s\n",
339 priv->phydev->dev->name);
Simon Glass64dcd252015-04-05 16:07:40 -0600340 return ret;
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530341 }
342
Simon Glass0ea38db2017-01-11 11:46:08 +0100343 ret = dw_adjust_link(priv, mac_p, priv->phydev);
344 if (ret)
345 return ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530346
Simon Glassf63f28e2017-01-11 11:46:09 +0100347 return 0;
348}
349
Simon Glasse72ced22017-01-11 11:46:10 +0100350int designware_eth_enable(struct dw_eth_dev *priv)
Simon Glassf63f28e2017-01-11 11:46:09 +0100351{
352 struct eth_mac_regs *mac_p = priv->mac_regs_p;
353
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400354 if (!priv->phydev->link)
Simon Glass64dcd252015-04-05 16:07:40 -0600355 return -EIO;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530356
Armando Viscontiaa510052012-03-26 00:09:55 +0000357 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530358
359 return 0;
360}
361
Florian Fainelli7a9ca9d2017-12-09 14:59:55 -0800362#define ETH_ZLEN 60
363
Simon Glass64dcd252015-04-05 16:07:40 -0600364static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530365{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530366 struct eth_dma_regs *dma_p = priv->dma_regs_p;
367 u32 desc_num = priv->tx_currdescnum;
368 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200369 ulong desc_start = (ulong)desc_p;
370 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200371 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200372 ulong data_start = desc_p->dmamac_addr;
373 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
Ian Campbell964ea7c2014-05-08 22:26:33 +0100374 /*
375 * Strictly we only need to invalidate the "txrx_status" field
376 * for the following check, but on some platforms we cannot
Marek Vasut96cec172014-09-15 01:05:23 +0200377 * invalidate only 4 bytes, so we flush the entire descriptor,
378 * which is 16 bytes in total. This is safe because the
379 * individual descriptors in the array are each aligned to
380 * ARCH_DMA_MINALIGN and padded appropriately.
Ian Campbell964ea7c2014-05-08 22:26:33 +0100381 */
Marek Vasut96cec172014-09-15 01:05:23 +0200382 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400383
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530384 /* Check if the descriptor is owned by CPU */
385 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
386 printf("CPU not owner of tx frame\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600387 return -EPERM;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530388 }
389
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200390 memcpy((void *)data_start, packet, length);
Simon Goldschmidt7efb75b2018-11-17 10:24:42 +0100391 if (length < ETH_ZLEN) {
392 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
393 length = ETH_ZLEN;
394 }
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530395
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400396 /* Flush data to be sent */
Marek Vasut96cec172014-09-15 01:05:23 +0200397 flush_dcache_range(data_start, data_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400398
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530399#if defined(CONFIG_DW_ALTDESCRIPTOR)
400 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
Simon Goldschmidtae8ac8d2018-11-17 10:24:41 +0100401 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
402 ((length << DESC_TXCTRL_SIZE1SHFT) &
403 DESC_TXCTRL_SIZE1MASK);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530404
405 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
406 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
407#else
Simon Goldschmidtae8ac8d2018-11-17 10:24:41 +0100408 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
409 ((length << DESC_TXCTRL_SIZE1SHFT) &
410 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
411 DESC_TXCTRL_TXFIRST;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530412
413 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
414#endif
415
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400416 /* Flush modified buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200417 flush_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400418
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530419 /* Test the wrap-around condition. */
420 if (++desc_num >= CONFIG_TX_DESCR_NUM)
421 desc_num = 0;
422
423 priv->tx_currdescnum = desc_num;
424
425 /* Start the transmission */
426 writel(POLL_DATA, &dma_p->txpolldemand);
427
428 return 0;
429}
430
Simon Glass75577ba2015-04-05 16:07:41 -0600431static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530432{
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400433 u32 status, desc_num = priv->rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530434 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Simon Glass75577ba2015-04-05 16:07:41 -0600435 int length = -EAGAIN;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200436 ulong desc_start = (ulong)desc_p;
437 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200438 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200439 ulong data_start = desc_p->dmamac_addr;
440 ulong data_end;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530441
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400442 /* Invalidate entire buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200443 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400444
445 status = desc_p->txrx_status;
446
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530447 /* Check if the owner is the CPU */
448 if (!(status & DESC_RXSTS_OWNBYDMA)) {
449
Marek Vasut2b261092015-12-20 03:59:23 +0100450 length = (status & DESC_RXSTS_FRMLENMSK) >>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530451 DESC_RXSTS_FRMLENSHFT;
452
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400453 /* Invalidate received data */
Marek Vasut96cec172014-09-15 01:05:23 +0200454 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
455 invalidate_dcache_range(data_start, data_end);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200456 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530457 }
458
Simon Glass75577ba2015-04-05 16:07:41 -0600459 return length;
460}
461
462static int _dw_free_pkt(struct dw_eth_dev *priv)
463{
464 u32 desc_num = priv->rx_currdescnum;
465 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200466 ulong desc_start = (ulong)desc_p;
467 ulong desc_end = desc_start +
Simon Glass75577ba2015-04-05 16:07:41 -0600468 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
469
470 /*
471 * Make the current descriptor valid again and go to
472 * the next one
473 */
474 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
475
476 /* Flush only status field - others weren't changed */
477 flush_dcache_range(desc_start, desc_end);
478
479 /* Test the wrap-around condition. */
480 if (++desc_num >= CONFIG_RX_DESCR_NUM)
481 desc_num = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530482 priv->rx_currdescnum = desc_num;
483
Simon Glass75577ba2015-04-05 16:07:41 -0600484 return 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530485}
486
Simon Glass64dcd252015-04-05 16:07:40 -0600487static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530488{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400489 struct phy_device *phydev;
Simon Goldschmidt5dce9df2019-07-15 21:53:05 +0200490 int phy_addr = -1, ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530491
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400492#ifdef CONFIG_PHY_ADDR
Simon Goldschmidt5dce9df2019-07-15 21:53:05 +0200493 phy_addr = CONFIG_PHY_ADDR;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530494#endif
495
Simon Goldschmidt5dce9df2019-07-15 21:53:05 +0200496 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400497 if (!phydev)
Simon Glass64dcd252015-04-05 16:07:40 -0600498 return -ENODEV;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530499
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400500 phydev->supported &= PHY_GBIT_FEATURES;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300501 if (priv->max_speed) {
502 ret = phy_set_supported(phydev, priv->max_speed);
503 if (ret)
504 return ret;
505 }
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400506 phydev->advertising = phydev->supported;
507
508 priv->phydev = phydev;
509 phy_config(phydev);
510
Simon Glass64dcd252015-04-05 16:07:40 -0600511 return 0;
512}
513
Simon Glass75577ba2015-04-05 16:07:41 -0600514#ifndef CONFIG_DM_ETH
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900515static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
Simon Glass64dcd252015-04-05 16:07:40 -0600516{
Simon Glassf63f28e2017-01-11 11:46:09 +0100517 int ret;
518
Simon Glasse72ced22017-01-11 11:46:10 +0100519 ret = designware_eth_init(dev->priv, dev->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100520 if (!ret)
521 ret = designware_eth_enable(dev->priv);
522
523 return ret;
Simon Glass64dcd252015-04-05 16:07:40 -0600524}
525
526static int dw_eth_send(struct eth_device *dev, void *packet, int length)
527{
528 return _dw_eth_send(dev->priv, packet, length);
529}
530
531static int dw_eth_recv(struct eth_device *dev)
532{
Simon Glass75577ba2015-04-05 16:07:41 -0600533 uchar *packet;
534 int length;
535
536 length = _dw_eth_recv(dev->priv, &packet);
537 if (length == -EAGAIN)
538 return 0;
539 net_process_received_packet(packet, length);
540
541 _dw_free_pkt(dev->priv);
542
543 return 0;
Simon Glass64dcd252015-04-05 16:07:40 -0600544}
545
546static void dw_eth_halt(struct eth_device *dev)
547{
548 return _dw_eth_halt(dev->priv);
549}
550
551static int dw_write_hwaddr(struct eth_device *dev)
552{
553 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530554}
555
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400556int designware_initialize(ulong base_addr, u32 interface)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530557{
558 struct eth_device *dev;
559 struct dw_eth_dev *priv;
560
561 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
562 if (!dev)
563 return -ENOMEM;
564
565 /*
566 * Since the priv structure contains the descriptors which need a strict
567 * buswidth alignment, memalign is used to allocate memory
568 */
Ian Campbell1c848a22014-05-08 22:26:32 +0100569 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
570 sizeof(struct dw_eth_dev));
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530571 if (!priv) {
572 free(dev);
573 return -ENOMEM;
574 }
575
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200576 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
577 printf("designware: buffers are outside DMA memory\n");
578 return -EINVAL;
579 }
580
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530581 memset(dev, 0, sizeof(struct eth_device));
582 memset(priv, 0, sizeof(struct dw_eth_dev));
583
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400584 sprintf(dev->name, "dwmac.%lx", base_addr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530585 dev->iobase = (int)base_addr;
586 dev->priv = priv;
587
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530588 priv->dev = dev;
589 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
590 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
591 DW_DMA_BASE_OFFSET);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530592
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530593 dev->init = dw_eth_init;
594 dev->send = dw_eth_send;
595 dev->recv = dw_eth_recv;
596 dev->halt = dw_eth_halt;
597 dev->write_hwaddr = dw_write_hwaddr;
598
599 eth_register(dev);
600
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400601 priv->interface = interface;
602
603 dw_mdio_init(dev->name, priv->mac_regs_p);
604 priv->bus = miiphy_get_dev_by_name(dev->name);
605
Simon Glass64dcd252015-04-05 16:07:40 -0600606 return dw_phy_init(priv, dev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530607}
Simon Glass75577ba2015-04-05 16:07:41 -0600608#endif
609
610#ifdef CONFIG_DM_ETH
611static int designware_eth_start(struct udevice *dev)
612{
Simon Glassc69cda22020-12-03 16:55:20 -0700613 struct eth_pdata *pdata = dev_get_plat(dev);
Simon Glassf63f28e2017-01-11 11:46:09 +0100614 struct dw_eth_dev *priv = dev_get_priv(dev);
615 int ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600616
Simon Glasse72ced22017-01-11 11:46:10 +0100617 ret = designware_eth_init(priv, pdata->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100618 if (ret)
619 return ret;
620 ret = designware_eth_enable(priv);
621 if (ret)
622 return ret;
623
624 return 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600625}
626
Simon Glasse72ced22017-01-11 11:46:10 +0100627int designware_eth_send(struct udevice *dev, void *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600628{
629 struct dw_eth_dev *priv = dev_get_priv(dev);
630
631 return _dw_eth_send(priv, packet, length);
632}
633
Simon Glasse72ced22017-01-11 11:46:10 +0100634int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Simon Glass75577ba2015-04-05 16:07:41 -0600635{
636 struct dw_eth_dev *priv = dev_get_priv(dev);
637
638 return _dw_eth_recv(priv, packetp);
639}
640
Simon Glasse72ced22017-01-11 11:46:10 +0100641int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600642{
643 struct dw_eth_dev *priv = dev_get_priv(dev);
644
645 return _dw_free_pkt(priv);
646}
647
Simon Glasse72ced22017-01-11 11:46:10 +0100648void designware_eth_stop(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600649{
650 struct dw_eth_dev *priv = dev_get_priv(dev);
651
652 return _dw_eth_halt(priv);
653}
654
Simon Glasse72ced22017-01-11 11:46:10 +0100655int designware_eth_write_hwaddr(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600656{
Simon Glassc69cda22020-12-03 16:55:20 -0700657 struct eth_pdata *pdata = dev_get_plat(dev);
Simon Glass75577ba2015-04-05 16:07:41 -0600658 struct dw_eth_dev *priv = dev_get_priv(dev);
659
660 return _dw_write_hwaddr(priv, pdata->enetaddr);
661}
662
Bin Meng8b7ee662015-09-11 03:24:35 -0700663static int designware_eth_bind(struct udevice *dev)
664{
665#ifdef CONFIG_DM_PCI
666 static int num_cards;
667 char name[20];
668
669 /* Create a unique device name for PCI type devices */
670 if (device_is_on_pci_bus(dev)) {
671 sprintf(name, "eth_designware#%u", num_cards++);
672 device_set_name(dev, name);
673 }
674#endif
675
676 return 0;
677}
678
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100679int designware_eth_probe(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600680{
Simon Glassc69cda22020-12-03 16:55:20 -0700681 struct eth_pdata *pdata = dev_get_plat(dev);
Simon Glass75577ba2015-04-05 16:07:41 -0600682 struct dw_eth_dev *priv = dev_get_priv(dev);
Bin Mengf0dc73c2015-09-03 05:37:29 -0700683 u32 iobase = pdata->iobase;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200684 ulong ioaddr;
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200685 int ret, err;
Ley Foon Tan495c70f2018-06-14 18:45:23 +0800686 struct reset_ctl_bulk reset_bulk;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100687#ifdef CONFIG_CLK
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200688 int i, clock_nb;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100689
690 priv->clock_count = 0;
Patrick Delaunay89f68302020-09-25 09:41:14 +0200691 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
692 0);
Patrice Chotardba1f9662017-11-29 09:06:11 +0100693 if (clock_nb > 0) {
694 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
695 GFP_KERNEL);
696 if (!priv->clocks)
697 return -ENOMEM;
698
699 for (i = 0; i < clock_nb; i++) {
700 err = clk_get_by_index(dev, i, &priv->clocks[i]);
701 if (err < 0)
702 break;
703
704 err = clk_enable(&priv->clocks[i]);
Eugeniy Paltsev1693a572018-02-06 17:12:09 +0300705 if (err && err != -ENOSYS && err != -ENOTSUPP) {
Patrice Chotardba1f9662017-11-29 09:06:11 +0100706 pr_err("failed to enable clock %d\n", i);
707 clk_free(&priv->clocks[i]);
708 goto clk_err;
709 }
710 priv->clock_count++;
711 }
712 } else if (clock_nb != -ENOENT) {
713 pr_err("failed to get clock phandle(%d)\n", clock_nb);
714 return clock_nb;
715 }
716#endif
Simon Glass75577ba2015-04-05 16:07:41 -0600717
Jacob Chen6ec922f2017-03-27 16:54:17 +0800718#if defined(CONFIG_DM_REGULATOR)
719 struct udevice *phy_supply;
720
721 ret = device_get_supply_regulator(dev, "phy-supply",
722 &phy_supply);
723 if (ret) {
724 debug("%s: No phy supply\n", dev->name);
725 } else {
726 ret = regulator_set_enable(phy_supply, true);
727 if (ret) {
728 puts("Error enabling phy supply\n");
729 return ret;
730 }
731 }
732#endif
733
Ley Foon Tan495c70f2018-06-14 18:45:23 +0800734 ret = reset_get_bulk(dev, &reset_bulk);
735 if (ret)
736 dev_warn(dev, "Can't get reset: %d\n", ret);
737 else
738 reset_deassert_bulk(&reset_bulk);
739
Bin Meng8b7ee662015-09-11 03:24:35 -0700740#ifdef CONFIG_DM_PCI
741 /*
742 * If we are on PCI bus, either directly attached to a PCI root port,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700743 * or via a PCI bridge, fill in plat before we probe the hardware.
Bin Meng8b7ee662015-09-11 03:24:35 -0700744 */
745 if (device_is_on_pci_bus(dev)) {
Bin Meng8b7ee662015-09-11 03:24:35 -0700746 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
747 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
Bin Meng6758a6c2016-02-02 05:58:00 -0800748 iobase = dm_pci_mem_to_phys(dev, iobase);
Bin Meng8b7ee662015-09-11 03:24:35 -0700749
750 pdata->iobase = iobase;
751 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
752 }
753#endif
754
Bin Mengf0dc73c2015-09-03 05:37:29 -0700755 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200756 ioaddr = iobase;
757 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
758 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
Simon Glass75577ba2015-04-05 16:07:41 -0600759 priv->interface = pdata->phy_interface;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300760 priv->max_speed = pdata->max_speed;
Simon Glass75577ba2015-04-05 16:07:41 -0600761
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200762 ret = dw_mdio_init(dev->name, dev);
763 if (ret) {
764 err = ret;
765 goto mdio_err;
766 }
Simon Glass75577ba2015-04-05 16:07:41 -0600767 priv->bus = miiphy_get_dev_by_name(dev->name);
768
769 ret = dw_phy_init(priv, dev);
770 debug("%s, ret=%d\n", __func__, ret);
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200771 if (!ret)
772 return 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600773
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200774 /* continue here for cleanup if no PHY found */
775 err = ret;
776 mdio_unregister(priv->bus);
777 mdio_free(priv->bus);
778mdio_err:
Patrice Chotardba1f9662017-11-29 09:06:11 +0100779
780#ifdef CONFIG_CLK
781clk_err:
782 ret = clk_release_all(priv->clocks, priv->clock_count);
783 if (ret)
784 pr_err("failed to disable all clocks\n");
785
Patrice Chotardba1f9662017-11-29 09:06:11 +0100786#endif
Simon Goldschmidt4ee587e2019-07-12 21:07:03 +0200787 return err;
Simon Glass75577ba2015-04-05 16:07:41 -0600788}
789
Bin Meng5d2459f2015-10-07 21:32:38 -0700790static int designware_eth_remove(struct udevice *dev)
791{
792 struct dw_eth_dev *priv = dev_get_priv(dev);
793
794 free(priv->phydev);
795 mdio_unregister(priv->bus);
796 mdio_free(priv->bus);
797
Patrice Chotardba1f9662017-11-29 09:06:11 +0100798#ifdef CONFIG_CLK
799 return clk_release_all(priv->clocks, priv->clock_count);
800#else
Bin Meng5d2459f2015-10-07 21:32:38 -0700801 return 0;
Patrice Chotardba1f9662017-11-29 09:06:11 +0100802#endif
Bin Meng5d2459f2015-10-07 21:32:38 -0700803}
804
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100805const struct eth_ops designware_eth_ops = {
Simon Glass75577ba2015-04-05 16:07:41 -0600806 .start = designware_eth_start,
807 .send = designware_eth_send,
808 .recv = designware_eth_recv,
809 .free_pkt = designware_eth_free_pkt,
810 .stop = designware_eth_stop,
811 .write_hwaddr = designware_eth_write_hwaddr,
812};
813
Simon Glassd1998a92020-12-03 16:55:21 -0700814int designware_eth_of_to_plat(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600815{
Simon Glassc69cda22020-12-03 16:55:20 -0700816 struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
Simon Glassbcee8d62019-12-06 21:41:35 -0700817#if CONFIG_IS_ENABLED(DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100818 struct dw_eth_dev *priv = dev_get_priv(dev);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300819#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100820 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
Simon Glass75577ba2015-04-05 16:07:41 -0600821 const char *phy_mode;
Simon Glassbcee8d62019-12-06 21:41:35 -0700822#if CONFIG_IS_ENABLED(DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100823 int reset_flags = GPIOD_IS_OUT;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300824#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100825 int ret = 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600826
Philipp Tomsich15050f12017-09-11 22:04:13 +0200827 pdata->iobase = dev_read_addr(dev);
Simon Glass75577ba2015-04-05 16:07:41 -0600828 pdata->phy_interface = -1;
Philipp Tomsich15050f12017-09-11 22:04:13 +0200829 phy_mode = dev_read_string(dev, "phy-mode");
Simon Glass75577ba2015-04-05 16:07:41 -0600830 if (phy_mode)
831 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
832 if (pdata->phy_interface == -1) {
833 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
834 return -EINVAL;
835 }
836
Philipp Tomsich15050f12017-09-11 22:04:13 +0200837 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300838
Simon Glassbcee8d62019-12-06 21:41:35 -0700839#if CONFIG_IS_ENABLED(DM_GPIO)
Philipp Tomsich7ad326a2017-06-07 18:46:01 +0200840 if (dev_read_bool(dev, "snps,reset-active-low"))
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100841 reset_flags |= GPIOD_ACTIVE_LOW;
842
843 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
844 &priv->reset_gpio, reset_flags);
845 if (ret == 0) {
Philipp Tomsich7ad326a2017-06-07 18:46:01 +0200846 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
847 dw_pdata->reset_delays, 3);
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100848 } else if (ret == -ENOENT) {
849 ret = 0;
850 }
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300851#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100852
853 return ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600854}
855
856static const struct udevice_id designware_eth_ids[] = {
857 { .compatible = "allwinner,sun7i-a20-gmac" },
Beniamino Galvanicfe25562016-08-16 11:49:50 +0200858 { .compatible = "amlogic,meson6-dwmac" },
Heiner Kallweit655217d2017-01-27 21:25:59 +0100859 { .compatible = "amlogic,meson-gx-dwmac" },
Neil Armstrongec353ad2018-09-10 16:44:14 +0200860 { .compatible = "amlogic,meson-gxbb-dwmac" },
Neil Armstrong71a38a82018-11-08 17:16:11 +0100861 { .compatible = "amlogic,meson-axg-dwmac" },
Michael Kurzb20b70f2017-01-22 16:04:27 +0100862 { .compatible = "st,stm32-dwmac" },
Eugeniy Paltsev2a723232019-10-07 19:10:50 +0300863 { .compatible = "snps,arc-dwmac-3.70a" },
Simon Glass75577ba2015-04-05 16:07:41 -0600864 { }
865};
866
Marek Vasut9f76f102015-07-25 18:42:34 +0200867U_BOOT_DRIVER(eth_designware) = {
Simon Glass75577ba2015-04-05 16:07:41 -0600868 .name = "eth_designware",
869 .id = UCLASS_ETH,
870 .of_match = designware_eth_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700871 .of_to_plat = designware_eth_of_to_plat,
Bin Meng8b7ee662015-09-11 03:24:35 -0700872 .bind = designware_eth_bind,
Simon Glass75577ba2015-04-05 16:07:41 -0600873 .probe = designware_eth_probe,
Bin Meng5d2459f2015-10-07 21:32:38 -0700874 .remove = designware_eth_remove,
Simon Glass75577ba2015-04-05 16:07:41 -0600875 .ops = &designware_eth_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700876 .priv_auto = sizeof(struct dw_eth_dev),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700877 .plat_auto = sizeof(struct dw_eth_pdata),
Simon Glass75577ba2015-04-05 16:07:41 -0600878 .flags = DM_FLAG_ALLOC_PRIV_DMA,
879};
Bin Meng8b7ee662015-09-11 03:24:35 -0700880
881static struct pci_device_id supported[] = {
882 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
883 { }
884};
885
886U_BOOT_PCI_DEVICE(eth_designware, supported);
Simon Glass75577ba2015-04-05 16:07:41 -0600887#endif