blob: 91c2d10ffc8e0315b7ddde8d87adf363c4d15851 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Roberto Cerati45a16932013-04-24 10:46:17 +08002/*
3 * Micrel KS8851_MLL 16bit Network driver
4 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
Roberto Cerati45a16932013-04-24 10:46:17 +08005 */
6
Simon Glassf7ae49f2020-05-10 11:40:05 -06007#include <log.h>
Roberto Cerati45a16932013-04-24 10:46:17 +08008#include <asm/io.h>
9#include <common.h>
10#include <command.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
Simon Glassc05ed002020-05-10 11:40:11 -060014#include <linux/delay.h>
Roberto Cerati45a16932013-04-24 10:46:17 +080015
16#include "ks8851_mll.h"
17
18#define DRIVERNAME "ks8851_mll"
19
Roberto Cerati45a16932013-04-24 10:46:17 +080020#define RX_BUF_SIZE 2000
21
Roberto Cerati45a16932013-04-24 10:46:17 +080022/*
Roberto Cerati45a16932013-04-24 10:46:17 +080023 * struct ks_net - KS8851 driver private data
Marek Vasutb7c6ae22020-03-25 17:35:00 +010024 * @dev : legacy non-DM ethernet device structure
25 * @iobase : register base
Roberto Cerati45a16932013-04-24 10:46:17 +080026 * @bus_width : i/o bus width.
Roberto Cerati45a16932013-04-24 10:46:17 +080027 * @sharedbus : Multipex(addr and data bus) mode indicator.
Marek Vasut63f22f52020-03-25 17:23:11 +010028 * @extra_byte : number of extra byte prepended rx pkt.
Roberto Cerati45a16932013-04-24 10:46:17 +080029 */
Roberto Cerati45a16932013-04-24 10:46:17 +080030struct ks_net {
Marek Vasut1d476de2020-03-25 18:00:35 +010031#ifndef CONFIG_DM_ETH
Marek Vasutb7c6ae22020-03-25 17:35:00 +010032 struct eth_device dev;
Marek Vasut1d476de2020-03-25 18:00:35 +010033#endif
Marek Vasutb7c6ae22020-03-25 17:35:00 +010034 phys_addr_t iobase;
Roberto Cerati45a16932013-04-24 10:46:17 +080035 int bus_width;
Roberto Cerati45a16932013-04-24 10:46:17 +080036 u16 sharedbus;
Marek Vasut9c9f3fc2020-03-25 18:47:10 +010037 u16 rxfc;
Roberto Cerati45a16932013-04-24 10:46:17 +080038 u8 extra_byte;
Marek Vasutb7c6ae22020-03-25 17:35:00 +010039};
Roberto Cerati45a16932013-04-24 10:46:17 +080040
41#define BE3 0x8000 /* Byte Enable 3 */
42#define BE2 0x4000 /* Byte Enable 2 */
43#define BE1 0x2000 /* Byte Enable 1 */
44#define BE0 0x1000 /* Byte Enable 0 */
45
Marek Vasutb7c6ae22020-03-25 17:35:00 +010046static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
Roberto Cerati45a16932013-04-24 10:46:17 +080047{
48 u8 shift_bit = offset & 0x03;
49 u8 shift_data = (offset & 1) << 3;
50
Marek Vasutb7c6ae22020-03-25 17:35:00 +010051 writew(offset | (BE0 << shift_bit), ks->iobase + 2);
Roberto Cerati45a16932013-04-24 10:46:17 +080052
Marek Vasutb7c6ae22020-03-25 17:35:00 +010053 return (u8)(readw(ks->iobase) >> shift_data);
Roberto Cerati45a16932013-04-24 10:46:17 +080054}
55
Marek Vasutb7c6ae22020-03-25 17:35:00 +010056static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
Roberto Cerati45a16932013-04-24 10:46:17 +080057{
Marek Vasutb7c6ae22020-03-25 17:35:00 +010058 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
Roberto Cerati45a16932013-04-24 10:46:17 +080059
Marek Vasutb7c6ae22020-03-25 17:35:00 +010060 return readw(ks->iobase);
Roberto Cerati45a16932013-04-24 10:46:17 +080061}
62
Marek Vasutb7c6ae22020-03-25 17:35:00 +010063static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
Roberto Cerati45a16932013-04-24 10:46:17 +080064{
Marek Vasutb7c6ae22020-03-25 17:35:00 +010065 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
66 writew(val, ks->iobase);
Roberto Cerati45a16932013-04-24 10:46:17 +080067}
68
69/*
70 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
71 * enabled.
72 * @ks: The chip state
73 * @wptr: buffer address to save data
74 * @len: length in byte to read
75 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +010076static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
Roberto Cerati45a16932013-04-24 10:46:17 +080077{
78 len >>= 1;
79
80 while (len--)
Marek Vasutb7c6ae22020-03-25 17:35:00 +010081 *wptr++ = readw(ks->iobase);
Roberto Cerati45a16932013-04-24 10:46:17 +080082}
83
84/*
85 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
86 * @ks: The chip information
87 * @wptr: buffer address
88 * @len: length in byte to write
89 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +010090static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
Roberto Cerati45a16932013-04-24 10:46:17 +080091{
92 len >>= 1;
93
94 while (len--)
Marek Vasutb7c6ae22020-03-25 17:35:00 +010095 writew(*wptr++, ks->iobase);
Roberto Cerati45a16932013-04-24 10:46:17 +080096}
97
Marek Vasutb7c6ae22020-03-25 17:35:00 +010098static void ks_enable_int(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +080099{
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100100 ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
Roberto Cerati45a16932013-04-24 10:46:17 +0800101}
102
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100103static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
Roberto Cerati45a16932013-04-24 10:46:17 +0800104{
Marek Vasut8ec27b02020-03-25 17:25:29 +0100105 unsigned int pmecr;
Roberto Cerati45a16932013-04-24 10:46:17 +0800106
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100107 ks_rdreg16(ks, KS_GRR);
108 pmecr = ks_rdreg16(ks, KS_PMECR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800109 pmecr &= ~PMECR_PM_MASK;
110 pmecr |= pwrmode;
111
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100112 ks_wrreg16(ks, KS_PMECR, pmecr);
Roberto Cerati45a16932013-04-24 10:46:17 +0800113}
114
115/*
116 * ks_read_config - read chip configuration of bus width.
117 * @ks: The chip information
118 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100119static void ks_read_config(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800120{
121 u16 reg_data = 0;
122
123 /* Regardless of bus width, 8 bit read should always work. */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100124 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
125 reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
Roberto Cerati45a16932013-04-24 10:46:17 +0800126
127 /* addr/data bus are multiplexed */
128 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
129
130 /*
131 * There are garbage data when reading data from QMU,
132 * depending on bus-width.
133 */
134 if (reg_data & CCR_8BIT) {
135 ks->bus_width = ENUM_BUS_8BIT;
136 ks->extra_byte = 1;
137 } else if (reg_data & CCR_16BIT) {
138 ks->bus_width = ENUM_BUS_16BIT;
139 ks->extra_byte = 2;
140 } else {
141 ks->bus_width = ENUM_BUS_32BIT;
142 ks->extra_byte = 4;
143 }
144}
145
146/*
147 * ks_soft_reset - issue one of the soft reset to the device
148 * @ks: The device state.
149 * @op: The bit(s) to set in the GRR
150 *
151 * Issue the relevant soft-reset command to the device's GRR register
152 * specified by @op.
153 *
154 * Note, the delays are in there as a caution to ensure that the reset
155 * has time to take effect and then complete. Since the datasheet does
156 * not currently specify the exact sequence, we have chosen something
157 * that seems to work with our device.
158 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100159static void ks_soft_reset(struct ks_net *ks, unsigned int op)
Roberto Cerati45a16932013-04-24 10:46:17 +0800160{
161 /* Disable interrupt first */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100162 ks_wrreg16(ks, KS_IER, 0x0000);
163 ks_wrreg16(ks, KS_GRR, op);
Roberto Cerati45a16932013-04-24 10:46:17 +0800164 mdelay(10); /* wait a short time to effect reset */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100165 ks_wrreg16(ks, KS_GRR, 0);
Roberto Cerati45a16932013-04-24 10:46:17 +0800166 mdelay(1); /* wait for condition to clear */
167}
168
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100169void ks_enable_qmu(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800170{
171 u16 w;
172
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100173 w = ks_rdreg16(ks, KS_TXCR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800174
175 /* Enables QMU Transmit (TXCR). */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100176 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
Roberto Cerati45a16932013-04-24 10:46:17 +0800177
178 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100179 w = ks_rdreg16(ks, KS_RXQCR);
180 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
Roberto Cerati45a16932013-04-24 10:46:17 +0800181
182 /* Enables QMU Receive (RXCR1). */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100183 w = ks_rdreg16(ks, KS_RXCR1);
184 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
Roberto Cerati45a16932013-04-24 10:46:17 +0800185}
186
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100187static void ks_disable_qmu(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800188{
189 u16 w;
190
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100191 w = ks_rdreg16(ks, KS_TXCR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800192
193 /* Disables QMU Transmit (TXCR). */
194 w &= ~TXCR_TXE;
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100195 ks_wrreg16(ks, KS_TXCR, w);
Roberto Cerati45a16932013-04-24 10:46:17 +0800196
197 /* Disables QMU Receive (RXCR1). */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100198 w = ks_rdreg16(ks, KS_RXCR1);
Roberto Cerati45a16932013-04-24 10:46:17 +0800199 w &= ~RXCR1_RXE;
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100200 ks_wrreg16(ks, KS_RXCR1, w);
Roberto Cerati45a16932013-04-24 10:46:17 +0800201}
202
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100203static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
Roberto Cerati45a16932013-04-24 10:46:17 +0800204{
205 u32 r = ks->extra_byte & 0x1;
206 u32 w = ks->extra_byte - r;
207
208 /* 1. set sudo DMA mode */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100209 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
210 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
Roberto Cerati45a16932013-04-24 10:46:17 +0800211
212 /*
213 * 2. read prepend data
214 *
215 * read 4 + extra bytes and discard them.
216 * extra bytes for dummy, 2 for status, 2 for len
217 */
218
219 if (r)
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100220 ks_rdreg8(ks, 0);
Roberto Cerati45a16932013-04-24 10:46:17 +0800221
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100222 ks_inblk(ks, buf, w + 2 + 2);
Roberto Cerati45a16932013-04-24 10:46:17 +0800223
224 /* 3. read pkt data */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100225 ks_inblk(ks, buf, ALIGN(len, 4));
Roberto Cerati45a16932013-04-24 10:46:17 +0800226
227 /* 4. reset sudo DMA Mode */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100228 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
Roberto Cerati45a16932013-04-24 10:46:17 +0800229}
230
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100231static int ks_rcv(struct ks_net *ks, uchar *data)
Roberto Cerati45a16932013-04-24 10:46:17 +0800232{
Marek Vasut63f22f52020-03-25 17:23:11 +0100233 u16 sts, len;
Roberto Cerati45a16932013-04-24 10:46:17 +0800234
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100235 if (!ks->rxfc)
236 ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
Roberto Cerati45a16932013-04-24 10:46:17 +0800237
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100238 if (!ks->rxfc)
239 return 0;
Roberto Cerati45a16932013-04-24 10:46:17 +0800240
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100241 /* Checking Received packet status */
242 sts = ks_rdreg16(ks, KS_RXFHSR);
243 /* Get packet len from hardware */
244 len = ks_rdreg16(ks, KS_RXFHBCR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800245
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100246 if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
247 /* read data block including CRC 4 bytes */
248 ks_read_qmu(ks, (u16 *)data, len);
249 ks->rxfc--;
250 return len - 4;
Roberto Cerati45a16932013-04-24 10:46:17 +0800251 }
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100252
253 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
254 printf(DRIVERNAME ": bad packet\n");
255 return 0;
Roberto Cerati45a16932013-04-24 10:46:17 +0800256}
257
258/*
259 * ks_read_selftest - read the selftest memory info.
260 * @ks: The device state
261 *
262 * Read and check the TX/RX memory selftest information.
263 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100264static int ks_read_selftest(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800265{
266 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
267 u16 mbir;
268 int ret = 0;
269
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100270 mbir = ks_rdreg16(ks, KS_MBIR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800271
272 if ((mbir & both_done) != both_done) {
273 printf(DRIVERNAME ": Memory selftest not finished\n");
274 return 0;
275 }
276
277 if (mbir & MBIR_TXMBFA) {
278 printf(DRIVERNAME ": TX memory selftest fails\n");
279 ret |= 1;
280 }
281
282 if (mbir & MBIR_RXMBFA) {
283 printf(DRIVERNAME ": RX memory selftest fails\n");
284 ret |= 2;
285 }
286
287 debug(DRIVERNAME ": the selftest passes\n");
288
289 return ret;
290}
291
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100292static void ks_setup(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800293{
294 u16 w;
295
296 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100297 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
Roberto Cerati45a16932013-04-24 10:46:17 +0800298
299 /* Setup Receive Frame Data Pointer Auto-Increment */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100300 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
Roberto Cerati45a16932013-04-24 10:46:17 +0800301
302 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100303 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
Roberto Cerati45a16932013-04-24 10:46:17 +0800304
305 /* Setup RxQ Command Control (RXQCR) */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100306 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
Roberto Cerati45a16932013-04-24 10:46:17 +0800307
308 /*
309 * set the force mode to half duplex, default is full duplex
310 * because if the auto-negotiation fails, most switch uses
311 * half-duplex.
312 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100313 w = ks_rdreg16(ks, KS_P1MBCR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800314 w &= ~P1MBCR_FORCE_FDX;
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100315 ks_wrreg16(ks, KS_P1MBCR, w);
Roberto Cerati45a16932013-04-24 10:46:17 +0800316
317 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100318 ks_wrreg16(ks, KS_TXCR, w);
Roberto Cerati45a16932013-04-24 10:46:17 +0800319
320 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
321
322 /* Normal mode */
323 w |= RXCR1_RXPAFMA;
324
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100325 ks_wrreg16(ks, KS_RXCR1, w);
Roberto Cerati45a16932013-04-24 10:46:17 +0800326}
327
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100328static void ks_setup_int(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800329{
Roberto Cerati45a16932013-04-24 10:46:17 +0800330 /* Clear the interrupts status of the hardware. */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100331 ks_wrreg16(ks, KS_ISR, 0xffff);
Roberto Cerati45a16932013-04-24 10:46:17 +0800332}
333
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100334static int ks8851_mll_detect_chip(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800335{
Marek Vasuteb69d8b2020-03-25 18:15:46 +0100336 unsigned short val;
Roberto Cerati45a16932013-04-24 10:46:17 +0800337
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100338 ks_read_config(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800339
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100340 val = ks_rdreg16(ks, KS_CIDER);
Roberto Cerati45a16932013-04-24 10:46:17 +0800341
342 if (val == 0xffff) {
343 /* Special case -- no chip present */
344 printf(DRIVERNAME ": is chip mounted ?\n");
345 return -1;
346 } else if ((val & 0xfff0) != CIDER_ID) {
347 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
348 return -1;
349 }
350
351 debug("Read back KS8851 id 0x%x\n", val);
352
Marek Vasuteb69d8b2020-03-25 18:15:46 +0100353 if ((val & 0xfff0) != CIDER_ID) {
Roberto Cerati45a16932013-04-24 10:46:17 +0800354 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
355 return -1;
356 }
357
Roberto Cerati45a16932013-04-24 10:46:17 +0800358 return 0;
359}
360
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100361static void ks8851_mll_reset(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800362{
363 /* wake up powermode to normal mode */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100364 ks_set_powermode(ks, PMECR_PM_NORMAL);
Roberto Cerati45a16932013-04-24 10:46:17 +0800365 mdelay(1); /* wait for normal mode to take effect */
366
367 /* Disable interrupt and reset */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100368 ks_soft_reset(ks, GRR_GSR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800369
370 /* turn off the IRQs and ack any outstanding */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100371 ks_wrreg16(ks, KS_IER, 0x0000);
372 ks_wrreg16(ks, KS_ISR, 0xffff);
Roberto Cerati45a16932013-04-24 10:46:17 +0800373
374 /* shutdown RX/TX QMU */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100375 ks_disable_qmu(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800376}
377
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100378static void ks8851_mll_phy_configure(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800379{
380 u16 data;
381
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100382 ks_setup(ks);
383 ks_setup_int(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800384
385 /* Probing the phy */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100386 data = ks_rdreg16(ks, KS_OBCR);
387 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
Roberto Cerati45a16932013-04-24 10:46:17 +0800388
389 debug(DRIVERNAME ": phy initialized\n");
390}
391
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100392static void ks8851_mll_enable(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800393{
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100394 ks_wrreg16(ks, KS_ISR, 0xffff);
395 ks_enable_int(ks);
396 ks_enable_qmu(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800397}
398
Marek Vasutf7259122020-03-25 17:54:45 +0100399static int ks8851_mll_init_common(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800400{
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100401 if (ks_read_selftest(ks)) {
Roberto Cerati45a16932013-04-24 10:46:17 +0800402 printf(DRIVERNAME ": Selftest failed\n");
403 return -1;
404 }
405
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100406 ks8851_mll_reset(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800407
408 /* Configure the PHY, initialize the link state */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100409 ks8851_mll_phy_configure(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800410
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100411 ks->rxfc = 0;
412
Roberto Cerati45a16932013-04-24 10:46:17 +0800413 /* Turn on Tx + Rx */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100414 ks8851_mll_enable(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800415
416 return 0;
417}
418
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100419static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
Roberto Cerati45a16932013-04-24 10:46:17 +0800420{
Marek Vasutb0435972020-03-25 17:18:55 +0100421 __le16 txw[2];
Roberto Cerati45a16932013-04-24 10:46:17 +0800422 /* start header at txb[0] to align txw entries */
Marek Vasutb0435972020-03-25 17:18:55 +0100423 txw[0] = 0;
424 txw[1] = cpu_to_le16(len);
Roberto Cerati45a16932013-04-24 10:46:17 +0800425
426 /* 1. set sudo-DMA mode */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100427 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
428 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
Marek Vasut8ec27b02020-03-25 17:25:29 +0100429 /* 2. write status/length info */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100430 ks_outblk(ks, txw, 4);
Roberto Cerati45a16932013-04-24 10:46:17 +0800431 /* 3. write pkt data */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100432 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
Roberto Cerati45a16932013-04-24 10:46:17 +0800433 /* 4. reset sudo-DMA mode */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100434 ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
Roberto Cerati45a16932013-04-24 10:46:17 +0800435 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100436 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
Roberto Cerati45a16932013-04-24 10:46:17 +0800437 /* 6. wait until TXQCR_METFE is auto-cleared */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100438 do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
Roberto Cerati45a16932013-04-24 10:46:17 +0800439}
440
Marek Vasutf7259122020-03-25 17:54:45 +0100441static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
Roberto Cerati45a16932013-04-24 10:46:17 +0800442{
443 u8 *data = (u8 *)packet;
444 u16 tmplen = (u16)length;
445 u16 retv;
446
447 /*
448 * Extra space are required:
449 * 4 byte for alignment, 4 for status/length, 4 for CRC
450 */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100451 retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
Roberto Cerati45a16932013-04-24 10:46:17 +0800452 if (retv >= tmplen + 12) {
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100453 ks_write_qmu(ks, data, tmplen);
Roberto Cerati45a16932013-04-24 10:46:17 +0800454 return 0;
Roberto Cerati45a16932013-04-24 10:46:17 +0800455 }
Marek Vasut8ec27b02020-03-25 17:25:29 +0100456
457 printf(DRIVERNAME ": failed to send packet: No buffer\n");
458 return -1;
Roberto Cerati45a16932013-04-24 10:46:17 +0800459}
460
Marek Vasutf7259122020-03-25 17:54:45 +0100461static void ks8851_mll_halt_common(struct ks_net *ks)
Roberto Cerati45a16932013-04-24 10:46:17 +0800462{
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100463 ks8851_mll_reset(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800464}
465
466/*
467 * Maximum receive ring size; that is, the number of packets
468 * we can buffer before overflow happens. Basically, this just
469 * needs to be enough to prevent a packet being discarded while
470 * we are processing the previous one.
471 */
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100472static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
Roberto Cerati45a16932013-04-24 10:46:17 +0800473{
474 u16 status;
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100475 int ret = 0;
Roberto Cerati45a16932013-04-24 10:46:17 +0800476
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100477 status = ks_rdreg16(ks, KS_ISR);
Roberto Cerati45a16932013-04-24 10:46:17 +0800478
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100479 ks_wrreg16(ks, KS_ISR, status);
Roberto Cerati45a16932013-04-24 10:46:17 +0800480
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100481 if (ks->rxfc || (status & IRQ_RXI))
482 ret = ks_rcv(ks, data);
Roberto Cerati45a16932013-04-24 10:46:17 +0800483
Marek Vasut8ec27b02020-03-25 17:25:29 +0100484 if (status & IRQ_LDI) {
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100485 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
Marek Vasut8ec27b02020-03-25 17:25:29 +0100486
Roberto Cerati45a16932013-04-24 10:46:17 +0800487 pmecr &= ~PMECR_WKEVT_MASK;
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100488 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
Roberto Cerati45a16932013-04-24 10:46:17 +0800489 }
490
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100491 return ret;
Roberto Cerati45a16932013-04-24 10:46:17 +0800492}
493
Marek Vasutf7259122020-03-25 17:54:45 +0100494static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
Roberto Cerati45a16932013-04-24 10:46:17 +0800495{
496 u16 addrl, addrm, addrh;
497
Marek Vasutf7259122020-03-25 17:54:45 +0100498 addrh = (enetaddr[0] << 8) | enetaddr[1];
499 addrm = (enetaddr[2] << 8) | enetaddr[3];
500 addrl = (enetaddr[4] << 8) | enetaddr[5];
Roberto Cerati45a16932013-04-24 10:46:17 +0800501
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100502 ks_wrreg16(ks, KS_MARH, addrh);
503 ks_wrreg16(ks, KS_MARM, addrm);
504 ks_wrreg16(ks, KS_MARL, addrl);
Marek Vasutf7259122020-03-25 17:54:45 +0100505}
506
Marek Vasut1d476de2020-03-25 18:00:35 +0100507#ifndef CONFIG_DM_ETH
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900508static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd)
Marek Vasutf7259122020-03-25 17:54:45 +0100509{
510 struct ks_net *ks = container_of(dev, struct ks_net, dev);
511
512 return ks8851_mll_init_common(ks);
513}
514
515static void ks8851_mll_halt(struct eth_device *dev)
516{
517 struct ks_net *ks = container_of(dev, struct ks_net, dev);
518
519 ks8851_mll_halt_common(ks);
520}
521
522static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
523{
524 struct ks_net *ks = container_of(dev, struct ks_net, dev);
525
526 return ks8851_mll_send_common(ks, packet, length);
527}
528
529static int ks8851_mll_recv(struct eth_device *dev)
530{
531 struct ks_net *ks = container_of(dev, struct ks_net, dev);
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100532 int ret;
Marek Vasutf7259122020-03-25 17:54:45 +0100533
Marek Vasut9c9f3fc2020-03-25 18:47:10 +0100534 ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
535 if (ret)
536 net_process_received_packet(net_rx_packets[0], ret);
537
538 return ret;
Marek Vasutf7259122020-03-25 17:54:45 +0100539}
540
541static int ks8851_mll_write_hwaddr(struct eth_device *dev)
542{
543 struct ks_net *ks = container_of(dev, struct ks_net, dev);
544
545 ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
Roberto Cerati45a16932013-04-24 10:46:17 +0800546
547 return 0;
548}
549
550int ks8851_mll_initialize(u8 dev_num, int base_addr)
551{
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100552 struct ks_net *ks;
Roberto Cerati45a16932013-04-24 10:46:17 +0800553
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100554 ks = calloc(1, sizeof(*ks));
555 if (!ks)
Marek Vasute3b54cd2020-03-25 16:52:38 +0100556 return -ENOMEM;
Roberto Cerati45a16932013-04-24 10:46:17 +0800557
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100558 ks->iobase = base_addr;
Roberto Cerati45a16932013-04-24 10:46:17 +0800559
560 /* Try to detect chip. Will fail if not present. */
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100561 if (ks8851_mll_detect_chip(ks)) {
562 free(ks);
Roberto Cerati45a16932013-04-24 10:46:17 +0800563 return -1;
564 }
565
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100566 ks->dev.init = ks8851_mll_init;
567 ks->dev.halt = ks8851_mll_halt;
568 ks->dev.send = ks8851_mll_send;
569 ks->dev.recv = ks8851_mll_recv;
570 ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
571 sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
Roberto Cerati45a16932013-04-24 10:46:17 +0800572
Marek Vasutb7c6ae22020-03-25 17:35:00 +0100573 eth_register(&ks->dev);
Roberto Cerati45a16932013-04-24 10:46:17 +0800574
575 return 0;
576}
Marek Vasut1d476de2020-03-25 18:00:35 +0100577#else /* ifdef CONFIG_DM_ETH */
578static int ks8851_start(struct udevice *dev)
579{
580 struct ks_net *ks = dev_get_priv(dev);
581
582 return ks8851_mll_init_common(ks);
583}
584
585static void ks8851_stop(struct udevice *dev)
586{
587 struct ks_net *ks = dev_get_priv(dev);
588
589 ks8851_mll_halt_common(ks);
590}
591
592static int ks8851_send(struct udevice *dev, void *packet, int length)
593{
594 struct ks_net *ks = dev_get_priv(dev);
595 int ret;
596
597 ret = ks8851_mll_send_common(ks, packet, length);
598
599 return ret ? 0 : -ETIMEDOUT;
600}
601
602static int ks8851_recv(struct udevice *dev, int flags, uchar **packetp)
603{
604 struct ks_net *ks = dev_get_priv(dev);
605 uchar *data = net_rx_packets[0];
606 int ret;
607
608 ret = ks8851_mll_recv_common(ks, data);
609 if (ret)
610 *packetp = (void *)data;
611
612 return ret ? ret : -EAGAIN;
613}
614
615static int ks8851_write_hwaddr(struct udevice *dev)
616{
617 struct ks_net *ks = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700618 struct eth_pdata *pdata = dev_get_plat(dev);
Marek Vasut1d476de2020-03-25 18:00:35 +0100619
620 ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
621
622 return 0;
623}
624
Marek Vasut68cbc632020-10-08 15:14:17 +0200625static int ks8851_read_rom_hwaddr(struct udevice *dev)
626{
627 struct ks_net *ks = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700628 struct eth_pdata *pdata = dev_get_plat(dev);
Marek Vasut68cbc632020-10-08 15:14:17 +0200629 u16 addrl, addrm, addrh;
630
631 /* No EEPROM means no valid MAC address. */
632 if (!(ks_rdreg16(ks, KS_CCR) & CCR_EEPROM))
633 return -EINVAL;
634
635 /*
636 * If the EEPROM contains valid MAC address, it is loaded into
637 * the NIC on power on. Read the MAC out of the NIC registers.
638 */
639 addrl = ks_rdreg16(ks, KS_MARL);
640 addrm = ks_rdreg16(ks, KS_MARM);
641 addrh = ks_rdreg16(ks, KS_MARH);
642
643 pdata->enetaddr[0] = (addrh >> 8) & 0xff;
644 pdata->enetaddr[1] = addrh & 0xff;
645 pdata->enetaddr[2] = (addrm >> 8) & 0xff;
646 pdata->enetaddr[3] = addrm & 0xff;
647 pdata->enetaddr[4] = (addrl >> 8) & 0xff;
648 pdata->enetaddr[5] = addrl & 0xff;
649
650 return !is_valid_ethaddr(pdata->enetaddr);
651}
652
Marek Vasut1d476de2020-03-25 18:00:35 +0100653static int ks8851_bind(struct udevice *dev)
654{
655 return device_set_name(dev, dev->name);
656}
657
658static int ks8851_probe(struct udevice *dev)
659{
660 struct ks_net *ks = dev_get_priv(dev);
661
662 /* Try to detect chip. Will fail if not present. */
663 ks8851_mll_detect_chip(ks);
664
665 return 0;
666}
667
Simon Glassd1998a92020-12-03 16:55:21 -0700668static int ks8851_of_to_plat(struct udevice *dev)
Marek Vasut1d476de2020-03-25 18:00:35 +0100669{
670 struct ks_net *ks = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700671 struct eth_pdata *pdata = dev_get_plat(dev);
Marek Vasut1d476de2020-03-25 18:00:35 +0100672
Masahiro Yamada25484932020-07-17 14:36:48 +0900673 pdata->iobase = dev_read_addr(dev);
Marek Vasut1d476de2020-03-25 18:00:35 +0100674 ks->iobase = pdata->iobase;
675
676 return 0;
677}
678
679static const struct eth_ops ks8851_ops = {
680 .start = ks8851_start,
681 .stop = ks8851_stop,
682 .send = ks8851_send,
683 .recv = ks8851_recv,
684 .write_hwaddr = ks8851_write_hwaddr,
Marek Vasut68cbc632020-10-08 15:14:17 +0200685 .read_rom_hwaddr = ks8851_read_rom_hwaddr,
Marek Vasut1d476de2020-03-25 18:00:35 +0100686};
687
688static const struct udevice_id ks8851_ids[] = {
689 { .compatible = "micrel,ks8851-mll" },
690 { }
691};
692
693U_BOOT_DRIVER(ks8851) = {
694 .name = "eth_ks8851",
695 .id = UCLASS_ETH,
696 .of_match = ks8851_ids,
697 .bind = ks8851_bind,
Simon Glassd1998a92020-12-03 16:55:21 -0700698 .of_to_plat = ks8851_of_to_plat,
Marek Vasut1d476de2020-03-25 18:00:35 +0100699 .probe = ks8851_probe,
700 .ops = &ks8851_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700701 .priv_auto = sizeof(struct ks_net),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700702 .plat_auto = sizeof(struct eth_pdata),
Marek Vasut1d476de2020-03-25 18:00:35 +0100703 .flags = DM_FLAG_ALLOC_PRIV_DMA,
704};
705#endif