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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
wdenk04a85b32004-04-15 18:22:41 +000010 * (C) Copyright 2003-2004 Arabella Software Ltd.
wdenkcceb8712003-06-23 18:12:28 +000011 * Yuli Barcohen <yuli@arabellasw.com>
wdenk2535d602003-07-17 23:16:40 +000012 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
wdenkef5a9672003-12-07 00:46:27 +000013 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
wdenk04a85b32004-04-15 18:22:41 +000014 * Ported to MPC8272ADS board.
wdenkcceb8712003-06-23 18:12:28 +000015 *
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020016 * Copyright (c) 2005 MontaVista Software, Inc.
Wolfgang Denk1972dc02005-09-25 16:27:55 +020017 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS
19 *
Scott Woodc73ed272009-04-02 18:20:43 -050020 * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
21 *
wdenke2211742002-11-02 23:30:20 +000022 * See file CREDITS for list of people who contributed to this
23 * project.
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of
28 * the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 * MA 02111-1307 USA
39 */
40
wdenke2211742002-11-02 23:30:20 +000041#ifndef __CONFIG_H
42#define __CONFIG_H
43
44/*
45 * High Level Configuration Options
46 * (easy to change)
47 */
48
wdenk04a85b32004-04-15 18:22:41 +000049#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
wdenke2211742002-11-02 23:30:20 +000050
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050051#define CONFIG_CPM2 1 /* Has a CPM2 */
52
wdenk901787d2005-04-03 23:22:21 +000053/*
54 * Figure out if we are booting low via flash HRCW or high via the BCSR.
55 */
56#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057# define CONFIG_SYS_LOWBOOT 1
wdenk901787d2005-04-03 23:22:21 +000058#endif
59
wdenk2535d602003-07-17 23:16:40 +000060/* ADS flavours */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
62#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
63#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
64#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
wdenk2535d602003-07-17 23:16:40 +000065
66#ifndef CONFIG_ADSTYPE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
wdenk2535d602003-07-17 23:16:40 +000068#endif /* CONFIG_ADSTYPE */
69
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
wdenk04a85b32004-04-15 18:22:41 +000071#define CONFIG_MPC8272 1
Scott Wood8701ece2009-04-03 15:26:45 -050072#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
73/*
74 * Actually MPC8275, but the code is littered with ifdefs that
75 * apply to both, or which use this ifdef to assume board-specific
76 * details. :-(
77 */
78#define CONFIG_MPC8272 1
wdenk04a85b32004-04-15 18:22:41 +000079#else
80#define CONFIG_MPC8260 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk04a85b32004-04-15 18:22:41 +000082
wdenkc837dcb2004-01-20 23:12:12 +000083#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenke2211742002-11-02 23:30:20 +000084
85/* allow serial and ethaddr to be overwritten */
86#define CONFIG_ENV_OVERWRITE
87
88/*
89 * select serial console configuration
90 *
91 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
92 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
93 * for SCC).
94 *
95 * if CONFIG_CONS_NONE is defined, then the serial console routines must
96 * defined elsewhere (for example, on the cogent platform, there are serial
97 * ports on the motherboard which are used for the serial console - see
98 * cogent/cma101/serial.[ch]).
99 */
100#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
101#define CONFIG_CONS_ON_SCC /* define if console on SCC */
102#undef CONFIG_CONS_NONE /* define if console on something else */
103#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
104
105/*
106 * select ethernet configuration
107 *
108 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
109 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
110 * for FCC)
111 *
112 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500113 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +0000114 */
115#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
116#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
117#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk48b42612003-06-19 23:01:32 +0000118
119#ifdef CONFIG_ETHER_ON_FCC
120
121#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenke2211742002-11-02 23:30:20 +0000122
wdenk04a85b32004-04-15 18:22:41 +0000123#if CONFIG_ETHER_INDEX == 1
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125# define CONFIG_SYS_PHY_ADDR 0
126# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
127# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
wdenk04a85b32004-04-15 18:22:41 +0000128
129#elif CONFIG_ETHER_INDEX == 2
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
132# define CONFIG_SYS_PHY_ADDR 3
133# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
wdenk04a85b32004-04-15 18:22:41 +0000134#else /* RxCLK is CLK13, TxCLK is CLK14 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135# define CONFIG_SYS_PHY_ADDR 0
136# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
137#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk04a85b32004-04-15 18:22:41 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
wdenke2211742002-11-02 23:30:20 +0000140
141#endif /* CONFIG_ETHER_INDEX */
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
144#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
wdenk04a85b32004-04-15 18:22:41 +0000145
wdenk48b42612003-06-19 23:01:32 +0000146#define CONFIG_MII /* MII PHY management */
147#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
148/*
149 * GPIO pins used for bit-banged MII communications
150 */
151#define MDIO_PORT 2 /* Port C */
wdenk48b42612003-06-19 23:01:32 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
154#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
155#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
wdenk04a85b32004-04-15 18:22:41 +0000156#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
158#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
159#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk48b42612003-06-19 23:01:32 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
162#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
163#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
wdenk04a85b32004-04-15 18:22:41 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
166 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
wdenk04a85b32004-04-15 18:22:41 +0000167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
169 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenk48b42612003-06-19 23:01:32 +0000170
171#define MIIDELAY udelay(1)
172
173#endif /* CONFIG_ETHER_ON_FCC */
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
wdenk04a85b32004-04-15 18:22:41 +0000176#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
wdenk2535d602003-07-17 23:16:40 +0000177#else
wdenke2211742002-11-02 23:30:20 +0000178#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
180#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000181
wdenkdb2f721f2003-03-06 00:58:30 +0000182#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200183#define CONFIG_SPD_ADDR 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000184#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000186
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200187/*PCI*/
Scott Wood8701ece2009-04-03 15:26:45 -0500188#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200189#define CONFIG_PCI
190#define CONFIG_PCI_PNP
191#define CONFIG_PCI_BOOTDELAY 0
192#define CONFIG_PCI_SCAN_SHOW
193#endif
194
wdenkdb2f721f2003-03-06 00:58:30 +0000195#ifndef CONFIG_SDRAM_PBI
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200196#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
wdenkdb2f721f2003-03-06 00:58:30 +0000197#endif
198
199#ifndef CONFIG_8260_CLKIN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
wdenk2535d602003-07-17 23:16:40 +0000201#define CONFIG_8260_CLKIN 100000000 /* in Hz */
202#else
wdenkef5a9672003-12-07 00:46:27 +0000203#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000204#endif
wdenk2535d602003-07-17 23:16:40 +0000205#endif
206
wdenke1599e82004-10-10 23:27:33 +0000207#define CONFIG_BAUDRATE 115200
wdenke2211742002-11-02 23:30:20 +0000208
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +0400209#define CONFIG_OF_LIBFDT 1
210#define CONFIG_OF_BOARD_SETUP 1
211#if defined(CONFIG_OF_LIBFDT)
212#define OF_CPU "cpu@0"
213#define OF_TBCLK (bd->bi_busfreq / 4)
214#endif
215
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500216/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500217 * BOOTP options
218 */
219#define CONFIG_BOOTP_BOOTFILESIZE
220#define CONFIG_BOOTP_BOOTPATH
221#define CONFIG_BOOTP_GATEWAY
222#define CONFIG_BOOTP_HOSTNAME
223
224
225/*
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500226 * Command line configuration.
227 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200228#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500229
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200230#define CONFIG_CMD_ASKENV
231#define CONFIG_CMD_CACHE
232#define CONFIG_CMD_CDP
233#define CONFIG_CMD_DHCP
234#define CONFIG_CMD_DIAG
235#define CONFIG_CMD_I2C
236#define CONFIG_CMD_IMMAP
237#define CONFIG_CMD_IRQ
238#define CONFIG_CMD_JFFS2
239#define CONFIG_CMD_MII
240#define CONFIG_CMD_PCI
241#define CONFIG_CMD_PING
242#define CONFIG_CMD_PORTIO
243#define CONFIG_CMD_REGINFO
244#define CONFIG_CMD_SAVES
245#define CONFIG_CMD_SDRAM
246
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500247#undef CONFIG_CMD_XIMG
wdenk2535d602003-07-17 23:16:40 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500250 #undef CONFIG_CMD_SDRAM
251 #undef CONFIG_CMD_I2C
252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500254 #undef CONFIG_CMD_SDRAM
255 #undef CONFIG_CMD_I2C
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500256
wdenk2535d602003-07-17 23:16:40 +0000257#else
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500258 #undef CONFIG_CMD_PCI
259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000261
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500262
wdenk04a85b32004-04-15 18:22:41 +0000263#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
264#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
265#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
wdenke2211742002-11-02 23:30:20 +0000266
Jon Loeliger8353e132007-07-08 14:14:17 -0500267#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000268#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
269#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
270#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
271#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
272#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
273#endif
274
wdenkef5a9672003-12-07 00:46:27 +0000275#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200276#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
wdenke2211742002-11-02 23:30:20 +0000277
278/*
279 * Miscellaneous configurable options
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_HUSH_PARSER
282#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
283#define CONFIG_SYS_LONGHELP /* undef to save memory */
284#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger8353e132007-07-08 14:14:17 -0500285#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000287#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000289#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
291#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
292#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
295#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenke2211742002-11-02 23:30:20 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_FLASH_BASE 0xff800000
304#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
305#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
306#define CONFIG_SYS_FLASH_SIZE 8
307#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
308#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
309#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
310#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
311#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenk8564acf2003-07-14 22:13:32 +0000312
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200313/*
314 * JFFS2 partitions
315 *
316 * Note: fake mtd_id used, no linux mtd map file
317 */
318#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
319#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
wdenke2211742002-11-02 23:30:20 +0000321
322/* this is stuff came out of the Motorola docs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#ifndef CONFIG_SYS_LOWBOOT
324#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenk901787d2005-04-03 23:22:21 +0000325#endif
wdenke2211742002-11-02 23:30:20 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_IMMR 0xF0000000
328#define CONFIG_SYS_BCSR 0xF4500000
Scott Wood8701ece2009-04-03 15:26:45 -0500329#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PCI_INT 0xF8200000
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200331#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_SDRAM_BASE 0x00000000
333#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
wdenke2211742002-11-02 23:30:20 +0000334
335#define RS232EN_1 0x02000002
336#define RS232EN_2 0x01000001
wdenk2535d602003-07-17 23:16:40 +0000337#define FETHIEN1 0x08000008
338#define FETH1_RST 0x04000004
wdenk04a85b32004-04-15 18:22:41 +0000339#define FETHIEN2 0x10000000
wdenk2535d602003-07-17 23:16:40 +0000340#define FETH2_RST 0x08000000
wdenk326428c2003-08-31 18:37:54 +0000341#define BCSR_PCI_MODE 0x01000000
wdenke2211742002-11-02 23:30:20 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
344#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
345#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
346#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
347#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#ifdef CONFIG_SYS_LOWBOOT
wdenk901787d2005-04-03 23:22:21 +0000350/* PQ2FADS flash HRCW = 0x0EB4B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
wdenk901787d2005-04-03 23:22:21 +0000352 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
353 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
354 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
355 )
356#else
357/* PQ2FADS BCSR HRCW = 0x0CB23645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
wdenke2211742002-11-02 23:30:20 +0000359 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
360 ( HRCW_BMS | HRCW_APPC10 ) |\
361 ( HRCW_MODCK_H0101 ) \
362 )
wdenk901787d2005-04-03 23:22:21 +0000363#endif
wdenke2211742002-11-02 23:30:20 +0000364/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_HRCW_SLAVE1 0
366#define CONFIG_SYS_HRCW_SLAVE2 0
367#define CONFIG_SYS_HRCW_SLAVE3 0
368#define CONFIG_SYS_HRCW_SLAVE4 0
369#define CONFIG_SYS_HRCW_SLAVE5 0
370#define CONFIG_SYS_HRCW_SLAVE6 0
371#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000372
373#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
374#define BOOTFLAG_WARM 0x02 /* Software reboot */
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
377#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
378# define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000379#endif
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
382#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000383
wdenkef5a9672003-12-07 00:46:27 +0000384#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
wdenkef5a9672003-12-07 00:46:27 +0000386#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
wdenkef5a9672003-12-07 00:46:27 +0000388#endif /* CONFIG_BZIP2 */
389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200391# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200392# define CONFIG_ENV_SECT_SIZE 0x40000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
wdenke2211742002-11-02 23:30:20 +0000394#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200395# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#endif /* CONFIG_SYS_RAMBOOT */
wdenke2211742002-11-02 23:30:20 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500401#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000403#endif
404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_HID0_INIT 0
406#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenke2211742002-11-02 23:30:20 +0000407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000409
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_SYPCR 0xFFFFFFC3
411#define CONFIG_SYS_BCR 0x100C0000
412#define CONFIG_SYS_SIUMCR 0x0A200000
413#define CONFIG_SYS_SCCR SCCR_DFBRG01
414#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
415#define CONFIG_SYS_OR0_PRELIM 0xFF800876
416#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
417#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
wdenke2211742002-11-02 23:30:20 +0000418
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200419/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
422#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
423#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
Scott Wood8701ece2009-04-03 15:26:45 -0500424#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
425#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
426#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200427#endif
428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_RMR RMR_CSRE
430#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
431#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
432#define CONFIG_SYS_RCCR 0
wdenk2535d602003-07-17 23:16:40 +0000433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
435#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
436#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
wdenk326428c2003-08-31 18:37:54 +0000437
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
439#define CONFIG_SYS_OR2 0xFE002EC0
440#define CONFIG_SYS_PSDMR 0x824B36A3
441#define CONFIG_SYS_PSRT 0x13
442#define CONFIG_SYS_LSDMR 0x828737A3
443#define CONFIG_SYS_LSRT 0x13
444#define CONFIG_SYS_MPTPR 0x2800
445#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
446#define CONFIG_SYS_OR2 0xFC002CC0
447#define CONFIG_SYS_PSDMR 0x834E24A3
448#define CONFIG_SYS_PSRT 0x13
449#define CONFIG_SYS_MPTPR 0x2800
wdenk2535d602003-07-17 23:16:40 +0000450#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_OR2 0xFF000CA0
452#define CONFIG_SYS_PSDMR 0x016EB452
453#define CONFIG_SYS_PSRT 0x21
454#define CONFIG_SYS_LSDMR 0x0086A522
455#define CONFIG_SYS_LSRT 0x21
456#define CONFIG_SYS_MPTPR 0x1900
457#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_RESET_ADDRESS 0x04400000
wdenke2211742002-11-02 23:30:20 +0000460
Scott Wood8701ece2009-04-03 15:26:45 -0500461#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200462
463/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
465#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
466#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200467 PICMR_PREFETCH_EN)
468
469/*
470 * These are the windows that allow the CPU to access PCI address space.
471 * All three PCI master windows, which allow the CPU to access PCI
472 * prefetch, non prefetch, and IO space (see below), must all fit within
473 * these windows.
474 */
475
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200476/*
477 * Master window that allows the CPU to access PCI Memory (prefetch).
478 * This window will be setup with the second set of Outbound ATU registers
479 * in the bridge.
480 */
481
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
483#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
484#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
485#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
486#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200487
488/*
489 * Master window that allows the CPU to access PCI Memory (non-prefetch).
490 * This window will be setup with the second set of Outbound ATU registers
491 * in the bridge.
492 */
493
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
495#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
496#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
497#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
498#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200499
500/*
501 * Master window that allows the CPU to access PCI IO space.
502 * This window will be setup with the first set of Outbound ATU registers
503 * in the bridge.
504 */
505
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
507#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
508#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
509#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
510#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200511
512
513/* PCIBR0 - for PCI IO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
515#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200516/* PCIBR1 - prefetch and non-prefetch regions joined together */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
518#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200519
520#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
521
Scott Wood42f9ebf2009-04-03 15:24:40 -0500522#define CONFIG_HAS_ETH0
523
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200525#define CONFIG_HAS_ETH1
Wolfgang Denkc2d0ab42005-09-26 00:53:02 +0200526#endif
527
Scott Woodc73ed272009-04-02 18:20:43 -0500528#define CONFIG_NETDEV eth0
529#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
530
531#define XMK_STR(x) #x
532#define MK_STR(x) XMK_STR(x)
533
534#define CONFIG_EXTRA_ENV_SETTINGS \
535 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
536 "tftpflash=tftpboot $loadaddr $uboot; " \
537 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
538 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
539 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
540 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
541 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
542 "fdtaddr=400000\0" \
543 "console=ttyCPM0\0" \
544 "setbootargs=setenv bootargs " \
545 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
546 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
548 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
549
550#define CONFIG_NFSBOOTCOMMAND \
551 "setenv rootdev /dev/nfs;" \
552 "run setipargs;" \
553 "tftp $loadaddr $bootfile;" \
554 "tftp $fdtaddr $fdtfile;" \
555 "bootm $loadaddr - $fdtaddr"
556
557#define CONFIG_RAMBOOTCOMMAND \
558 "setenv rootdev /dev/ram;" \
559 "run setbootargs;" \
560 "tftp $ramdiskaddr $ramdiskfile;" \
561 "tftp $loadaddr $bootfile;" \
562 "tftp $fdtaddr $fdtfile;" \
563 "bootm $loadaddr $ramdiskaddr $fdtaddr"
564
565#undef MK_STR
566#undef XMK_STR
567
wdenke2211742002-11-02 23:30:20 +0000568#endif /* __CONFIG_H */