Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f1d56dffd7f1a112482cdbe4e0ac2076e1eb3fe1 / . / include / configs / ti_omap5_common.h
blob: 4c3a2766ecbd73777118811eb73f8f0c42c8ba1b [file] [log] [blame]
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated.
4 * Sricharan R <r.sricharan@ti.com>
5 *
6 * Derived from OMAP4 done by:
7 * Aneesh V <aneesh@ti.com>
8 *
9 * TI OMAP5 AND DRA7XX common configuration settings
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200[diff] [blame]11 * SPDX-License-Identifier: GPL-2.0+
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]12 *
13 * For more details, please see the technical documents listed at
14 * http://www.ti.com/product/omap5432
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]15 */
16
Enric Balletbò i Serra3d657a02013-12-06 21:30:19 +0100[diff] [blame]17#ifndef __CONFIG_TI_OMAP5_COMMON_H
18#define __CONFIG_TI_OMAP5_COMMON_H
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]19
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]20/* Use General purpose timer 1 */
21#define CONFIG_SYS_TIMERBASE GPT2_BASE
22
Tom Rini078aa4f2013-08-20 08:53:52 -0400[diff] [blame]23/*
24 * For the DDR timing information we can either dynamically determine
25 * the timings to use or use pre-determined timings (based on using the
26 * dynamic method. Default to the static timing infomation.
27 */
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]28#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]29#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
30#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
31#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
32#endif
33
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]34#define CONFIG_PALMAS_POWER
Tom Rinia8017572013-08-09 11:22:18 -0400[diff] [blame]35
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]36#include <asm/arch/cpu.h>
37#include <asm/arch/omap.h>
38
Nishanth Menon9a0f4002015-07-22 18:05:41 -0500[diff] [blame]39#include <configs/ti_armv7_omap.h>
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]40
41/*
42 * Hardware drivers
43 */
Thomas Chouc7b96862015-11-19 21:48:12 +0800[diff] [blame]44#define CONFIG_SYS_NS16550_CLK 48000000
Lokesh Vutla0a3f4072017-02-10 20:37:20 +0530[diff] [blame]45#if !defined(CONFIG_DM_SERIAL)
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]46#define CONFIG_SYS_NS16550_SERIAL
47#define CONFIG_SYS_NS16550_REG_SIZE (-4)
Tom Rini01e870b2015-09-17 16:47:04 -0400[diff] [blame]48#endif
Tom Rinidd2445e2013-04-05 06:21:46 +0000[diff] [blame]49
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]50/*
51 * Environment setup
52 */
Tom Rini9552ee32013-04-05 06:21:45 +0000[diff] [blame]53
Kishon Vijay Abraham I7a5a3e32015-02-23 18:40:20 +0530[diff] [blame]54#ifndef DFUARGS
55#define DFUARGS
56#endif
57
Semen Protsenko4fd79ac2017-06-14 21:34:23 +0300[diff] [blame]58#include <environment/ti/boot.h>
Sekhar Nori88fdfcd2017-04-06 14:52:56 +0530[diff] [blame]59#include <environment/ti/mmc.h>
60
Lokesh Vutla4ec3f6e2014-07-14 19:57:58 +0530[diff] [blame]61#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]62#define CONFIG_EXTRA_ENV_SETTINGS \
Tom Rinifb3ad9b2014-03-28 15:03:29 -0400[diff] [blame]63 DEFAULT_LINUX_BOOT_ENV \
Lokesh Vutla85d17be2015-08-28 13:35:07 +0530[diff] [blame]64 DEFAULT_MMC_TI_ARGS \
Lokesh Vutla1e93cc82016-11-29 11:58:00 +0530[diff] [blame]65 DEFAULT_FIT_TI_ARGS \
Semen Protsenko4fd79ac2017-06-14 21:34:23 +0300[diff] [blame]66 DEFAULT_COMMON_BOOT_TI_ARGS \
67 DEFAULT_FDT_TI_ARGS \
Kishon Vijay Abraham I7a5a3e32015-02-23 18:40:20 +0530[diff] [blame]68 DFUARGS \
Cooper Jr., Franklin23208662015-04-21 07:51:04 -0500[diff] [blame]69 NETARGS \
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]70
Tom Rini078aa4f2013-08-20 08:53:52 -0400[diff] [blame]71/*
72 * SPL related defines. The Public RAM memory map the ROM defines the
Daniel Allredb9b84032016-05-19 19:10:50 -0500[diff] [blame]73 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
74 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
75 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
Tom Rini078aa4f2013-08-20 08:53:52 -0400[diff] [blame]76 * print some information.
77 */
Daniel Allredb9b84032016-05-19 19:10:50 -0500[diff] [blame]78#ifdef CONFIG_TI_SECURE_DEVICE
79/*
80 * For memory booting on HS parts, the first 4KB of the internal RAM is
81 * reserved for secure world use and the flash loader image is
82 * preceded by a secure certificate. The SPL will therefore run in internal
83 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
84 */
85#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
86#define CONFIG_SPL_TEXT_BASE 0x40301350
Daniel Allred32d333f2016-09-02 00:40:23 -0500[diff] [blame]87/* If no specific start address is specified then the secure EMIF
88 * region will be placed at the end of the DDR space. In order to prevent
89 * the main u-boot relocation from clobbering that memory and causing a
90 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
91 */
92#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
93#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
94#endif
Daniel Allredb9b84032016-05-19 19:10:50 -0500[diff] [blame]95#else
96/*
97 * For all booting on GP parts, the flash loader image is
98 * downloaded into internal RAM at address 0x40300000.
99 */
100#define CONFIG_SPL_TEXT_BASE 0x40300000
101#endif
102
Tom Rini983e3702016-11-07 21:34:54 -0500[diff] [blame]103#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
Tom Rinid3289aa2014-04-03 07:52:53 -0400[diff] [blame]104#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
105 (128 << 20))
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000[diff] [blame]106
Enric Balletbò i Serra70e71b62013-12-06 21:30:20 +0100[diff] [blame]107#ifdef CONFIG_NAND
108#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
109#endif
110
Mugunthan V N136b1012015-09-29 14:42:26 +0530[diff] [blame]111#ifdef CONFIG_SPL_BUILD
Mugunthan V N30a0cdb2015-12-24 16:08:18 +0530[diff] [blame]112#undef CONFIG_TIMER
Mugunthan V N136b1012015-09-29 14:42:26 +0530[diff] [blame]113#endif
114
Enric Balletbò i Serra3d657a02013-12-06 21:30:19 +0100[diff] [blame]115#endif /* __CONFIG_TI_OMAP5_COMMON_H */