blob: aa942ea6499026963a13ecd45940a76a00a3cf75 [file] [log] [blame]
Udit Kumardb7af512023-05-11 14:47:48 +05301.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2.. sectionauthor:: Udit Kumar <u-kumar1@ti.com>
3
4J7200 Platforms
5===============
6
7Introduction:
8-------------
9The J7200 family of SoCs are part of K3 Multicore SoC architecture platform
10targeting automotive applications. They are designed as a low power, high
11performance and highly integrated device architecture, adding significant
12enhancement on processing power, graphics capability, video and imaging
13processing, virtualization and coherent memory support.
14
15The device is partitioned into three functional domains, each containing
16specific processing cores and peripherals:
17
181. Wake-up (WKUP) domain:
19 * Device Management and Security Controller (DMSC)
20
212. Microcontroller (MCU) domain:
22 * Dual Core ARM Cortex-R5F processor
23
243. MAIN domain:
25 * Dual core 64-bit ARM Cortex-A72
26
27More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1
28
29Boot Flow:
30----------
31Below is the pictorial representation of boot flow:
32
Nishanth Menon68b3baa2023-07-27 13:58:45 -050033.. image:: img/boot_diagram_k3_current.svg
Udit Kumardb7af512023-05-11 14:47:48 +053034
35- Here DMSC acts as master and provides all the critical services. R5/A72
36 requests DMSC to get these services done as shown in the above diagram.
37
38Sources:
39--------
Udit Kumardb7af512023-05-11 14:47:48 +053040
Nishanth Menoncce3e7a2023-07-27 13:58:44 -050041.. include:: k3.rst
42 :start-after: .. k3_rst_include_start_boot_sources
43 :end-before: .. k3_rst_include_end_boot_sources
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +053044
Udit Kumardb7af512023-05-11 14:47:48 +053045Build procedure:
46----------------
Nishanth Menonc727b812023-07-27 13:58:48 -0500470. Setup the environment variables:
Udit Kumardb7af512023-05-11 14:47:48 +053048
Nishanth Menonc727b812023-07-27 13:58:48 -050049.. include:: k3.rst
50 :start-after: .. k3_rst_include_start_common_env_vars_desc
51 :end-before: .. k3_rst_include_end_common_env_vars_desc
52
53.. include:: k3.rst
54 :start-after: .. k3_rst_include_start_board_env_vars_desc
55 :end-before: .. k3_rst_include_end_board_env_vars_desc
56
57Set the variables corresponding to this platform:
58
59.. include:: k3.rst
60 :start-after: .. k3_rst_include_start_common_env_vars_defn
61 :end-before: .. k3_rst_include_end_common_env_vars_defn
Udit Kumardb7af512023-05-11 14:47:48 +053062.. code-block:: bash
63
Nishanth Menonc727b812023-07-27 13:58:48 -050064 $ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
65 $ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
66 $ export TFA_BOARD=generic
67 $ # we dont use any extra TFA parameters
68 $ unset TFA_EXTRA_ARGS
69 $ export OPTEE_PLATFORM=k3-j7200
70 $ # we dont use any extra OP-TEE parameters
71 $ unset OPTEE_EXTRA_ARGS
72
73.. j7200_evm_rst_include_start_build_steps
74
751. Trusted Firmware-A:
76
77.. include:: k3.rst
78 :start-after: .. k3_rst_include_start_build_steps_tfa
79 :end-before: .. k3_rst_include_end_build_steps_tfa
80
Udit Kumardb7af512023-05-11 14:47:48 +053081
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530822. OP-TEE:
Udit Kumardb7af512023-05-11 14:47:48 +053083
Nishanth Menonc727b812023-07-27 13:58:48 -050084.. include:: k3.rst
85 :start-after: .. k3_rst_include_start_build_steps_optee
86 :end-before: .. k3_rst_include_end_build_steps_optee
Udit Kumardb7af512023-05-11 14:47:48 +053087
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530883. U-Boot:
Udit Kumardb7af512023-05-11 14:47:48 +053089
90* 4.1 R5:
91
Nishanth Menonc727b812023-07-27 13:58:48 -050092.. include:: k3.rst
93 :start-after: .. k3_rst_include_start_build_steps_spl_r5
94 :end-before: .. k3_rst_include_end_build_steps_spl_r5
Udit Kumardb7af512023-05-11 14:47:48 +053095
96* 4.2 A72:
97
Nishanth Menonc727b812023-07-27 13:58:48 -050098.. include:: k3.rst
99 :start-after: .. k3_rst_include_start_build_steps_uboot
100 :end-before: .. k3_rst_include_end_build_steps_uboot
101.. j7200_evm_rst_include_end_build_steps
Udit Kumardb7af512023-05-11 14:47:48 +0530102
103Target Images
104--------------
Tom Rinif687c8f2023-07-25 12:44:16 -0400105In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
106variant (GP, HS-FS, HS-SE) requires a different source for these files.
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530107
108 - GP
109
110 * tiboot3-j7200-gp-evm.bin from step 4.1
111 * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
112
113 - HS-FS
114
115 * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1
116 * tispl.bin, u-boot.img from step 4.2
117
118 - HS-SE
119
120 * tiboot3-j7200_sr2-hs-evm.bin from step 4.1
121 * tispl.bin, u-boot.img from step 4.2
Udit Kumardb7af512023-05-11 14:47:48 +0530122
123Image formats:
124--------------
125
Nishanth Menonf4ade092023-07-27 13:58:49 -0500126- tiboot3.bin
Udit Kumardb7af512023-05-11 14:47:48 +0530127
Nishanth Menonf4ade092023-07-27 13:58:49 -0500128.. image:: img/j7200_tiboot3.bin.svg
Udit Kumardb7af512023-05-11 14:47:48 +0530129
130- tispl.bin
131
Nishanth Menonf4ade092023-07-27 13:58:49 -0500132.. image:: img/dm_tispl.bin.svg
Udit Kumardb7af512023-05-11 14:47:48 +0530133
Udit Kumardb7af512023-05-11 14:47:48 +0530134
135
136Switch Setting for Boot Mode
137----------------------------
138
139Boot Mode pins provide means to select the boot mode and options before the
140device is powered up. After every POR, they are the main source to populate
141the Boot Parameter Tables.
142
143The following table shows some common boot modes used on J7200 platform. More
144details can be found in the Technical Reference Manual:
145https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section.
146
147
148*Boot Modes*
149
150============ ============= =============
151Switch Label SW9: 12345678 SW8: 12345678
152============ ============= =============
153SD 00000000 10000010
154EMMC 01000000 10000000
155OSPI 01000000 00000110
156UART 01110000 00000000
157USB DFU 00100000 10000000
158============ ============= =============
159
160For SW8 and SW9, the switch state in the "ON" position = 1.
161
162eMMC:
163-----
164ROM supports booting from eMMC raw read or UDA FS mode.
165
166Below is memory layout in case of booting from
167boot 0/1 partition in raw mode.
168
169Current allocated size for tiboot3 size is 1MB, tispl is 2MB.
170
171Size of u-boot.img is taken 4MB for refernece,
172But this is subject to change depending upon atf, optee size
173
174.. code-block:: console
175
176 boot0/1 partition (8 MB) user partition
177 0x0+----------------------------------+ 0x0+------------------------+
178 | tiboot3.bin (1 MB) | | |
179 0x800+----------------------------------+ | |
180 | tispl.bin (2 MB) | | |
181 0x1800+----------------------------------+ | |
182 | u-boot.img (4MB) | | |
183 0x3800+----------------------------------+ | |
184 | | | |
185 0x3900+ environment | | |
186 | | | |
187 0x3A00+----------------------------------+ +-------------------------+
188
189In case of UDA FS mode booting, following is layout.
190
191All boot images tiboot3.bin, tispl and u-boot should be written to
192fat formatted UDA FS as file.
193
194.. code-block:: console
195
196 boot0/1 partition (8 MB) user partition
197 0x0+---------------------------------+ 0x0+-------------------------+
198 | | | tiboot3.bin* |
199 0x800+----------------------------------+ | |
200 | | | tispl.bin |
201 0x1800+----------------------------------+ | |
202 | | | u-boot.img |
203 0x3800+----------------------------------+ | |
204 | | | |
205 0x3900+ | | environment |
206 | | | |
207 0x3A00+----------------------------------+ +-------------------------+
208
209
210
211In case of booting from eMMC, write above images into raw or UDA FS.
212and set mmc partconf accordingly.