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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
Michal Simekf4c7a4a2018-06-04 14:57:34 +020016static long do_fpga_get_device(char *arg)
17{
18 long dev = FPGA_INVALID_DEVICE;
19 char *devstr = env_get("fpga");
20
21 if (devstr)
22 /* Should be strtol to handle -1 cases */
23 dev = simple_strtol(devstr, NULL, 16);
24
25 if (arg)
26 dev = simple_strtol(arg, NULL, 16);
27
28 debug("%s: device = %ld\n", __func__, dev);
29
30 return dev;
31}
32
wdenk4a9cbbe2002-08-27 09:48:53 +000033/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010034enum {
35 FPGA_NONE = -1,
Michal Simek5cf22282017-01-06 11:20:54 +010036 FPGA_LOAD,
37 FPGA_LOADB,
38 FPGA_DUMP,
39 FPGA_LOADMK,
40 FPGA_LOADP,
41 FPGA_LOADBP,
42 FPGA_LOADFS,
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053043 FPGA_LOADS,
Michal Simek5cf22282017-01-06 11:20:54 +010044};
wdenk4a9cbbe2002-08-27 09:48:53 +000045
Michal Simek323fe382018-05-30 10:00:40 +020046/*
47 * Map op to supported operations. We don't use a table since we
48 * would just have to relocate it from flash anyway.
49 */
50static int fpga_get_op(char *opstr)
51{
52 int op = FPGA_NONE;
53
Michal Simekf4c7a4a2018-06-04 14:57:34 +020054 if (!strcmp("loadb", opstr))
Michal Simek323fe382018-05-30 10:00:40 +020055 op = FPGA_LOADB;
56 else if (!strcmp("load", opstr))
57 op = FPGA_LOAD;
58#if defined(CONFIG_CMD_FPGA_LOADP)
59 else if (!strcmp("loadp", opstr))
60 op = FPGA_LOADP;
61#endif
62#if defined(CONFIG_CMD_FPGA_LOADBP)
63 else if (!strcmp("loadbp", opstr))
64 op = FPGA_LOADBP;
65#endif
66#if defined(CONFIG_CMD_FPGA_LOADFS)
67 else if (!strcmp("loadfs", opstr))
68 op = FPGA_LOADFS;
69#endif
70#if defined(CONFIG_CMD_FPGA_LOADMK)
71 else if (!strcmp("loadmk", opstr))
72 op = FPGA_LOADMK;
73#endif
74 else if (!strcmp("dump", opstr))
75 op = FPGA_DUMP;
76#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
77 else if (!strcmp("loads", opstr))
78 op = FPGA_LOADS;
79#endif
80
81 return op;
82}
83
wdenk4a9cbbe2002-08-27 09:48:53 +000084/* ------------------------------------------------------------------------- */
85/* command form:
86 * fpga <op> <device number> <data addr> <datasize>
87 * where op is 'load', 'dump', or 'info'
88 * If there is no device number field, the fpga environment variable is used.
89 * If there is no data addr field, the fpgadata environment variable is used.
90 * The info command requires no data address field.
91 */
Michal Simekfc598412013-04-26 13:10:07 +020092int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000093{
wdenkd4ca31c2004-01-02 14:00:00 +000094 int op, dev = FPGA_INVALID_DEVICE;
95 size_t data_size = 0;
96 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -060097 char *devstr = env_get("fpga");
98 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +000099 int rc = FPGA_FAIL;
Michal Simekfc598412013-04-26 13:10:07 +0200100#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100101 const char *fit_uname = NULL;
102 ulong fit_addr;
103#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530104#if defined(CONFIG_CMD_FPGA_LOADFS)
105 fpga_fs_info fpga_fsinfo;
106 fpga_fsinfo.fstype = FS_TYPE_ANY;
107#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530108#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
109 struct fpga_secure_info fpga_sec_info;
110
111 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
112#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000113
wdenkd4ca31c2004-01-02 14:00:00 +0000114 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +0200115 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +0000116 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +0200117 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000118
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530119 if (argc > 9 || argc < 2) {
120 debug("%s: Too many or too few args (%d)\n", __func__, argc);
121 return CMD_RET_USAGE;
122 }
123
Michal Simek323fe382018-05-30 10:00:40 +0200124 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530125
126 switch (op) {
Michal Simek55010962018-05-30 09:57:42 +0200127 case FPGA_NONE:
128 printf("Unknown fpga operation \"%s\"\n", argv[1]);
129 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530130#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530131 case FPGA_LOADFS:
132 if (argc < 9)
133 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530134 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530135 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530136 fpga_fsinfo.interface = argv[6];
137 fpga_fsinfo.dev_part = argv[7];
138 fpga_fsinfo.filename = argv[8];
Michal Simek44d839b2018-05-30 11:18:38 +0200139
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530140 argc = 5;
141 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530142#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530143#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
144 case FPGA_LOADS:
145 if (argc < 7)
146 return CMD_RET_USAGE;
147 if (argc == 8)
148 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
149 simple_strtoull(argv[7],
150 NULL, 16);
151 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
152 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +0200153
154 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
155 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
156 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
157 return CMD_RET_USAGE;
158 }
159
160 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
161 !fpga_sec_info.userkey_addr) {
162 puts("ERR: User key not provided\n");
163 return CMD_RET_USAGE;
164 }
165
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530166 argc = 5;
167 break;
168#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530169 default:
170 break;
171 }
172
173 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +0000174 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +0200175 data_size = simple_strtoul(argv[4], NULL, 16);
Michal Simek5cadab62018-05-30 11:28:57 +0200176 if (!data_size) {
177 puts("Zero data_size\n");
178 return CMD_RET_USAGE;
179 }
wdenkd4ca31c2004-01-02 14:00:00 +0000180 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100181#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200182 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
183 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100184 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200185 debug("* fpga: subimage '%s' from FIT image ",
186 fit_uname);
187 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100188 } else
189#endif
190 {
Michal Simekfc598412013-04-26 13:10:07 +0200191 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000192 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200193 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100194 }
Michal Simek455ad582016-01-05 13:51:48 +0100195 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Michal Simek5cadab62018-05-30 11:28:57 +0200196 if (!fpga_data) {
197 puts("Zero fpga_data address\n");
198 return CMD_RET_USAGE;
199 }
wdenkd4ca31c2004-01-02 14:00:00 +0000200 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200201 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000202 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000203 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000204
Stefano Babica790b5b2010-10-19 09:22:52 +0200205 if (dev == FPGA_INVALID_DEVICE) {
206 puts("FPGA device not specified\n");
Michal Simekccd65202018-05-30 10:04:34 +0200207 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200208 }
209
210 switch (op) {
wdenkd4ca31c2004-01-02 14:00:00 +0000211 case FPGA_LOAD:
Michal Simek7a78bd22014-05-02 14:09:30 +0200212 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenkd4ca31c2004-01-02 14:00:00 +0000213 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000214
Michal Simek67193862014-05-02 13:43:39 +0200215#if defined(CONFIG_CMD_FPGA_LOADP)
216 case FPGA_LOADP:
217 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
218 break;
219#endif
220
wdenk30ce5ab2005-01-09 18:12:51 +0000221 case FPGA_LOADB:
Michal Simek7a78bd22014-05-02 14:09:30 +0200222 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk30ce5ab2005-01-09 18:12:51 +0000223 break;
224
Michal Simek67193862014-05-02 13:43:39 +0200225#if defined(CONFIG_CMD_FPGA_LOADBP)
226 case FPGA_LOADBP:
227 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
228 break;
229#endif
230
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530231#if defined(CONFIG_CMD_FPGA_LOADFS)
232 case FPGA_LOADFS:
233 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
234 break;
235#endif
236
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530237#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
238 case FPGA_LOADS:
239 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
240 break;
241#endif
242
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530243#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200244 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200245 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200246#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100247 case IMAGE_FORMAT_LEGACY:
248 {
Michal Simekfc598412013-04-26 13:10:07 +0200249 image_header_t *hdr =
250 (image_header_t *)fpga_data;
251 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200252 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200253
Michal Simek32d7cdd2013-10-04 10:51:01 +0200254 comp = image_get_comp(hdr);
255 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200256#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200257 ulong image_buf = image_get_data(hdr);
258 data = image_get_load(hdr);
259 ulong image_size = ~0UL;
260
261 if (gunzip((void *)data, ~0UL,
262 (void *)image_buf,
263 &image_size) != 0) {
264 puts("GUNZIP: error\n");
265 return 1;
266 }
267 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200268#else
269 puts("Gunzip image is not supported\n");
270 return 1;
271#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200272 } else {
273 data = (ulong)image_get_data(hdr);
274 data_size = image_get_data_size(hdr);
275 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200276 rc = fpga_load(dev, (void *)data, data_size,
277 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200278 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100279 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200280#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100281#if defined(CONFIG_FIT)
282 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100283 {
284 const void *fit_hdr = (const void *)fpga_data;
285 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000286 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100287
288 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200289 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100290 return 1;
291 }
292
Michal Simekfc598412013-04-26 13:10:07 +0200293 if (!fit_check_format(fit_hdr)) {
294 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100295 return 1;
296 }
297
298 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200299 noffset = fit_image_get_node(fit_hdr,
300 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100301 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200302 printf("Can't find '%s' FIT subimage\n",
303 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100304 return 1;
305 }
306
307 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000308 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100309 puts ("Bad Data Hash\n");
310 return 1;
311 }
312
313 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200314 if (fit_image_get_data(fit_hdr, noffset,
315 &fit_data, &data_size)) {
316 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100317 return 1;
318 }
319
Michal Simek7a78bd22014-05-02 14:09:30 +0200320 rc = fpga_load(dev, fit_data, data_size,
321 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100322 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100323 break;
324#endif
325 default:
Michal Simekfc598412013-04-26 13:10:07 +0200326 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100327 rc = FPGA_FAIL;
328 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200329 }
330 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530331#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200332
wdenkd4ca31c2004-01-02 14:00:00 +0000333 case FPGA_DUMP:
Michal Simekfc598412013-04-26 13:10:07 +0200334 rc = fpga_dump(dev, fpga_data, data_size);
wdenkd4ca31c2004-01-02 14:00:00 +0000335 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000336
wdenkd4ca31c2004-01-02 14:00:00 +0000337 default:
Michal Simekfc598412013-04-26 13:10:07 +0200338 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000339 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000340 }
Michal Simekfc598412013-04-26 13:10:07 +0200341 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000342}
343
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200344static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
345 char * const argv[])
346{
347 long dev = do_fpga_get_device(argv[0]);
348
349 return fpga_info(dev);
350}
351
Michal Simek9657d972018-06-04 14:55:20 +0200352static cmd_tbl_t fpga_commands[] = {
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200353 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek9657d972018-06-04 14:55:20 +0200354};
355
356static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
357 char *const argv[])
358{
359 cmd_tbl_t *fpga_cmd;
360 int ret;
361
362 if (argc < 2)
363 return CMD_RET_USAGE;
364
365 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
366 ARRAY_SIZE(fpga_commands));
367
368 /* This should be removed when all functions are converted */
369 if (!fpga_cmd)
370 return do_fpga(cmdtp, flag, argc, argv);
371
372 /* FIXME This can't be reached till all functions are converted */
373 if (!fpga_cmd) {
374 debug("fpga: non existing command\n");
375 return CMD_RET_USAGE;
376 }
377
378 argc -= 2;
379 argv += 2;
380
381 if (argc > fpga_cmd->maxargs) {
382 debug("fpga: more parameters passed\n");
383 return CMD_RET_USAGE;
384 }
385
386 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
387
388 return cmd_process_error(fpga_cmd, ret);
389}
390
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530391#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9657d972018-06-04 14:55:20 +0200392U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530393#else
Michal Simek9657d972018-06-04 14:55:20 +0200394U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530395#endif
Michal Simekfc598412013-04-26 13:10:07 +0200396 "loadable FPGA image support",
397 "[operation type] [device number] [image address] [image size]\n"
398 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100399 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200400 " info\t[dev]\t\t\tlist known device information\n"
401 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200402#if defined(CONFIG_CMD_FPGA_LOADP)
403 " loadp\t[dev] [address] [size]\t"
404 "Load device from memory buffer with partial bitstream\n"
405#endif
Michal Simekfc598412013-04-26 13:10:07 +0200406 " loadb\t[dev] [address] [size]\t"
407 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200408#if defined(CONFIG_CMD_FPGA_LOADBP)
409 " loadbp\t[dev] [address] [size]\t"
410 "Load device from bitstream buffer with partial bitstream"
411 "(Xilinx only)\n"
412#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530413#if defined(CONFIG_CMD_FPGA_LOADFS)
414 "Load device from filesystem (FAT by default) (Xilinx only)\n"
415 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
416 " [<dev[:part]>] <filename>\n"
417#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530418#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200419 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100420#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200421 "\n"
422 "\tFor loadmk operating on FIT format uImage address must include\n"
423 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100424#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530425#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530426#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
427 "Load encrypted bitstream (Xilinx only)\n"
428 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
429 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
430 "Loads the secure bistreams(authenticated/encrypted/both\n"
431 "authenticated and encrypted) of [size] from [address].\n"
432 "The auth-OCM/DDR flag specifies to perform authentication\n"
433 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
434 "The enc flag specifies which key to be used for decryption\n"
435 "0-device key, 1-user key, 2-no encryption.\n"
436 "The optional Userkey address specifies from which address key\n"
437 "has to be used for decryption if user key is selected.\n"
438 "NOTE: the sceure bitstream has to be created using xilinx\n"
439 "bootgen tool only.\n"
440#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100441);