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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f5c48644ba252c4bb68dce25d1bfc86368dc324f / . / arch / arm / dts / zynqmp-zcu102-revA.dts
blob: 78110c490e8d5bdba8719115e331a594bd5729ff [file] [log] [blame]
Michal Simek18a952c2018-03-27 10:36:39 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]2/*
Michal Simek23b34d12017-11-02 10:21:08 +0100[diff] [blame]3 * dts file for Xilinx ZynqMP ZCU102 RevA
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]4 *
Michal Simek18a952c2018-03-27 10:36:39 +0200[diff] [blame]5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
Michal Simekee4983f2017-12-08 14:50:42 +0100[diff] [blame]13#include "zynqmp-clk-ccf.dtsi"
Michal Simek9d928f02018-03-27 12:13:13 +0200[diff] [blame]14#include <dt-bindings/input/input.h>
Michal Simeke4e7f2f2016-05-25 20:09:35 +0200[diff] [blame]15#include <dt-bindings/gpio/gpio.h>
Michal Simekd70cb512017-12-01 15:50:31 +0100[diff] [blame]16#include <dt-bindings/phy/phy.h>
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]17
18/ {
19 model = "ZynqMP ZCU102 RevA";
Michal Simekbe463452017-07-20 12:38:27 +0200[diff] [blame]20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &uart1;
Michal Simek69d09dd2016-09-09 08:46:39 +0200[diff] [blame]31 serial2 = &dcc;
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek8bdad432019-01-18 09:10:39 +0100[diff] [blame]39 xlnx,eeprom = &eeprom;
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]40 };
41
Michal Simekc926e6f2016-11-11 13:21:04 +0100[diff] [blame]42 memory@0 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 };
Michal Simek4ae78e52016-04-20 13:12:25 +0200[diff] [blame]46
Michal Simeke4e7f2f2016-05-25 20:09:35 +0200[diff] [blame]47 gpio-keys {
48 compatible = "gpio-keys";
Michal Simeke4e7f2f2016-05-25 20:09:35 +0200[diff] [blame]49 autorepeat;
50 sw19 {
51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
Michal Simek9d928f02018-03-27 12:13:13 +0200[diff] [blame]53 linux,code = <KEY_DOWN>;
Michal Simeke4e7f2f2016-05-25 20:09:35 +0200[diff] [blame]54 gpio-key,wakeup;
55 autorepeat;
56 };
57 };
58
Michal Simek4ae78e52016-04-20 13:12:25 +0200[diff] [blame]59 leds {
60 compatible = "gpio-leds";
61 heartbeat_led {
62 label = "heartbeat";
Chirag Parekhd801ce52017-01-25 07:00:57 -0800[diff] [blame]63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
Michal Simek4ae78e52016-04-20 13:12:25 +0200[diff] [blame]64 linux,default-trigger = "heartbeat";
65 };
66 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]67
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71 };
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75 };
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79 };
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83 };
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87 };
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91 };
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95 };
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99 };
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103 };
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107 };
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111 };
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115 };
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119 };
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123 };
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127 };
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131 };
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135 };
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 };
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]140};
141
142&can1 {
143 status = "okay";
144};
145
Michal Simek69d09dd2016-09-09 08:46:39 +0200[diff] [blame]146&dcc {
147 status = "okay";
148};
149
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]150&fpd_dma_chan1 {
151 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]152};
153
154&fpd_dma_chan2 {
155 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]156};
157
158&fpd_dma_chan3 {
159 status = "okay";
160};
161
162&fpd_dma_chan4 {
163 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]164};
165
166&fpd_dma_chan5 {
167 status = "okay";
168};
169
170&fpd_dma_chan6 {
171 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]172};
173
174&fpd_dma_chan7 {
175 status = "okay";
176};
177
178&fpd_dma_chan8 {
179 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]180};
181
182&gem3 {
183 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]184 phy-handle = <&phy0>;
185 phy-mode = "rgmii-id";
Michal Simek2975a422019-08-08 12:44:22 +0200[diff] [blame]186 phy0: ethernet-phy@21 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]187 reg = <21>;
188 ti,rx-internal-delay = <0x8>;
189 ti,tx-internal-delay = <0xa>;
190 ti,fifo-depth = <0x1>;
Harini Katakam631d9a92019-02-13 17:02:21 +0530[diff] [blame]191 ti,dp83867-rxctrl-strap-quirk;
Harini Katakam26b2c682019-03-13 19:41:19 +0530[diff] [blame]192 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]193 };
194};
195
196&gpio {
197 status = "okay";
198};
199
200&gpu {
201 status = "okay";
202};
203
204&i2c0 {
205 status = "okay";
206 clock-frequency = <400000>;
207
208 tca6416_u97: gpio@20 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]209 compatible = "ti,tca6416";
210 reg = <0x20>;
Michal Simekdb2d6222019-03-12 10:15:27 +0100[diff] [blame]211 gpio-controller; /* IRQ not connected */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]212 #gpio-cells = <2>;
Michal Simekdb2d6222019-03-12 10:15:27 +0100[diff] [blame]213 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
214 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
215 "", "", "", "", "", "", "", "", "";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]216 gtr_sel0 {
217 gpio-hog;
218 gpios = <0 0>;
Bharat Kumar Gogadaf811eca2017-01-30 12:06:02 +0530[diff] [blame]219 output-low; /* PCIE = 0, DP = 1 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]220 line-name = "sel0";
221 };
222 gtr_sel1 {
223 gpio-hog;
224 gpios = <1 0>;
225 output-high; /* PCIE = 0, DP = 1 */
226 line-name = "sel1";
227 };
228 gtr_sel2 {
229 gpio-hog;
230 gpios = <2 0>;
231 output-high; /* PCIE = 0, USB0 = 1 */
232 line-name = "sel2";
233 };
234 gtr_sel3 {
235 gpio-hog;
236 gpios = <3 0>;
237 output-high; /* PCIE = 0, SATA = 1 */
238 line-name = "sel3";
239 };
240 };
241
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]242 tca6416_u61: gpio@21 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]243 compatible = "ti,tca6416";
244 reg = <0x21>;
Michal Simekdb2d6222019-03-12 10:15:27 +0100[diff] [blame]245 gpio-controller; /* IRQ not connected */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]246 #gpio-cells = <2>;
Michal Simekdb2d6222019-03-12 10:15:27 +0100[diff] [blame]247 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
248 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
249 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
250 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]251 };
252
Michal Simekba7b6df2018-03-27 10:38:08 +0200[diff] [blame]253 i2c-mux@75 { /* u60 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]254 compatible = "nxp,pca9544";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <0x75>;
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]258 i2c@0 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <0>;
262 /* PS_PMBUS */
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]263 u76: ina226@40 { /* u76 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]264 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]265 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]266 label = "ina226-u76";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]267 reg = <0x40>;
268 shunt-resistor = <5000>;
269 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]270 u77: ina226@41 { /* u77 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]271 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]272 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]273 label = "ina226-u77";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]274 reg = <0x41>;
275 shunt-resistor = <5000>;
276 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]277 u78: ina226@42 { /* u78 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]278 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]279 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]280 label = "ina226-u78";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]281 reg = <0x42>;
282 shunt-resistor = <5000>;
283 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]284 u87: ina226@43 { /* u87 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]285 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]286 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]287 label = "ina226-u87";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]288 reg = <0x43>;
289 shunt-resistor = <5000>;
290 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]291 u85: ina226@44 { /* u85 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]292 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]293 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]294 label = "ina226-u85";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]295 reg = <0x44>;
296 shunt-resistor = <5000>;
297 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]298 u86: ina226@45 { /* u86 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]299 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]300 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]301 label = "ina226-u86";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]302 reg = <0x45>;
303 shunt-resistor = <5000>;
304 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]305 u93: ina226@46 { /* u93 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]306 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]307 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]308 label = "ina226-u93";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]309 reg = <0x46>;
310 shunt-resistor = <5000>;
311 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]312 u88: ina226@47 { /* u88 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]313 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]314 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]315 label = "ina226-u88";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]316 reg = <0x47>;
317 shunt-resistor = <5000>;
318 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]319 u15: ina226@4a { /* u15 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]320 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]321 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]322 label = "ina226-u15";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]323 reg = <0x4a>;
324 shunt-resistor = <5000>;
325 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]326 u92: ina226@4b { /* u92 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]327 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]328 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]329 label = "ina226-u92";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]330 reg = <0x4b>;
331 shunt-resistor = <5000>;
332 };
333 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]334 i2c@1 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <1>;
338 /* PL_PMBUS */
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]339 u79: ina226@40 { /* u79 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]340 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]341 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]342 label = "ina226-u79";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]343 reg = <0x40>;
344 shunt-resistor = <2000>;
345 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]346 u81: ina226@41 { /* u81 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]347 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]348 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]349 label = "ina226-u81";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]350 reg = <0x41>;
351 shunt-resistor = <5000>;
352 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]353 u80: ina226@42 { /* u80 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]354 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]355 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]356 label = "ina226-u80";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]357 reg = <0x42>;
358 shunt-resistor = <5000>;
359 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]360 u84: ina226@43 { /* u84 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]361 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]362 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]363 label = "ina226-u84";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]364 reg = <0x43>;
365 shunt-resistor = <5000>;
366 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]367 u16: ina226@44 { /* u16 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]368 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]369 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]370 label = "ina226-u16";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]371 reg = <0x44>;
372 shunt-resistor = <5000>;
373 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]374 u65: ina226@45 { /* u65 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]375 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]376 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]377 label = "ina226-u65";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]378 reg = <0x45>;
379 shunt-resistor = <5000>;
380 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]381 u74: ina226@46 { /* u74 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]382 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]383 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]384 label = "ina226-u74";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]385 reg = <0x46>;
386 shunt-resistor = <5000>;
387 };
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]388 u75: ina226@47 { /* u75 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]389 compatible = "ti,ina226";
Michal Simekfaddcbe2019-08-16 10:42:42 +0200[diff] [blame]390 #io-channel-cells = <1>;
Michal Simek003170e2019-08-26 10:20:07 +0200[diff] [blame]391 label = "ina226-u75";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]392 reg = <0x47>;
393 shunt-resistor = <5000>;
394 };
395 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]396 i2c@2 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]397 #address-cells = <1>;
398 #size-cells = <0>;
399 reg = <2>;
400 /* MAXIM_PMBUS - 00 */
401 max15301@a { /* u46 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]402 compatible = "maxim,max15301";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]403 reg = <0xa>;
404 };
405 max15303@b { /* u4 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]406 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]407 reg = <0xb>;
408 };
409 max15303@10 { /* u13 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]410 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]411 reg = <0x10>;
412 };
413 max15301@13 { /* u47 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]414 compatible = "maxim,max15301";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]415 reg = <0x13>;
416 };
417 max15303@14 { /* u7 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]418 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]419 reg = <0x14>;
420 };
421 max15303@15 { /* u6 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]422 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]423 reg = <0x15>;
424 };
425 max15303@16 { /* u10 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]426 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]427 reg = <0x16>;
428 };
429 max15303@17 { /* u9 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]430 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]431 reg = <0x17>;
432 };
433 max15301@18 { /* u63 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]434 compatible = "maxim,max15301";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]435 reg = <0x18>;
436 };
437 max15303@1a { /* u49 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]438 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]439 reg = <0x1a>;
440 };
441 max15303@1d { /* u18 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]442 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]443 reg = <0x1d>;
444 };
445 max15303@20 { /* u8 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]446 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]447 status = "disabled"; /* unreachable */
448 reg = <0x20>;
449 };
Michal Simek52af7e32018-03-27 12:01:24 +0200[diff] [blame]450 max20751@72 { /* u95 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]451 compatible = "maxim,max20751";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]452 reg = <0x72>;
453 };
Michal Simek52af7e32018-03-27 12:01:24 +0200[diff] [blame]454 max20751@73 { /* u96 */
Michal Simeka16e5782018-03-27 10:52:40 +0200[diff] [blame]455 compatible = "maxim,max20751";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]456 reg = <0x73>;
457 };
458 };
459 /* Bus 3 is not connected */
460 };
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]461};
462
463&i2c1 {
464 status = "okay";
465 clock-frequency = <400000>;
Michal Simek9c77cb72017-11-02 11:51:59 +0100[diff] [blame]466
Michal Simek52af7e32018-03-27 12:01:24 +0200[diff] [blame]467 /* PL i2c via PCA9306 - u45 */
Michal Simekba7b6df2018-03-27 10:38:08 +0200[diff] [blame]468 i2c-mux@74 { /* u34 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]469 compatible = "nxp,pca9548";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <0x74>;
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]473 i2c@0 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <0>;
477 /*
478 * IIC_EEPROM 1kB memory which uses 256B blocks
479 * where every block has different address.
480 * 0 - 256B address 0x54
481 * 256B - 512B address 0x55
482 * 512B - 768B address 0x56
483 * 768B - 1024B address 0x57
484 */
Michal Simekae9775f2017-11-02 11:42:12 +0100[diff] [blame]485 eeprom: eeprom@54 { /* u23 */
Michal Simek098505f2018-03-27 10:54:25 +0200[diff] [blame]486 compatible = "atmel,24c08";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]487 reg = <0x54>;
488 };
489 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]490 i2c@1 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <1>;
Michal Simek147ae1f2018-03-27 10:39:53 +0200[diff] [blame]494 si5341: clock-generator@36 { /* SI5341 - u69 */
Michal Simekbbe5c722018-03-27 12:48:30 +0200[diff] [blame]495 compatible = "silabs,si5341";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]496 reg = <0x36>;
497 };
498
499 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]500 i2c@2 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <2>;
Michal Simek147ae1f2018-03-27 10:39:53 +0200[diff] [blame]504 si570_1: clock-generator@5d { /* USER SI570 - u42 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]505 #clock-cells = <0>;
506 compatible = "silabs,si570";
507 reg = <0x5d>;
508 temperature-stability = <50>;
509 factory-fout = <300000000>;
510 clock-frequency = <300000000>;
Michal Simek6bd13ee2018-07-18 12:10:02 +0200[diff] [blame]511 clock-output-names = "si570_user";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]512 };
513 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]514 i2c@3 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <3>;
Michal Simek147ae1f2018-03-27 10:39:53 +0200[diff] [blame]518 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]519 #clock-cells = <0>;
520 compatible = "silabs,si570";
521 reg = <0x5d>;
522 temperature-stability = <50>; /* copy from zc702 */
523 factory-fout = <156250000>;
524 clock-frequency = <148500000>;
Michal Simek6bd13ee2018-07-18 12:10:02 +0200[diff] [blame]525 clock-output-names = "si570_mgt";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]526 };
527 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]528 i2c@4 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]529 #address-cells = <1>;
530 #size-cells = <0>;
531 reg = <4>;
Michal Simek147ae1f2018-03-27 10:39:53 +0200[diff] [blame]532 si5328: clock-generator@69 {/* SI5328 - u20 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]533 compatible = "silabs,si5328";
534 reg = <0x69>;
Michal Simekb10255f2017-11-02 12:45:10 +0100[diff] [blame]535 /*
536 * Chip has interrupt present connected to PL
537 * interrupt-parent = <&>;
538 * interrupts = <>;
539 */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]540 };
541 };
542 /* 5 - 7 unconnected */
543 };
544
Michal Simekba7b6df2018-03-27 10:38:08 +0200[diff] [blame]545 i2c-mux@75 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]546 compatible = "nxp,pca9548"; /* u135 */
547 #address-cells = <1>;
548 #size-cells = <0>;
549 reg = <0x75>;
550
551 i2c@0 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 reg = <0>;
555 /* HPC0_IIC */
556 };
557 i2c@1 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 reg = <1>;
561 /* HPC1_IIC */
562 };
563 i2c@2 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 reg = <2>;
567 /* SYSMON */
568 };
Michal Simek95f7d642018-03-27 10:47:26 +0200[diff] [blame]569 i2c@3 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]570 #address-cells = <1>;
571 #size-cells = <0>;
572 reg = <3>;
573 /* DDR4 SODIMM */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]574 };
575 i2c@4 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 reg = <4>;
579 /* SEP 3 */
580 };
581 i2c@5 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 reg = <5>;
585 /* SEP 2 */
586 };
587 i2c@6 {
588 #address-cells = <1>;
589 #size-cells = <0>;
590 reg = <6>;
591 /* SEP 1 */
592 };
593 i2c@7 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 reg = <7>;
597 /* SEP 0 */
598 };
599 };
600};
601
602&pcie {
Bharat Kumar Gogadaf811eca2017-01-30 12:06:02 +0530[diff] [blame]603 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]604};
605
606&qspi {
607 status = "okay";
608 is-dual = <1>;
609 flash@0 {
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000[diff] [blame]610 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]611 #address-cells = <1>;
612 #size-cells = <1>;
613 reg = <0x0>;
614 spi-tx-bus-width = <1>;
615 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
616 spi-max-frequency = <108000000>; /* Based on DC1 spec */
617 partition@qspi-fsbl-uboot { /* for testing purpose */
618 label = "qspi-fsbl-uboot";
619 reg = <0x0 0x100000>;
620 };
621 partition@qspi-linux { /* for testing purpose */
622 label = "qspi-linux";
623 reg = <0x100000 0x500000>;
624 };
625 partition@qspi-device-tree { /* for testing purpose */
626 label = "qspi-device-tree";
627 reg = <0x600000 0x20000>;
628 };
629 partition@qspi-rootfs { /* for testing purpose */
630 label = "qspi-rootfs";
631 reg = <0x620000 0x5E0000>;
632 };
633 };
634};
635
636&rtc {
637 status = "okay";
638};
639
640&sata {
641 status = "okay";
642 /* SATA OOB timing settings */
643 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
644 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
645 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
646 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
647 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
648 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
649 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
650 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
Michal Simekd70cb512017-12-01 15:50:31 +0100[diff] [blame]651 phy-names = "sata-phy";
652 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]653};
654
655/* SD1 with level shifter */
656&sdhci1 {
657 status = "okay";
658 no-1-8-v; /* for 1.0 silicon */
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530[diff] [blame]659 xlnx,mio_bank = <1>;
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]660};
661
Michal Simekd70cb512017-12-01 15:50:31 +0100[diff] [blame]662&serdes {
663 status = "okay";
664};
665
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]666&uart0 {
667 status = "okay";
668};
669
670&uart1 {
671 status = "okay";
672};
673
674/* ULPI SMSC USB3320 */
675&usb0 {
676 status = "okay";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]677};
678
679&dwc3_0 {
680 status = "okay";
681 dr_mode = "host";
Michal Simekd70cb512017-12-01 15:50:31 +0100[diff] [blame]682 snps,usb3_lpm_capable;
683 phy-names = "usb3-phy";
684 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
685 maximum-speed = "super-speed";
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]686};
687
Shubhrajyoti Dattafe16aa42017-04-06 12:28:14 +0530[diff] [blame]688&watchdog0 {
689 status = "okay";
690};
691
Michal Simek795ebc02017-11-02 12:04:43 +0100[diff] [blame]692&xilinx_ams {
693 status = "okay";
694};
695
696&ams_ps {
697 status = "okay";
698};
699
700&ams_pl {
701 status = "okay";
702};
703
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]704&xilinx_drm {
705 status = "okay";
706 clocks = <&si570_1>;
707};
708
709&xlnx_dp {
710 status = "okay";
711};
712
713&xlnx_dp_sub {
714 status = "okay";
715 xlnx,vid-clk-pl;
716};
717
718&xlnx_dp_snd_pcm0 {
719 status = "okay";
720};
721
722&xlnx_dp_snd_pcm1 {
723 status = "okay";
724};
725
726&xlnx_dp_snd_card {
727 status = "okay";
728};
729
730&xlnx_dp_snd_codec0 {
731 status = "okay";
732};
733
734&xlnx_dpdma {
735 status = "okay";
736};