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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese8870e452013-04-09 21:06:08 +00002/*
3 * Copyright 2013 Stefan Roese <sr@denx.de>
Stefan Roese8870e452013-04-09 21:06:08 +00004 */
5
6#include <common.h>
Simon Glass4d72caa2020-05-10 11:40:01 -06007#include <lmb.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Jeroen Hofstee5624c6b2014-10-08 22:57:52 +02009#include <asm/arch/sys_proto.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090010#include <linux/errno.h>
Stefan Roese8870e452013-04-09 21:06:08 +000011#include <asm/io.h>
Stefano Babic552a8482017-06-29 10:16:06 +020012#include <asm/mach-imx/regs-common.h>
Stefan Roese8870e452013-04-09 21:06:08 +000013
Ye Li528915c2019-01-04 09:10:20 +000014DECLARE_GLOBAL_DATA_PTR;
15
Stefan Roese8870e452013-04-09 21:06:08 +000016/* 1 second delay should be plenty of time for block reset. */
17#define RESET_MAX_TIMEOUT 1000000
18
19#define MXS_BLOCK_SFTRST (1 << 31)
20#define MXS_BLOCK_CLKGATE (1 << 30)
21
22int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
23 int timeout)
24{
25 while (--timeout) {
26 if ((readl(&reg->reg) & mask) == mask)
27 break;
28 udelay(1);
29 }
30
31 return !timeout;
32}
33
34int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
35 int timeout)
36{
37 while (--timeout) {
38 if ((readl(&reg->reg) & mask) == 0)
39 break;
40 udelay(1);
41 }
42
43 return !timeout;
44}
45
46int mxs_reset_block(struct mxs_register_32 *reg)
47{
48 /* Clear SFTRST */
49 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
50
51 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
52 return 1;
53
54 /* Clear CLKGATE */
55 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
56
57 /* Set SFTRST */
58 writel(MXS_BLOCK_SFTRST, &reg->reg_set);
59
60 /* Wait for CLKGATE being set */
61 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
62 return 1;
63
64 /* Clear SFTRST */
65 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
66
67 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
68 return 1;
69
70 /* Clear CLKGATE */
71 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
72
73 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
74 return 1;
75
76 return 0;
77}
Ye Li528915c2019-01-04 09:10:20 +000078
79static ulong get_sp(void)
80{
81 ulong ret;
82
83 asm("mov %0, sp" : "=r"(ret) : );
84 return ret;
85}
86
87void board_lmb_reserve(struct lmb *lmb)
88{
89 ulong sp, bank_end;
90 int bank;
91
92 sp = get_sp();
93 debug("## Current stack ends at 0x%08lx ", sp);
94
95 /* adjust sp by 16K to be safe */
96 sp -= 4096 << 2;
97 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
98 if (sp < gd->bd->bi_dram[bank].start)
99 continue;
100 bank_end = gd->bd->bi_dram[bank].start +
101 gd->bd->bi_dram[bank].size;
102 if (sp >= bank_end)
103 continue;
104 lmb_reserve(lmb, sp, bank_end - sp);
105 break;
106 }
107}