blob: 0ce97656715f0e6a2dbdbf95542b436005556819 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00002/*
wdenk97d80fc2004-06-09 00:34:46 +00003 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00004 *
Claudiu Manoilaec84bf2013-09-30 12:44:42 +03005 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00006 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +00007 * author Andy Fleming
wdenk42d1f032003-10-15 23:53:47 +00008 */
9
10#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000011#include <common.h>
Bin Meng9a1d6af2016-01-11 22:41:24 -080012#include <dm.h>
wdenk42d1f032003-10-15 23:53:47 +000013#include <malloc.h>
14#include <net.h>
15#include <command.h>
Andy Flemingdd3d1f52008-08-31 16:33:25 -050016#include <tsec.h>
Andy Fleming063c1262011-04-08 02:10:54 -050017#include <fsl_mdio.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060019#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090020#include <linux/errno.h>
Hou Zhiqiangb4eb9cf2020-07-16 18:09:12 +080021#include <miiphy.h>
chenhui zhaoaada81d2011-10-03 08:38:50 -050022#include <asm/processor.h>
Alison Wang52d00a82014-09-05 13:52:38 +080023#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000024
Bin Meng9a1d6af2016-01-11 22:41:24 -080025#ifndef CONFIG_DM_ETH
Andy Fleming75b9d4a2008-08-31 16:33:26 -050026/* Default initializations for TSEC controllers. */
27
28static struct tsec_info_struct tsec_info[] = {
29#ifdef CONFIG_TSEC1
30 STD_TSEC_INFO(1), /* TSEC1 */
31#endif
32#ifdef CONFIG_TSEC2
33 STD_TSEC_INFO(2), /* TSEC2 */
34#endif
35#ifdef CONFIG_MPC85XX_FEC
36 {
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030037 .regs = TSEC_GET_REGS(2, 0x2000),
Andy Fleming75b9d4a2008-08-31 16:33:26 -050038 .devname = CONFIG_MPC85XX_FEC_NAME,
39 .phyaddr = FEC_PHY_ADDR,
Andy Fleming063c1262011-04-08 02:10:54 -050040 .flags = FEC_FLAGS,
41 .mii_devname = DEFAULT_MII_NAME
Andy Fleming75b9d4a2008-08-31 16:33:26 -050042 }, /* FEC */
43#endif
44#ifdef CONFIG_TSEC3
45 STD_TSEC_INFO(3), /* TSEC3 */
46#endif
47#ifdef CONFIG_TSEC4
48 STD_TSEC_INFO(4), /* TSEC4 */
49#endif
50};
Bin Meng9a1d6af2016-01-11 22:41:24 -080051#endif /* CONFIG_DM_ETH */
Andy Fleming75b9d4a2008-08-31 16:33:26 -050052
Andy Fleming2abe3612008-08-31 16:33:27 -050053#define TBIANA_SETTINGS ( \
54 TBIANA_ASYMMETRIC_PAUSE \
55 | TBIANA_SYMMETRIC_PAUSE \
56 | TBIANA_FULL_DUPLEX \
57 )
58
Felix Radensky90b5bf22010-06-28 01:57:39 +030059/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
60#ifndef CONFIG_TSEC_TBICR_SETTINGS
Kumar Gala72c96a62010-12-01 22:55:54 -060061#define CONFIG_TSEC_TBICR_SETTINGS ( \
Andy Fleming2abe3612008-08-31 16:33:27 -050062 TBICR_PHY_RESET \
Kumar Gala72c96a62010-12-01 22:55:54 -060063 | TBICR_ANEG_ENABLE \
Andy Fleming2abe3612008-08-31 16:33:27 -050064 | TBICR_FULL_DUPLEX \
65 | TBICR_SPEED1_SET \
66 )
Felix Radensky90b5bf22010-06-28 01:57:39 +030067#endif /* CONFIG_TSEC_TBICR_SETTINGS */
Peter Tyser46e91672009-11-03 17:52:07 -060068
Andy Fleming2abe3612008-08-31 16:33:27 -050069/* Configure the TBI for SGMII operation */
70static void tsec_configure_serdes(struct tsec_private *priv)
71{
Bin Meng9872b732016-01-11 22:41:18 -080072 /*
73 * Access TBI PHY registers at given TSEC register offset as opposed
74 * to the register offset used for external PHY accesses
75 */
Andy Fleming063c1262011-04-08 02:10:54 -050076 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010077 0, TBI_ANA, TBIANA_SETTINGS);
Andy Fleming063c1262011-04-08 02:10:54 -050078 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010079 0, TBI_TBICON, TBICON_CLK_SELECT);
Andy Fleming063c1262011-04-08 02:10:54 -050080 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010081 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
Andy Fleming2abe3612008-08-31 16:33:27 -050082}
michael.firth@bt.com55fe7c52008-01-16 11:40:51 +000083
Chris Packham1a4af5c2018-11-26 21:00:28 +130084/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
85 * and this is the ethernet-crc method needed for TSEC -- and perhaps
86 * some other adapter -- hash tables
87 */
88#define CRCPOLY_LE 0xedb88320
89static u32 ether_crc(size_t len, unsigned char const *p)
90{
91 int i;
92 u32 crc;
93
94 crc = ~0;
95 while (len--) {
96 crc ^= *p++;
97 for (i = 0; i < 8; i++)
98 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
99 }
100 /* an reverse the bits, cuz of way they arrive -- last-first */
101 crc = (crc >> 16) | (crc << 16);
102 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
103 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
104 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
105 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
106 return crc;
107}
108
David Updegraff53a5c422007-06-11 10:41:07 -0500109/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
110
111/* Set the appropriate hash bit for the given addr */
112
Bin Meng9872b732016-01-11 22:41:18 -0800113/*
114 * The algorithm works like so:
David Updegraff53a5c422007-06-11 10:41:07 -0500115 * 1) Take the Destination Address (ie the multicast address), and
116 * do a CRC on it (little endian), and reverse the bits of the
117 * result.
118 * 2) Use the 8 most significant bits as a hash into a 256-entry
119 * table. The table is controlled through 8 32-bit registers:
Claudiu Manoil876d4512013-09-30 12:44:40 +0300120 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
121 * 255. This means that the 3 most significant bits in the
David Updegraff53a5c422007-06-11 10:41:07 -0500122 * hash index which gaddr register to use, and the 5 other bits
123 * indicate which bit (assuming an IBM numbering scheme, which
Claudiu Manoil876d4512013-09-30 12:44:40 +0300124 * for PowerPC (tm) is usually the case) in the register holds
Bin Meng9872b732016-01-11 22:41:18 -0800125 * the entry.
126 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800127#ifndef CONFIG_DM_ETH
Chris Packham67bb9842018-11-26 21:00:29 +1300128static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
129 int join)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800130#else
Chris Packham67bb9842018-11-26 21:00:29 +1300131static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800132#endif
David Updegraff53a5c422007-06-11 10:41:07 -0500133{
Simon Glass0fd3d912020-12-22 19:30:28 -0700134 struct tsec_private *priv;
135 struct tsec __iomem *regs;
Claudiu Manoil876d4512013-09-30 12:44:40 +0300136 u32 result, value;
137 u8 whichbit, whichreg;
David Updegraff53a5c422007-06-11 10:41:07 -0500138
Simon Glass0fd3d912020-12-22 19:30:28 -0700139#ifndef CONFIG_DM_ETH
140 priv = (struct tsec_private *)dev->priv;
141#else
142 priv = dev_get_priv(dev);
143#endif
144 regs = priv->regs;
Claudiu Manoil876d4512013-09-30 12:44:40 +0300145 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
146 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
147 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
David Updegraff53a5c422007-06-11 10:41:07 -0500148
Mario Sixd38de332018-01-15 11:08:21 +0100149 value = BIT(31 - whichbit);
David Updegraff53a5c422007-06-11 10:41:07 -0500150
Chris Packham67bb9842018-11-26 21:00:29 +1300151 if (join)
Claudiu Manoil876d4512013-09-30 12:44:40 +0300152 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
153 else
154 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
155
David Updegraff53a5c422007-06-11 10:41:07 -0500156 return 0;
157}
Mingkai Hu90751912011-01-27 12:52:46 +0800158
Bin Meng9872b732016-01-11 22:41:18 -0800159/*
160 * Initialized required registers to appropriate values, zeroing
Mingkai Hu90751912011-01-27 12:52:46 +0800161 * those we don't care about (unless zero is bad, in which case,
162 * choose a more appropriate value)
163 */
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300164static void init_registers(struct tsec __iomem *regs)
Mingkai Hu90751912011-01-27 12:52:46 +0800165{
166 /* Clear IEVENT */
167 out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
168
169 out_be32(&regs->imask, IMASK_INIT_CLEAR);
170
171 out_be32(&regs->hash.iaddr0, 0);
172 out_be32(&regs->hash.iaddr1, 0);
173 out_be32(&regs->hash.iaddr2, 0);
174 out_be32(&regs->hash.iaddr3, 0);
175 out_be32(&regs->hash.iaddr4, 0);
176 out_be32(&regs->hash.iaddr5, 0);
177 out_be32(&regs->hash.iaddr6, 0);
178 out_be32(&regs->hash.iaddr7, 0);
179
180 out_be32(&regs->hash.gaddr0, 0);
181 out_be32(&regs->hash.gaddr1, 0);
182 out_be32(&regs->hash.gaddr2, 0);
183 out_be32(&regs->hash.gaddr3, 0);
184 out_be32(&regs->hash.gaddr4, 0);
185 out_be32(&regs->hash.gaddr5, 0);
186 out_be32(&regs->hash.gaddr6, 0);
187 out_be32(&regs->hash.gaddr7, 0);
188
189 out_be32(&regs->rctrl, 0x00000000);
190
191 /* Init RMON mib registers */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300192 memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
Mingkai Hu90751912011-01-27 12:52:46 +0800193
194 out_be32(&regs->rmon.cam1, 0xffffffff);
195 out_be32(&regs->rmon.cam2, 0xffffffff);
196
197 out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
198
199 out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
200
201 out_be32(&regs->attr, ATTR_INIT_SETTINGS);
202 out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
Mingkai Hu90751912011-01-27 12:52:46 +0800203}
204
Bin Meng9872b732016-01-11 22:41:18 -0800205/*
206 * Configure maccfg2 based on negotiated speed and duplex
Mingkai Hu90751912011-01-27 12:52:46 +0800207 * reported by PHY handling code
208 */
Andy Fleming063c1262011-04-08 02:10:54 -0500209static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
Mingkai Hu90751912011-01-27 12:52:46 +0800210{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300211 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800212 u32 ecntrl, maccfg2;
213
Andy Fleming063c1262011-04-08 02:10:54 -0500214 if (!phydev->link) {
215 printf("%s: No link.\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800216 return;
217 }
218
219 /* clear all bits relative with interface mode */
220 ecntrl = in_be32(&regs->ecntrl);
221 ecntrl &= ~ECNTRL_R100;
222
223 maccfg2 = in_be32(&regs->maccfg2);
224 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
225
Andy Fleming063c1262011-04-08 02:10:54 -0500226 if (phydev->duplex)
Mingkai Hu90751912011-01-27 12:52:46 +0800227 maccfg2 |= MACCFG2_FULL_DUPLEX;
228
Andy Fleming063c1262011-04-08 02:10:54 -0500229 switch (phydev->speed) {
Mingkai Hu90751912011-01-27 12:52:46 +0800230 case 1000:
231 maccfg2 |= MACCFG2_GMII;
232 break;
233 case 100:
234 case 10:
235 maccfg2 |= MACCFG2_MII;
236
Bin Meng9872b732016-01-11 22:41:18 -0800237 /*
238 * Set R100 bit in all modes although
Mingkai Hu90751912011-01-27 12:52:46 +0800239 * it is only used in RGMII mode
240 */
Andy Fleming063c1262011-04-08 02:10:54 -0500241 if (phydev->speed == 100)
Mingkai Hu90751912011-01-27 12:52:46 +0800242 ecntrl |= ECNTRL_R100;
243 break;
244 default:
Andy Fleming063c1262011-04-08 02:10:54 -0500245 printf("%s: Speed was bad\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800246 break;
247 }
248
249 out_be32(&regs->ecntrl, ecntrl);
250 out_be32(&regs->maccfg2, maccfg2);
251
Andy Fleming063c1262011-04-08 02:10:54 -0500252 printf("Speed: %d, %s duplex%s\n", phydev->speed,
Mario Sixd38de332018-01-15 11:08:21 +0100253 (phydev->duplex) ? "full" : "half",
254 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Mingkai Hu90751912011-01-27 12:52:46 +0800255}
256
Bin Meng8ba50172016-01-11 22:41:21 -0800257/*
258 * This returns the status bits of the device. The return value
259 * is never checked, and this is what the 8260 driver did, so we
260 * do the same. Presumably, this would be zero if there were no
261 * errors
262 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800263#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800264static int tsec_send(struct eth_device *dev, void *packet, int length)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800265#else
266static int tsec_send(struct udevice *dev, void *packet, int length)
267#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800268{
Simon Glass0fd3d912020-12-22 19:30:28 -0700269 struct tsec_private *priv;
270 struct tsec __iomem *regs;
Bin Meng8ba50172016-01-11 22:41:21 -0800271 int result = 0;
Vladimir Oltean07bd39f2019-07-19 00:29:55 +0300272 u16 status;
Bin Meng8ba50172016-01-11 22:41:21 -0800273 int i;
274
Simon Glass0fd3d912020-12-22 19:30:28 -0700275#ifndef CONFIG_DM_ETH
276 priv = (struct tsec_private *)dev->priv;
277#else
278 priv = dev_get_priv(dev);
279#endif
280 regs = priv->regs;
Bin Meng8ba50172016-01-11 22:41:21 -0800281 /* Find an empty buffer descriptor */
282 for (i = 0;
283 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
284 i++) {
285 if (i >= TOUT_LOOP) {
Vladimir Olteanb7be7762019-07-19 00:29:56 +0300286 printf("%s: tsec: tx buffers full\n", dev->name);
Bin Meng8ba50172016-01-11 22:41:21 -0800287 return result;
288 }
289 }
290
291 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
292 out_be16(&priv->txbd[priv->tx_idx].length, length);
293 status = in_be16(&priv->txbd[priv->tx_idx].status);
294 out_be16(&priv->txbd[priv->tx_idx].status, status |
295 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
296
297 /* Tell the DMA to go */
298 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
299
300 /* Wait for buffer to be transmitted */
301 for (i = 0;
302 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
303 i++) {
304 if (i >= TOUT_LOOP) {
Vladimir Olteanb7be7762019-07-19 00:29:56 +0300305 printf("%s: tsec: tx error\n", dev->name);
Bin Meng8ba50172016-01-11 22:41:21 -0800306 return result;
307 }
308 }
309
310 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
311 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
312
313 return result;
314}
315
Bin Meng9a1d6af2016-01-11 22:41:24 -0800316#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800317static int tsec_recv(struct eth_device *dev)
318{
319 struct tsec_private *priv = (struct tsec_private *)dev->priv;
320 struct tsec __iomem *regs = priv->regs;
321
322 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
323 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
Mario Sixd38de332018-01-15 11:08:21 +0100324 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
Bin Meng8ba50172016-01-11 22:41:21 -0800325 uchar *packet = net_rx_packets[priv->rx_idx];
326
327 /* Send the packet up if there were no errors */
328 if (!(status & RXBD_STATS))
329 net_process_received_packet(packet, length - 4);
330 else
331 printf("Got error %x\n", (status & RXBD_STATS));
332
333 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
334
335 status = RXBD_EMPTY;
336 /* Set the wrap bit if this is the last element in the list */
337 if ((priv->rx_idx + 1) == PKTBUFSRX)
338 status |= RXBD_WRAP;
339 out_be16(&priv->rxbd[priv->rx_idx].status, status);
340
341 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
342 }
343
344 if (in_be32(&regs->ievent) & IEVENT_BSY) {
345 out_be32(&regs->ievent, IEVENT_BSY);
346 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
347 }
348
349 return -1;
350}
Bin Meng9a1d6af2016-01-11 22:41:24 -0800351#else
352static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
353{
Simon Glass0fd3d912020-12-22 19:30:28 -0700354 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800355 struct tsec __iomem *regs = priv->regs;
356 int ret = -1;
357
358 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
359 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
Mario Sixd38de332018-01-15 11:08:21 +0100360 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
361 u32 buf;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800362
363 /* Send the packet up if there were no errors */
364 if (!(status & RXBD_STATS)) {
365 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
366 *packetp = (uchar *)buf;
367 ret = length - 4;
368 } else {
369 printf("Got error %x\n", (status & RXBD_STATS));
370 }
371 }
372
373 if (in_be32(&regs->ievent) & IEVENT_BSY) {
374 out_be32(&regs->ievent, IEVENT_BSY);
375 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
376 }
377
378 return ret;
379}
380
381static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
382{
Simon Glass0fd3d912020-12-22 19:30:28 -0700383 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
Mario Sixd38de332018-01-15 11:08:21 +0100384 u16 status;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800385
386 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
387
388 status = RXBD_EMPTY;
389 /* Set the wrap bit if this is the last element in the list */
390 if ((priv->rx_idx + 1) == PKTBUFSRX)
391 status |= RXBD_WRAP;
392 out_be16(&priv->rxbd[priv->rx_idx].status, status);
393
394 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
395
396 return 0;
397}
398#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800399
400/* Stop the interface */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800401#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800402static void tsec_halt(struct eth_device *dev)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800403#else
404static void tsec_halt(struct udevice *dev)
405#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800406{
Simon Glass0fd3d912020-12-22 19:30:28 -0700407 struct tsec_private *priv;
408 struct tsec __iomem *regs;
409#ifndef CONFIG_DM_ETH
410 priv = (struct tsec_private *)dev->priv;
411#else
412 priv = dev_get_priv(dev);
413#endif
414 regs = priv->regs;
Bin Meng8ba50172016-01-11 22:41:21 -0800415
416 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
417 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
418
419 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
420 != (IEVENT_GRSC | IEVENT_GTSC))
421 ;
422
423 clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
424
425 /* Shut down the PHY, as needed */
426 phy_shutdown(priv->phydev);
427}
428
chenhui zhaoaada81d2011-10-03 08:38:50 -0500429#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
430/*
431 * When MACCFG1[Rx_EN] is enabled during system boot as part
432 * of the eTSEC port initialization sequence,
433 * the eTSEC Rx logic may not be properly initialized.
434 */
Bin Meng56a27a12016-01-11 22:41:22 -0800435void redundant_init(struct tsec_private *priv)
chenhui zhaoaada81d2011-10-03 08:38:50 -0500436{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300437 struct tsec __iomem *regs = priv->regs;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500438 uint t, count = 0;
439 int fail = 1;
440 static const u8 pkt[] = {
441 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
442 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
443 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
444 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
445 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
446 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
447 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
448 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
449 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
450 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
451 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
452 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
453 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
454 0x71, 0x72};
455
456 /* Enable promiscuous mode */
457 setbits_be32(&regs->rctrl, 0x8);
458 /* Enable loopback mode */
459 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
460 /* Enable transmit and receive */
461 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
462
463 /* Tell the DMA it is clear to go */
464 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
465 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
466 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
467 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
468
469 do {
Mario Sixd38de332018-01-15 11:08:21 +0100470 u16 status;
471
Bin Meng56a27a12016-01-11 22:41:22 -0800472 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
chenhui zhaoaada81d2011-10-03 08:38:50 -0500473
474 /* Wait for buffer to be received */
Bin Menge677da92016-01-11 22:41:20 -0800475 for (t = 0;
476 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
Bin Meng362b1232016-01-11 22:41:19 -0800477 t++) {
chenhui zhaoaada81d2011-10-03 08:38:50 -0500478 if (t >= 10 * TOUT_LOOP) {
Bin Meng56a27a12016-01-11 22:41:22 -0800479 printf("%s: tsec: rx error\n", priv->dev->name);
chenhui zhaoaada81d2011-10-03 08:38:50 -0500480 break;
481 }
482 }
483
Bin Meng362b1232016-01-11 22:41:19 -0800484 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
chenhui zhaoaada81d2011-10-03 08:38:50 -0500485 fail = 0;
486
Bin Menge677da92016-01-11 22:41:20 -0800487 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300488 status = RXBD_EMPTY;
Bin Meng362b1232016-01-11 22:41:19 -0800489 if ((priv->rx_idx + 1) == PKTBUFSRX)
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300490 status |= RXBD_WRAP;
Bin Menge677da92016-01-11 22:41:20 -0800491 out_be16(&priv->rxbd[priv->rx_idx].status, status);
Bin Meng362b1232016-01-11 22:41:19 -0800492 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500493
494 if (in_be32(&regs->ievent) & IEVENT_BSY) {
495 out_be32(&regs->ievent, IEVENT_BSY);
496 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
497 }
498 if (fail) {
499 printf("loopback recv packet error!\n");
500 clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
501 udelay(1000);
502 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
503 }
504 } while ((count++ < 4) && (fail == 1));
505
506 if (fail)
507 panic("eTSEC init fail!\n");
508 /* Disable promiscuous mode */
509 clrbits_be32(&regs->rctrl, 0x8);
510 /* Disable loopback mode */
511 clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
512}
513#endif
514
Bin Meng9872b732016-01-11 22:41:18 -0800515/*
516 * Set up the buffers and their descriptors, and bring up the
Mingkai Hu90751912011-01-27 12:52:46 +0800517 * interface
518 */
Bin Meng56a27a12016-01-11 22:41:22 -0800519static void startup_tsec(struct tsec_private *priv)
Mingkai Hu90751912011-01-27 12:52:46 +0800520{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300521 struct tsec __iomem *regs = priv->regs;
Mario Sixd38de332018-01-15 11:08:21 +0100522 u16 status;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300523 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800524
Andy Fleming063c1262011-04-08 02:10:54 -0500525 /* reset the indices to zero */
Bin Meng362b1232016-01-11 22:41:19 -0800526 priv->rx_idx = 0;
527 priv->tx_idx = 0;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500528#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
529 uint svr;
530#endif
Andy Fleming063c1262011-04-08 02:10:54 -0500531
Mingkai Hu90751912011-01-27 12:52:46 +0800532 /* Point to the buffer descriptors */
Bin Menge677da92016-01-11 22:41:20 -0800533 out_be32(&regs->tbase, (u32)&priv->txbd[0]);
534 out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
Mingkai Hu90751912011-01-27 12:52:46 +0800535
536 /* Initialize the Rx Buffer descriptors */
537 for (i = 0; i < PKTBUFSRX; i++) {
Bin Menge677da92016-01-11 22:41:20 -0800538 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
539 out_be16(&priv->rxbd[i].length, 0);
540 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
Mingkai Hu90751912011-01-27 12:52:46 +0800541 }
Bin Menge677da92016-01-11 22:41:20 -0800542 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
543 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800544
545 /* Initialize the TX Buffer Descriptors */
546 for (i = 0; i < TX_BUF_CNT; i++) {
Bin Menge677da92016-01-11 22:41:20 -0800547 out_be16(&priv->txbd[i].status, 0);
548 out_be16(&priv->txbd[i].length, 0);
549 out_be32(&priv->txbd[i].bufptr, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800550 }
Bin Menge677da92016-01-11 22:41:20 -0800551 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
552 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800553
chenhui zhaoaada81d2011-10-03 08:38:50 -0500554#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
555 svr = get_svr();
556 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
Bin Meng56a27a12016-01-11 22:41:22 -0800557 redundant_init(priv);
chenhui zhaoaada81d2011-10-03 08:38:50 -0500558#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800559 /* Enable Transmit and Receive */
560 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
561
562 /* Tell the DMA it is clear to go */
563 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
564 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
565 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
566 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
567}
568
Bin Meng9872b732016-01-11 22:41:18 -0800569/*
Bin Meng9872b732016-01-11 22:41:18 -0800570 * Initializes data structures and registers for the controller,
571 * and brings the interface up. Returns the link status, meaning
Mingkai Hu90751912011-01-27 12:52:46 +0800572 * that it returns success if the link is up, failure otherwise.
Bin Meng9872b732016-01-11 22:41:18 -0800573 * This allows U-Boot to find the first active controller.
Mingkai Hu90751912011-01-27 12:52:46 +0800574 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800575#ifndef CONFIG_DM_ETH
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900576static int tsec_init(struct eth_device *dev, struct bd_info *bd)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800577#else
578static int tsec_init(struct udevice *dev)
579#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800580{
Simon Glass0fd3d912020-12-22 19:30:28 -0700581 struct tsec_private *priv;
582 struct tsec __iomem *regs;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800583#ifdef CONFIG_DM_ETH
Simon Glassc69cda22020-12-03 16:55:20 -0700584 struct eth_pdata *pdata = dev_get_plat(dev);
Vladimir Olteanf6297c02019-07-19 00:29:57 +0300585#else
586 struct eth_device *pdata = dev;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800587#endif
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300588 u32 tempval;
Timur Tabi11af8d62012-07-09 08:52:43 +0000589 int ret;
Mingkai Hu90751912011-01-27 12:52:46 +0800590
Simon Glass0fd3d912020-12-22 19:30:28 -0700591#ifndef CONFIG_DM_ETH
592 priv = (struct tsec_private *)dev->priv;
593#else
594 priv = dev_get_priv(dev);
595#endif
596 regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800597 /* Make sure the controller is stopped */
598 tsec_halt(dev);
599
600 /* Init MACCFG2. Defaults to GMII */
601 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
602
603 /* Init ECNTRL */
604 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
605
Bin Meng9872b732016-01-11 22:41:18 -0800606 /*
607 * Copy the station address into the address registers.
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300608 * For a station address of 0x12345678ABCD in transmission
609 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
610 * MACnADDR2 is set to 0x34120000.
611 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800612 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
613 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
Mingkai Hu90751912011-01-27 12:52:46 +0800614
615 out_be32(&regs->macstnaddr1, tempval);
616
Bin Meng9a1d6af2016-01-11 22:41:24 -0800617 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
Mingkai Hu90751912011-01-27 12:52:46 +0800618
619 out_be32(&regs->macstnaddr2, tempval);
620
Mingkai Hu90751912011-01-27 12:52:46 +0800621 /* Clear out (for the most part) the other registers */
622 init_registers(regs);
623
624 /* Ready the device for tx/rx */
Bin Meng56a27a12016-01-11 22:41:22 -0800625 startup_tsec(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800626
Andy Fleming063c1262011-04-08 02:10:54 -0500627 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000628 ret = phy_startup(priv->phydev);
629 if (ret) {
630 printf("Could not initialize PHY %s\n",
631 priv->phydev->dev->name);
632 return ret;
633 }
Andy Fleming063c1262011-04-08 02:10:54 -0500634
635 adjust_link(priv, priv->phydev);
636
Mingkai Hu90751912011-01-27 12:52:46 +0800637 /* If there's no link, fail */
Andy Fleming063c1262011-04-08 02:10:54 -0500638 return priv->phydev->link ? 0 : -1;
Mingkai Hu90751912011-01-27 12:52:46 +0800639}
640
Ramon Fried596ec9b2021-09-28 18:49:02 +0300641static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
Andy Fleming063c1262011-04-08 02:10:54 -0500642{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300643 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500644 u32 ecntrl;
645
646 ecntrl = in_be32(&regs->ecntrl);
647
648 if (ecntrl & ECNTRL_SGMII_MODE)
649 return PHY_INTERFACE_MODE_SGMII;
650
651 if (ecntrl & ECNTRL_TBI_MODE) {
652 if (ecntrl & ECNTRL_REDUCED_MODE)
653 return PHY_INTERFACE_MODE_RTBI;
654 else
655 return PHY_INTERFACE_MODE_TBI;
656 }
657
658 if (ecntrl & ECNTRL_REDUCED_MODE) {
Mario Sixd38de332018-01-15 11:08:21 +0100659 phy_interface_t interface;
660
Andy Fleming063c1262011-04-08 02:10:54 -0500661 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
662 return PHY_INTERFACE_MODE_RMII;
Andy Fleming063c1262011-04-08 02:10:54 -0500663
Mario Sixd38de332018-01-15 11:08:21 +0100664 interface = priv->interface;
Andy Fleming063c1262011-04-08 02:10:54 -0500665
Mario Sixd38de332018-01-15 11:08:21 +0100666 /*
667 * This isn't autodetected, so it must
668 * be set by the platform code.
669 */
670 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
671 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
672 interface == PHY_INTERFACE_MODE_RGMII_RXID)
673 return interface;
674
675 return PHY_INTERFACE_MODE_RGMII;
Andy Fleming063c1262011-04-08 02:10:54 -0500676 }
677
678 if (priv->flags & TSEC_GIGABIT)
679 return PHY_INTERFACE_MODE_GMII;
680
681 return PHY_INTERFACE_MODE_MII;
682}
683
Bin Meng9872b732016-01-11 22:41:18 -0800684/*
685 * Discover which PHY is attached to the device, and configure it
Mingkai Hu90751912011-01-27 12:52:46 +0800686 * properly. If the PHY is not recognized, then return 0
687 * (failure). Otherwise, return 1
688 */
Bin Meng56a27a12016-01-11 22:41:22 -0800689static int init_phy(struct tsec_private *priv)
Mingkai Hu90751912011-01-27 12:52:46 +0800690{
Andy Fleming063c1262011-04-08 02:10:54 -0500691 struct phy_device *phydev;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300692 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500693 u32 supported = (SUPPORTED_10baseT_Half |
694 SUPPORTED_10baseT_Full |
695 SUPPORTED_100baseT_Half |
696 SUPPORTED_100baseT_Full);
697
698 if (priv->flags & TSEC_GIGABIT)
699 supported |= SUPPORTED_1000baseT_Full;
Mingkai Hu90751912011-01-27 12:52:46 +0800700
701 /* Assign a Physical address to the TBI */
Bin Menga1c76c12016-01-11 22:41:25 -0800702 out_be32(&regs->tbipa, priv->tbiaddr);
Mingkai Hu90751912011-01-27 12:52:46 +0800703
Andy Fleming063c1262011-04-08 02:10:54 -0500704 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
Mingkai Hu90751912011-01-27 12:52:46 +0800705 tsec_configure_serdes(priv);
706
Hou Zhiqiangb4eb9cf2020-07-16 18:09:12 +0800707#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
Vladimir Oltean3c562512021-03-14 20:14:56 +0800708 phydev = dm_eth_phy_connect(priv->dev);
Hou Zhiqiangb4eb9cf2020-07-16 18:09:12 +0800709#else
Bin Meng56a27a12016-01-11 22:41:22 -0800710 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
711 priv->interface);
Hou Zhiqiangb4eb9cf2020-07-16 18:09:12 +0800712#endif
Claudiu Manoil7f233c02013-12-10 15:21:04 +0200713 if (!phydev)
714 return 0;
Mingkai Hu90751912011-01-27 12:52:46 +0800715
Andy Fleming063c1262011-04-08 02:10:54 -0500716 phydev->supported &= supported;
717 phydev->advertising = phydev->supported;
718
719 priv->phydev = phydev;
720
721 phy_config(phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800722
723 return 1;
724}
725
Bin Meng9a1d6af2016-01-11 22:41:24 -0800726#ifndef CONFIG_DM_ETH
Bin Meng9872b732016-01-11 22:41:18 -0800727/*
728 * Initialize device structure. Returns success if PHY
Mingkai Hu90751912011-01-27 12:52:46 +0800729 * initialization succeeded (i.e. if it recognizes the PHY)
730 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900731static int tsec_initialize(struct bd_info *bis,
732 struct tsec_info_struct *tsec_info)
Mingkai Hu90751912011-01-27 12:52:46 +0800733{
Vladimir Oltean07bd39f2019-07-19 00:29:55 +0300734 struct tsec_private *priv;
Mingkai Hu90751912011-01-27 12:52:46 +0800735 struct eth_device *dev;
736 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800737
Mario Sixd38de332018-01-15 11:08:21 +0100738 dev = (struct eth_device *)malloc(sizeof(*dev));
Mingkai Hu90751912011-01-27 12:52:46 +0800739
Mario Sixd38de332018-01-15 11:08:21 +0100740 if (!dev)
Mingkai Hu90751912011-01-27 12:52:46 +0800741 return 0;
742
Mario Sixd38de332018-01-15 11:08:21 +0100743 memset(dev, 0, sizeof(*dev));
Mingkai Hu90751912011-01-27 12:52:46 +0800744
745 priv = (struct tsec_private *)malloc(sizeof(*priv));
746
Mario Six5775f002018-01-15 11:08:22 +0100747 if (!priv) {
748 free(dev);
Mingkai Hu90751912011-01-27 12:52:46 +0800749 return 0;
Mario Six5775f002018-01-15 11:08:22 +0100750 }
Mingkai Hu90751912011-01-27 12:52:46 +0800751
Mingkai Hu90751912011-01-27 12:52:46 +0800752 priv->regs = tsec_info->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800753 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
754
755 priv->phyaddr = tsec_info->phyaddr;
Bin Menga1c76c12016-01-11 22:41:25 -0800756 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
Mingkai Hu90751912011-01-27 12:52:46 +0800757 priv->flags = tsec_info->flags;
758
Ben Whitten192bc692015-12-30 13:05:58 +0000759 strcpy(dev->name, tsec_info->devname);
Andy Fleming063c1262011-04-08 02:10:54 -0500760 priv->interface = tsec_info->interface;
761 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
Bin Meng56a27a12016-01-11 22:41:22 -0800762 priv->dev = dev;
Mingkai Hu90751912011-01-27 12:52:46 +0800763 dev->iobase = 0;
764 dev->priv = priv;
765 dev->init = tsec_init;
766 dev->halt = tsec_halt;
767 dev->send = tsec_send;
768 dev->recv = tsec_recv;
Mingkai Hu90751912011-01-27 12:52:46 +0800769 dev->mcast = tsec_mcast_addr;
Mingkai Hu90751912011-01-27 12:52:46 +0800770
Bin Meng9872b732016-01-11 22:41:18 -0800771 /* Tell U-Boot to get the addr from the env */
Mingkai Hu90751912011-01-27 12:52:46 +0800772 for (i = 0; i < 6; i++)
773 dev->enetaddr[i] = 0;
774
775 eth_register(dev);
776
777 /* Reset the MAC */
778 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
779 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
780 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
781
Mingkai Hu90751912011-01-27 12:52:46 +0800782 /* Try to initialize PHY here, and return */
Bin Meng56a27a12016-01-11 22:41:22 -0800783 return init_phy(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800784}
785
786/*
787 * Initialize all the TSEC devices
788 *
789 * Returns the number of TSEC devices that were initialized
790 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900791int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
792 int num)
Mingkai Hu90751912011-01-27 12:52:46 +0800793{
794 int i;
Mario Sixd38de332018-01-15 11:08:21 +0100795 int count = 0;
Mingkai Hu90751912011-01-27 12:52:46 +0800796
797 for (i = 0; i < num; i++) {
Mario Sixd38de332018-01-15 11:08:21 +0100798 int ret = tsec_initialize(bis, &tsecs[i]);
799
Mingkai Hu90751912011-01-27 12:52:46 +0800800 if (ret > 0)
801 count += ret;
802 }
803
804 return count;
805}
806
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900807int tsec_standard_init(struct bd_info *bis)
Mingkai Hu90751912011-01-27 12:52:46 +0800808{
Andy Fleming063c1262011-04-08 02:10:54 -0500809 struct fsl_pq_mdio_info info;
810
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300811 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
Andy Fleming063c1262011-04-08 02:10:54 -0500812 info.name = DEFAULT_MII_NAME;
813
814 fsl_pq_mdio_init(bis, &info);
815
Mingkai Hu90751912011-01-27 12:52:46 +0800816 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
817}
Bin Meng9a1d6af2016-01-11 22:41:24 -0800818#else /* CONFIG_DM_ETH */
819int tsec_probe(struct udevice *dev)
820{
Simon Glassc69cda22020-12-03 16:55:20 -0700821 struct eth_pdata *pdata = dev_get_plat(dev);
Vladimir Oltean07bd39f2019-07-19 00:29:55 +0300822 struct tsec_private *priv = dev_get_priv(dev);
Mario Six1313aaf2018-01-15 11:08:23 +0100823 struct ofnode_phandle_args phandle_args;
Vladimir Oltean29db3102019-07-19 00:29:53 +0300824 u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
Hou Zhiqiang7fb568d2020-07-16 18:09:14 +0800825 struct tsec_data *data;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800826 const char *phy_mode;
Bin Menga0815462021-03-14 20:15:01 +0800827 ofnode parent, child;
Vladimir Olteanbca686a2019-07-19 00:29:54 +0300828 fdt_addr_t reg;
Aleksandar Gerasimovski50dae8e2021-06-04 13:40:58 +0000829 u32 max_speed;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800830 int ret;
831
Hou Zhiqiang7fb568d2020-07-16 18:09:14 +0800832 data = (struct tsec_data *)dev_get_driver_data(dev);
833
Mario Six1313aaf2018-01-15 11:08:23 +0100834 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
Bin Menga0815462021-03-14 20:15:01 +0800835 if (pdata->iobase == FDT_ADDR_T_NONE) {
836 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
837 if (strncmp(ofnode_get_name(child), "queue-group",
838 strlen("queue-group")))
839 continue;
840
841 reg = ofnode_get_addr(child);
842 if (reg == FDT_ADDR_T_NONE) {
843 printf("No 'reg' property of <queue-group>\n");
844 return -ENOENT;
845 }
846 pdata->iobase = reg;
847
848 /*
849 * if there are multiple queue groups,
850 * only the first one is used.
851 */
852 break;
853 }
854
855 if (!ofnode_valid(child)) {
856 printf("No child node for <queue-group>?\n");
857 return -ENOENT;
858 }
859 }
860
Bin Meng408f0562021-03-14 20:14:59 +0800861 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800862
Vladimir Oltean29db3102019-07-19 00:29:53 +0300863 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
864 &phandle_args);
Hou Zhiqianga0f47e02020-05-03 22:48:43 +0800865 if (ret == 0) {
Vladimir Oltean29db3102019-07-19 00:29:53 +0300866 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
867
Hou Zhiqianga0f47e02020-05-03 22:48:43 +0800868 parent = ofnode_get_parent(phandle_args.node);
869 if (!ofnode_valid(parent)) {
870 printf("No parent node for TBI PHY?\n");
871 return -ENOENT;
872 }
873
874 reg = ofnode_get_addr_index(parent, 0);
875 if (reg == FDT_ADDR_T_NONE) {
876 printf("No 'reg' property of MII for TBI PHY\n");
877 return -ENOENT;
878 }
879
Hou Zhiqiang7fb568d2020-07-16 18:09:14 +0800880 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
Hou Zhiqianga0f47e02020-05-03 22:48:43 +0800881 0, MAP_NOCACHE);
882 }
883
Vladimir Oltean29db3102019-07-19 00:29:53 +0300884 priv->tbiaddr = tbiaddr;
Bin Menga1c76c12016-01-11 22:41:25 -0800885
Mario Six1313aaf2018-01-15 11:08:23 +0100886 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
Vladimir Olteanbc4e9822021-09-18 15:46:55 +0300887 if (!phy_mode)
888 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800889 if (phy_mode)
890 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
Vladimir Olteand883a5f2021-09-18 15:46:54 +0300891 if (pdata->phy_interface == -1)
892 pdata->phy_interface = tsec_get_interface(priv);
893
Bin Meng9a1d6af2016-01-11 22:41:24 -0800894 priv->interface = pdata->phy_interface;
895
Aleksandar Gerasimovski50dae8e2021-06-04 13:40:58 +0000896 /* Check for speed limit, default is 1000Mbps */
897 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
898
Bin Meng9a1d6af2016-01-11 22:41:24 -0800899 /* Initialize flags */
Aleksandar Gerasimovski50dae8e2021-06-04 13:40:58 +0000900 if (max_speed == 1000)
901 priv->flags = TSEC_GIGABIT;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800902 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
903 priv->flags |= TSEC_SGMII;
904
Bin Meng9a1d6af2016-01-11 22:41:24 -0800905 /* Reset the MAC */
906 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
907 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
908 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
909
910 priv->dev = dev;
911 priv->bus = miiphy_get_dev_by_name(dev->name);
912
913 /* Try to initialize PHY here, and return */
914 return !init_phy(priv);
915}
916
917int tsec_remove(struct udevice *dev)
918{
Simon Glass0fd3d912020-12-22 19:30:28 -0700919 struct tsec_private *priv = dev_get_priv(dev);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800920
921 free(priv->phydev);
922 mdio_unregister(priv->bus);
923 mdio_free(priv->bus);
924
925 return 0;
926}
927
928static const struct eth_ops tsec_ops = {
929 .start = tsec_init,
930 .send = tsec_send,
931 .recv = tsec_recv,
932 .free_pkt = tsec_free_pkt,
933 .stop = tsec_halt,
Bin Meng9a1d6af2016-01-11 22:41:24 -0800934 .mcast = tsec_mcast_addr,
Bin Meng9a1d6af2016-01-11 22:41:24 -0800935};
936
Hou Zhiqiang7fb568d2020-07-16 18:09:14 +0800937static struct tsec_data etsec2_data = {
938 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
939};
940
941static struct tsec_data gianfar_data = {
942 .mdio_regs_off = 0x0,
943};
944
Bin Meng9a1d6af2016-01-11 22:41:24 -0800945static const struct udevice_id tsec_ids[] = {
Hou Zhiqiang7fb568d2020-07-16 18:09:14 +0800946 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
947 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
Bin Meng9a1d6af2016-01-11 22:41:24 -0800948 { }
949};
950
951U_BOOT_DRIVER(eth_tsec) = {
952 .name = "tsec",
953 .id = UCLASS_ETH,
954 .of_match = tsec_ids,
955 .probe = tsec_probe,
956 .remove = tsec_remove,
957 .ops = &tsec_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700958 .priv_auto = sizeof(struct tsec_private),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700959 .plat_auto = sizeof(struct eth_pdata),
Bin Meng9a1d6af2016-01-11 22:41:24 -0800960 .flags = DM_FLAG_ALLOC_PRIV_DMA,
961};
962#endif /* CONFIG_DM_ETH */