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Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*
Stefan Roese1bbf5ea2007-01-30 15:01:49 +01002 * (C) Copyright 2006-2007
Wolfgang Denkba94a1b2006-05-30 15:56:48 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Configuation settings for the PDNB3 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34#define CONFIG_PDNB3 1 /* on an PDNB3 board */
35
36#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
37#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
38
39/*
40 * Ethernet
41 */
42#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
43#define CONFIG_NET_MULTI 1
44#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
45#define CONFIG_HAS_ETH1
46#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
47#define CONFIG_MII 1 /* MII PHY management */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020049
50/*
51 * Misc configuration options
52 */
53#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
Jean-Christophe PLAGNIOL-VILLARDb54384e2009-05-15 23:47:02 +020054#define CONFIG_TIMER_IRQ
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020055
56#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020058
59#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
60#define CONFIG_SETUP_MEMORY_TAGS 1
61#define CONFIG_INITRD_TAG 1
62
63/*
64 * Size of malloc() pool
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_MALLOC_LEN (1 << 20)
67#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020068
69/* allow to overwrite serial and ethaddr */
70#define CONFIG_ENV_OVERWRITE
71
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010072#define CONFIG_IXP_SERIAL
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020073#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020075
Jon Loeliger26a34562007-07-04 22:33:17 -050076
77/*
Jon Loeliger079a1362007-07-10 10:12:10 -050078 * BOOTP options
79 */
80#define CONFIG_BOOTP_BOOTFILESIZE
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84
85
86/*
Jon Loeliger26a34562007-07-04 22:33:17 -050087 * Command line configuration.
88 */
89#include <config_cmd_default.h>
90
91#define CONFIG_CMD_DHCP
92#define CONFIG_CMD_DATE
93#define CONFIG_CMD_NET
94#define CONFIG_CMD_MII
95#define CONFIG_CMD_I2C
96#define CONFIG_CMD_ELF
97#define CONFIG_CMD_PING
98
99#if !defined(CONFIG_SCPU)
100#define CONFIG_CMD_NAND
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100101#endif
102
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200103
104#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
105#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
106
107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
111#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
119#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200122 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200124
125/*
126 * Stack sizes
127 *
128 * The stack sizes are set up in start.S using the settings below
129 */
130#define CONFIG_STACKSIZE (128*1024) /* regular stack */
131#ifdef CONFIG_USE_IRQ
132#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
133#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
134#endif
135
136/***************************************************************
137 * Platform/Board specific defines start here.
138 ***************************************************************/
139
140/*-----------------------------------------------------------------------
141 * Default configuration (environment varibles...)
142 *----------------------------------------------------------------------*/
143#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100144 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200145 "echo"
146
147#undef CONFIG_BOOTARGS
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "hostname=pdnb3\0" \
152 "nfsargs=setenv bootargs root=/dev/nfs rw " \
153 "nfsroot=${serverip}:${rootpath}\0" \
154 "ramargs=setenv bootargs root=/dev/ram rw\0" \
155 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
156 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
157 ":${hostname}:${netdev}:off panic=1\0" \
158 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
159 "mtdparts=${mtdparts}\0" \
160 "flash_nfs=run nfsargs addip addtty;" \
161 "bootm ${kernel_addr}\0" \
162 "flash_self=run ramargs addip addtty;" \
163 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
164 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
165 "bootm\0" \
166 "rootpath=/opt/buildroot\0" \
167 "bootfile=/tftpboot/netbox/uImage\0" \
168 "kernel_addr=50080000\0" \
169 "ramdisk_addr=50200000\0" \
170 "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
171 "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
172 "cp.b 100000 50000000 ${filesize};" \
173 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100174 "upd=run load update\0" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200175 "ipaddr=10.0.0.233\0" \
176 "serverip=10.0.0.152\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200177 "netmask=255.255.0.0\0" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200178 "ethaddr=c6:6f:13:36:f3:81\0" \
179 "eth1addr=c6:6f:13:36:f3:82\0" \
180 "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
181 "4k@508k(renv)\0" \
182 ""
183#define CONFIG_BOOTCOMMAND "run net_nfs"
184
185/*
186 * Physical Memory Map
187 */
188#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
189#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
190#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_BASE 0x50000000
193#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100194#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100196#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100198#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200199
200/*
201 * Expansion bus settings
202 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100203#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100205#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100207#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200209
210/*
211 * SDRAM settings
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_SDR_CONFIG 0x18
214#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
215#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200216
217/*
218 * FLASH and environment organization
219 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100220#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200222#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100224#endif
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
232#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
235#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
236#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200237/*
238 * The following defines are added for buggy IOP480 byte interface.
239 * All other boards should use the standard values (CPCI405 etc.)
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
242#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
243#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200246
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200247#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100250#if defined(CONFIG_SCPU)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100251/* no redundant environment on SCPU */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200252#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
253#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100254#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200255#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
256#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200257
258/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200259#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
260#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100261#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200262
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100263#if !defined(CONFIG_SCPU)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200264/*
265 * NAND-FLASH stuff
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200268#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100269#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200270
271/*
272 * GPIO settings
273 */
274
275/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
277#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
278#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
279#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
280#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200281
282/* other GPIO's */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_GPIO_RESTORE_INT 0
284#define CONFIG_SYS_GPIO_RESTART_INT 1
285#define CONFIG_SYS_GPIO_SYS_RUNNING 2
286#define CONFIG_SYS_GPIO_PCI_INTA 3
287#define CONFIG_SYS_GPIO_PCI_INTB 4
288#define CONFIG_SYS_GPIO_I2C_SCL 6
289#define CONFIG_SYS_GPIO_I2C_SDA 7
290#define CONFIG_SYS_GPIO_FPGA_RESET 9
291#define CONFIG_SYS_GPIO_CLK_33M 15
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200292
293/*
294 * I2C stuff
295 */
296
297/* enable I2C and select the hardware/software driver */
298#undef CONFIG_HARD_I2C /* I2C with hardware support */
299#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
302#define CONFIG_SYS_I2C_SLAVE 0xFE
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200303
304/*
305 * Software (bit-bang) I2C driver configuration
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
308#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
311#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
312#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200313#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
315 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
316#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
317 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200318#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
319
320/*
321 * I2C RTC
322 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100323#if 0 /* test-only */
324#define CONFIG_RTC_DS1340 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100326#else
327/* M41T11 Serial Access Timekeeper(R) SRAM */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200328#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_I2C_RTC_ADDR 0x68
330#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100331#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200332
333/*
334 * Spartan3 FPGA configuration support
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
339#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
340#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
341#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
342#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200343
344/*
345 * Cache Configuration
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200348
349#endif /* __CONFIG_H */