Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Freescale ls1021a SOC common device tree source |
| 4 | * |
| 5 | * Copyright 2013-2015 Freescale Semiconductor, Inc. |
Gaurav Jain | 88071ca | 2022-03-24 11:50:34 +0530 | [diff] [blame] | 6 | * Copyright 2021 NXP |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 9 | #include "skeleton.dtsi" |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | |
| 12 | / { |
| 13 | compatible = "fsl,ls1021a"; |
| 14 | interrupt-parent = <&gic>; |
| 15 | |
| 16 | aliases { |
| 17 | serial0 = &lpuart0; |
| 18 | serial1 = &lpuart1; |
| 19 | serial2 = &lpuart2; |
| 20 | serial3 = &lpuart3; |
| 21 | serial4 = &lpuart4; |
| 22 | serial5 = &lpuart5; |
| 23 | sysclk = &sysclk; |
| 24 | }; |
| 25 | |
| 26 | cpus { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | |
| 30 | cpu@f00 { |
| 31 | compatible = "arm,cortex-a7"; |
| 32 | device_type = "cpu"; |
| 33 | reg = <0xf00>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 34 | clocks = <&clockgen 1 0>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | cpu@f01 { |
| 38 | compatible = "arm,cortex-a7"; |
| 39 | device_type = "cpu"; |
| 40 | reg = <0xf01>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 41 | clocks = <&clockgen 1 0>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 42 | }; |
| 43 | }; |
| 44 | |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 45 | sysclk: sysclk { |
| 46 | compatible = "fixed-clock"; |
| 47 | #clock-cells = <0>; |
| 48 | clock-frequency = <100000000>; |
| 49 | clock-output-names = "sysclk"; |
| 50 | }; |
| 51 | |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 52 | timer { |
| 53 | compatible = "arm,armv7-timer"; |
| 54 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 55 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 56 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 57 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 58 | }; |
| 59 | |
| 60 | pmu { |
| 61 | compatible = "arm,cortex-a7-pmu"; |
| 62 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| 64 | }; |
| 65 | |
| 66 | soc { |
| 67 | compatible = "simple-bus"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 68 | #address-cells = <1>; |
| 69 | #size-cells = <1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 70 | device_type = "soc"; |
| 71 | interrupt-parent = <&gic>; |
| 72 | ranges; |
| 73 | |
| 74 | gic: interrupt-controller@1400000 { |
| 75 | compatible = "arm,cortex-a7-gic"; |
| 76 | #interrupt-cells = <3>; |
| 77 | interrupt-controller; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 78 | reg = <0x1401000 0x1000>, |
| 79 | <0x1402000 0x1000>, |
| 80 | <0x1404000 0x2000>, |
| 81 | <0x1406000 0x2000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 82 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 83 | |
| 84 | }; |
| 85 | |
| 86 | ifc: ifc@1530000 { |
| 87 | compatible = "fsl,ifc", "simple-bus"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 88 | reg = <0x1530000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 89 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 90 | }; |
| 91 | |
| 92 | dcfg: dcfg@1ee0000 { |
| 93 | compatible = "fsl,ls1021a-dcfg", "syscon"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 94 | reg = <0x1ee0000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 95 | big-endian; |
| 96 | }; |
| 97 | |
| 98 | esdhc: esdhc@1560000 { |
| 99 | compatible = "fsl,esdhc"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 100 | reg = <0x1560000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 101 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 102 | clock-frequency = <0>; |
| 103 | voltage-ranges = <1800 1800 3300 3300>; |
| 104 | sdhci,auto-cmd12; |
| 105 | big-endian; |
| 106 | bus-width = <4>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 107 | }; |
| 108 | |
Biwen Li | 2b3393c | 2021-02-05 19:01:48 +0800 | [diff] [blame] | 109 | gpio0: gpio@2300000 { |
| 110 | compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; |
Lasse Klok Mikkelsen | fb6c96f | 2021-06-08 08:39:12 +0200 | [diff] [blame] | 111 | reg = <0x2300000 0x10000>; |
Biwen Li | 2b3393c | 2021-02-05 19:01:48 +0800 | [diff] [blame] | 112 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | gpio-controller; |
| 114 | #gpio-cells = <2>; |
| 115 | interrupt-controller; |
| 116 | #interrupt-cells = <2>; |
| 117 | }; |
| 118 | |
| 119 | gpio1: gpio@2310000 { |
| 120 | compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; |
Lasse Klok Mikkelsen | fb6c96f | 2021-06-08 08:39:12 +0200 | [diff] [blame] | 121 | reg = <0x2310000 0x10000>; |
Biwen Li | 2b3393c | 2021-02-05 19:01:48 +0800 | [diff] [blame] | 122 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| 123 | gpio-controller; |
| 124 | #gpio-cells = <2>; |
| 125 | interrupt-controller; |
| 126 | #interrupt-cells = <2>; |
| 127 | }; |
| 128 | |
| 129 | gpio2: gpio@2320000 { |
| 130 | compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; |
Lasse Klok Mikkelsen | fb6c96f | 2021-06-08 08:39:12 +0200 | [diff] [blame] | 131 | reg = <0x2320000 0x10000>; |
Biwen Li | 2b3393c | 2021-02-05 19:01:48 +0800 | [diff] [blame] | 132 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 133 | gpio-controller; |
| 134 | #gpio-cells = <2>; |
| 135 | interrupt-controller; |
| 136 | #interrupt-cells = <2>; |
| 137 | }; |
| 138 | |
| 139 | gpio3: gpio@2330000 { |
| 140 | compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; |
Lasse Klok Mikkelsen | fb6c96f | 2021-06-08 08:39:12 +0200 | [diff] [blame] | 141 | reg = <0x2330000 0x10000>; |
Biwen Li | 2b3393c | 2021-02-05 19:01:48 +0800 | [diff] [blame] | 142 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| 143 | gpio-controller; |
| 144 | #gpio-cells = <2>; |
| 145 | interrupt-controller; |
| 146 | #interrupt-cells = <2>; |
| 147 | }; |
| 148 | |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 149 | scfg: scfg@1570000 { |
| 150 | compatible = "fsl,ls1021a-scfg", "syscon"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 151 | reg = <0x1570000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 152 | big-endian; |
| 153 | }; |
| 154 | |
Gaurav Jain | 88071ca | 2022-03-24 11:50:34 +0530 | [diff] [blame] | 155 | crypto: crypto@1700000 { |
| 156 | compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; |
| 157 | fsl,sec-era = <7>; |
| 158 | #address-cells = <1>; |
| 159 | #size-cells = <1>; |
| 160 | reg = <0x1700000 0x100000>; |
| 161 | ranges = <0x0 0x1700000 0x100000>; |
| 162 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 163 | |
| 164 | sec_jr0: jr@10000 { |
| 165 | compatible = "fsl,sec-v5.0-job-ring", |
| 166 | "fsl,sec-v4.0-job-ring"; |
| 167 | reg = <0x10000 0x10000>; |
| 168 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 169 | }; |
| 170 | |
| 171 | sec_jr1: jr@20000 { |
| 172 | compatible = "fsl,sec-v5.0-job-ring", |
| 173 | "fsl,sec-v4.0-job-ring"; |
| 174 | reg = <0x20000 0x10000>; |
| 175 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | }; |
| 177 | |
| 178 | sec_jr2: jr@30000 { |
| 179 | compatible = "fsl,sec-v5.0-job-ring", |
| 180 | "fsl,sec-v4.0-job-ring"; |
| 181 | reg = <0x30000 0x10000>; |
| 182 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 183 | }; |
| 184 | |
| 185 | sec_jr3: jr@40000 { |
| 186 | compatible = "fsl,sec-v5.0-job-ring", |
| 187 | "fsl,sec-v4.0-job-ring"; |
| 188 | reg = <0x40000 0x10000>; |
| 189 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 190 | }; |
| 191 | |
| 192 | }; |
| 193 | |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 194 | clockgen: clocking@1ee1000 { |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 195 | compatible = "fsl,ls1021a-clockgen"; |
| 196 | reg = <0x0 0x1ee1000 0x0 0x1000>; |
| 197 | #clock-cells = <2>; |
| 198 | clocks = <&sysclk>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | dspi0: dspi@2100000 { |
| 202 | compatible = "fsl,vf610-dspi"; |
| 203 | #address-cells = <1>; |
| 204 | #size-cells = <0>; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 205 | reg = <0x2100000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 206 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 207 | clock-names = "dspi"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 208 | clocks = <&clockgen 4 1>; |
Michael Walle | 8c58089 | 2021-10-13 18:14:18 +0200 | [diff] [blame] | 209 | spi-num-chipselects = <6>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 210 | big-endian; |
| 211 | status = "disabled"; |
| 212 | }; |
| 213 | |
| 214 | dspi1: dspi@2110000 { |
| 215 | compatible = "fsl,vf610-dspi"; |
| 216 | #address-cells = <1>; |
| 217 | #size-cells = <0>; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 218 | reg = <0x2110000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 219 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 220 | clock-names = "dspi"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 221 | clocks = <&clockgen 4 1>; |
Michael Walle | 8c58089 | 2021-10-13 18:14:18 +0200 | [diff] [blame] | 222 | spi-num-chipselects = <6>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 223 | big-endian; |
| 224 | status = "disabled"; |
| 225 | }; |
| 226 | |
Haikun.Wang@freescale.com | 863b4e1 | 2015-03-24 21:20:40 +0800 | [diff] [blame] | 227 | qspi: quadspi@1550000 { |
Kuldeep Singh | b480bcc | 2019-12-12 11:49:24 +0530 | [diff] [blame] | 228 | compatible = "fsl,ls1021a-qspi"; |
Haikun.Wang@freescale.com | 863b4e1 | 2015-03-24 21:20:40 +0800 | [diff] [blame] | 229 | #address-cells = <1>; |
| 230 | #size-cells = <0>; |
| 231 | reg = <0x1550000 0x10000>, |
Kuldeep Singh | b480bcc | 2019-12-12 11:49:24 +0530 | [diff] [blame] | 232 | <0x40000000 0x1000000>; |
Yuan Yao | 93a1b7c | 2016-11-30 11:26:20 +0800 | [diff] [blame] | 233 | reg-names = "QuadSPI", "QuadSPI-memory"; |
Haikun.Wang@freescale.com | 863b4e1 | 2015-03-24 21:20:40 +0800 | [diff] [blame] | 234 | status = "disabled"; |
| 235 | }; |
| 236 | |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 237 | i2c0: i2c@2180000 { |
| 238 | compatible = "fsl,vf610-i2c"; |
| 239 | #address-cells = <1>; |
| 240 | #size-cells = <0>; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 241 | reg = <0x2180000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 242 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 243 | clock-names = "i2c"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 244 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
| 248 | i2c1: i2c@2190000 { |
| 249 | compatible = "fsl,vf610-i2c"; |
| 250 | #address-cells = <1>; |
| 251 | #size-cells = <0>; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 252 | reg = <0x2190000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 253 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 254 | clock-names = "i2c"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 255 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 256 | status = "disabled"; |
| 257 | }; |
| 258 | |
| 259 | i2c2: i2c@21a0000 { |
| 260 | compatible = "fsl,vf610-i2c"; |
| 261 | #address-cells = <1>; |
| 262 | #size-cells = <0>; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 263 | reg = <0x21a0000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 264 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 265 | clock-names = "i2c"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 266 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 267 | status = "disabled"; |
| 268 | }; |
| 269 | |
| 270 | uart0: serial@21c0500 { |
| 271 | compatible = "fsl,16550-FIFO64", "ns16550a"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 272 | reg = <0x21c0500 0x100>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 273 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 274 | fifo-size = <15>; |
| 275 | status = "disabled"; |
| 276 | }; |
| 277 | |
| 278 | uart1: serial@21c0600 { |
| 279 | compatible = "fsl,16550-FIFO64", "ns16550a"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 280 | reg = <0x21c0600 0x100>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 281 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 282 | fifo-size = <15>; |
| 283 | status = "disabled"; |
| 284 | }; |
| 285 | |
| 286 | uart2: serial@21d0500 { |
| 287 | compatible = "fsl,16550-FIFO64", "ns16550a"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 288 | reg = <0x21d0500 0x100>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 289 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 290 | fifo-size = <15>; |
| 291 | status = "disabled"; |
| 292 | }; |
| 293 | |
| 294 | uart3: serial@21d0600 { |
| 295 | compatible = "fsl,16550-FIFO64", "ns16550a"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 296 | reg = <0x21d0600 0x100>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 297 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 298 | fifo-size = <15>; |
| 299 | status = "disabled"; |
| 300 | }; |
| 301 | |
| 302 | lpuart0: serial@2950000 { |
| 303 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 304 | reg = <0x2950000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 305 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 306 | clocks = <&sysclk>; |
| 307 | clock-names = "ipg"; |
| 308 | status = "disabled"; |
| 309 | }; |
| 310 | |
| 311 | lpuart1: serial@2960000 { |
| 312 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 313 | reg = <0x2960000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 314 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 315 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 316 | clock-names = "ipg"; |
| 317 | status = "disabled"; |
| 318 | }; |
| 319 | |
| 320 | lpuart2: serial@2970000 { |
| 321 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 322 | reg = <0x2970000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 323 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 324 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 325 | clock-names = "ipg"; |
| 326 | status = "disabled"; |
| 327 | }; |
| 328 | |
| 329 | lpuart3: serial@2980000 { |
| 330 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 331 | reg = <0x2980000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 332 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 333 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 334 | clock-names = "ipg"; |
| 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
| 338 | lpuart4: serial@2990000 { |
| 339 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 340 | reg = <0x2990000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 341 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 342 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 343 | clock-names = "ipg"; |
| 344 | status = "disabled"; |
| 345 | }; |
| 346 | |
| 347 | lpuart5: serial@29a0000 { |
| 348 | compatible = "fsl,ls1021a-lpuart"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 349 | reg = <0x29a0000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 350 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 351 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 352 | clock-names = "ipg"; |
| 353 | status = "disabled"; |
| 354 | }; |
| 355 | |
| 356 | wdog0: watchdog@2ad0000 { |
| 357 | compatible = "fsl,imx21-wdt"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 358 | reg = <0x2ad0000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 359 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 360 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 361 | clock-names = "wdog-en"; |
| 362 | big-endian; |
| 363 | }; |
| 364 | |
| 365 | sai1: sai@2b50000 { |
| 366 | compatible = "fsl,vf610-sai"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 367 | reg = <0x2b50000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 368 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 369 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 370 | clock-names = "sai"; |
| 371 | dma-names = "tx", "rx"; |
| 372 | dmas = <&edma0 1 47>, |
| 373 | <&edma0 1 46>; |
| 374 | big-endian; |
| 375 | status = "disabled"; |
| 376 | }; |
| 377 | |
| 378 | sai2: sai@2b60000 { |
| 379 | compatible = "fsl,vf610-sai"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 380 | reg = <0x2b60000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 381 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 382 | clocks = <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 383 | clock-names = "sai"; |
| 384 | dma-names = "tx", "rx"; |
| 385 | dmas = <&edma0 1 45>, |
| 386 | <&edma0 1 44>; |
| 387 | big-endian; |
| 388 | status = "disabled"; |
| 389 | }; |
| 390 | |
| 391 | edma0: edma@2c00000 { |
| 392 | #dma-cells = <2>; |
| 393 | compatible = "fsl,vf610-edma"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 394 | reg = <0x2c00000 0x10000>, |
| 395 | <0x2c10000 0x10000>, |
| 396 | <0x2c20000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 397 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 398 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; |
| 399 | interrupt-names = "edma-tx", "edma-err"; |
| 400 | dma-channels = <32>; |
| 401 | big-endian; |
| 402 | clock-names = "dmamux0", "dmamux1"; |
Sean Anderson | f99068a | 2022-04-22 14:34:19 -0400 | [diff] [blame^] | 403 | clocks = <&clockgen 4 1>, |
| 404 | <&clockgen 4 1>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 405 | }; |
| 406 | |
Bin Meng | f588b4d | 2019-07-19 00:29:59 +0300 | [diff] [blame] | 407 | enet0: ethernet@2d10000 { |
| 408 | compatible = "fsl,etsec2"; |
| 409 | reg = <0x2d10000 0x1000>; |
| 410 | status = "disabled"; |
| 411 | }; |
| 412 | |
| 413 | enet1: ethernet@2d50000 { |
| 414 | compatible = "fsl,etsec2"; |
| 415 | reg = <0x2d50000 0x1000>; |
| 416 | status = "disabled"; |
| 417 | }; |
| 418 | |
| 419 | enet2: ethernet@2d90000 { |
| 420 | compatible = "fsl,etsec2"; |
| 421 | reg = <0x2d90000 0x1000>; |
| 422 | status = "disabled"; |
| 423 | }; |
| 424 | |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 425 | mdio0: mdio@2d24000 { |
Bin Meng | f588b4d | 2019-07-19 00:29:59 +0300 | [diff] [blame] | 426 | compatible = "fsl,etsec2-mdio"; |
| 427 | reg = <0x2d24000 0x4000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 428 | #address-cells = <1>; |
| 429 | #size-cells = <0>; |
Bin Meng | f588b4d | 2019-07-19 00:29:59 +0300 | [diff] [blame] | 430 | }; |
| 431 | |
| 432 | mdio1: mdio@2d64000 { |
| 433 | compatible = "fsl,etsec2-mdio"; |
| 434 | reg = <0x2d64000 0x4000>; |
| 435 | #address-cells = <1>; |
| 436 | #size-cells = <0>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 437 | }; |
| 438 | |
| 439 | usb@8600000 { |
| 440 | compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 441 | reg = <0x8600000 0x1000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 442 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| 443 | dr_mode = "host"; |
| 444 | phy_type = "ulpi"; |
| 445 | }; |
| 446 | |
| 447 | usb3@3100000 { |
Rajesh Bhagat | a866c21 | 2016-07-01 18:51:48 +0530 | [diff] [blame] | 448 | compatible = "fsl,layerscape-dwc3"; |
haikun | ce35fc1 | 2015-03-24 21:16:31 +0800 | [diff] [blame] | 449 | reg = <0x3100000 0x10000>; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 450 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 451 | dr_mode = "host"; |
| 452 | }; |
Minghuan Lian | add73a1 | 2016-12-13 14:54:11 +0800 | [diff] [blame] | 453 | |
| 454 | pcie@3400000 { |
| 455 | compatible = "fsl,ls-pcie", "snps,dw-pcie"; |
| 456 | reg = <0x03400000 0x20000 /* dbi registers */ |
| 457 | 0x01570000 0x10000 /* pf controls registers */ |
| 458 | 0x24000000 0x20000>; /* configuration space */ |
| 459 | reg-names = "dbi", "ctrl", "config"; |
| 460 | big-endian; |
| 461 | #address-cells = <3>; |
| 462 | #size-cells = <2>; |
| 463 | device_type = "pci"; |
| 464 | bus-range = <0x0 0xff>; |
| 465 | ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */ |
| 466 | 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */ |
| 467 | }; |
| 468 | |
| 469 | pcie@3500000 { |
| 470 | compatible = "fsl,ls-pcie", "snps,dw-pcie"; |
| 471 | reg = <0x03500000 0x10000 /* dbi registers */ |
| 472 | 0x01570000 0x10000 /* pf controls registers */ |
| 473 | 0x34000000 0x20000>; /* configuration space */ |
| 474 | reg-names = "dbi", "ctrl", "config"; |
| 475 | big-endian; |
| 476 | #address-cells = <3>; |
| 477 | #size-cells = <2>; |
| 478 | device_type = "pci"; |
| 479 | num-lanes = <2>; |
| 480 | bus-range = <0x0 0xff>; |
| 481 | ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ |
| 482 | 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ |
| 483 | }; |
Peng Ma | 9ed5ec9 | 2018-08-01 14:15:41 +0800 | [diff] [blame] | 484 | |
| 485 | sata: sata@3200000 { |
| 486 | compatible = "fsl,ls1021a-ahci"; |
Peng Ma | f68ce9e | 2019-05-29 02:40:47 +0000 | [diff] [blame] | 487 | reg = <0x3200000 0x10000 0x20220520 0x4>; |
Michael Walle | cde9b14 | 2021-10-13 18:14:20 +0200 | [diff] [blame] | 488 | reg-names = "ahci", "sata-ecc"; |
Peng Ma | 9ed5ec9 | 2018-08-01 14:15:41 +0800 | [diff] [blame] | 489 | interrupts = <0 101 4>; |
| 490 | status = "disabled"; |
| 491 | }; |
haikun | ddf79f3 | 2015-03-25 20:23:26 +0800 | [diff] [blame] | 492 | }; |
| 493 | }; |