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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
Shinya Kuribayashi5dfb3ee2008-10-19 12:08:50 +090026#include <netdev.h>
wdenk5da627a2003-10-09 20:09:04 +000027#include <asm/mipsregs.h>
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090028#include <asm/cacheops.h>
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090029#include <asm/reboot.h>
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090030
31#define cache_op(op,addr) \
32 __asm__ __volatile__( \
33 " .set push \n" \
34 " .set noreorder \n" \
35 " .set mips3\n\t \n" \
36 " cache %0, %1 \n" \
37 " .set pop \n" \
38 : \
39 : "i" (op), "R" (*(unsigned char *)(addr)))
wdenkc0218802003-03-27 12:09:35 +000040
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090041void __attribute__((weak)) _machine_restart(void)
42{
43}
44
wdenkc0218802003-03-27 12:09:35 +000045int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
46{
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090047 _machine_restart();
wdenk3e386912003-04-05 00:53:31 +000048
wdenkc0218802003-03-27 12:09:35 +000049 fprintf(stderr, "*** reset failed ***\n");
50 return 0;
51}
52
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +090053void flush_cache(ulong start_addr, ulong size)
wdenkc0218802003-03-27 12:09:35 +000054{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090056 unsigned long addr = start_addr & ~(lsize - 1);
57 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
58
59 while (1) {
Shinya Kuribayashi188e94c2008-04-08 16:20:35 +090060 cache_op(Hit_Writeback_Inv_D, addr);
61 cache_op(Hit_Invalidate_I, addr);
Shinya Kuribayashiccf8f822008-03-25 21:30:06 +090062 if (addr == aend)
63 break;
64 addr += lsize;
65 }
wdenkc0218802003-03-27 12:09:35 +000066}
wdenk5da627a2003-10-09 20:09:04 +000067
Stefan Roese03d3bfb2009-01-21 17:20:20 +010068void flush_dcache_range(ulong start_addr, ulong stop)
69{
70 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
71 unsigned long addr = start_addr & ~(lsize - 1);
72 unsigned long aend = (stop - 1) & ~(lsize - 1);
73
74 while (1) {
75 cache_op(Hit_Writeback_Inv_D, addr);
76 if (addr == aend)
77 break;
78 addr += lsize;
79 }
80}
81
82void invalidate_dcache_range(ulong start_addr, ulong stop)
83{
84 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
85 unsigned long addr = start_addr & ~(lsize - 1);
86 unsigned long aend = (stop - 1) & ~(lsize - 1);
87
88 while (1) {
89 cache_op(Hit_Invalidate_D, addr);
90 if (addr == aend)
91 break;
92 addr += lsize;
93 }
94}
95
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +090096void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
97{
Shinya Kuribayashie2ad8422008-05-30 00:53:38 +090098 write_c0_entrylo0(low0);
99 write_c0_pagemask(pagemask);
100 write_c0_entrylo1(low1);
101 write_c0_entryhi(hi);
102 write_c0_index(index);
wdenk5da627a2003-10-09 20:09:04 +0000103 tlb_write_indexed();
104}
Shinya Kuribayashi5dfb3ee2008-10-19 12:08:50 +0900105
106int cpu_eth_init(bd_t *bis)
107{
108#ifdef CONFIG_SOC_AU1X00
109 au1x00_enet_initialize(bis);
110#endif
111 return 0;
112}