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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5272C3 board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkbf9e3b32004-02-12 00:47:09 +00007 */
wdenk4e5ca3e2003-12-08 01:34:36 +00008
wdenkbf9e3b32004-02-12 00:47:09 +00009/*
10 * board/config.h - configuration options, board specific
11 */
wdenk4e5ca3e2003-12-08 01:34:36 +000012
wdenkbf9e3b32004-02-12 00:47:09 +000013#ifndef _M5272C3_H
14#define _M5272C3_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050020#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000021
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000024#define CONFIG_BAUDRATE 115200
wdenk4e5ca3e2003-12-08 01:34:36 +000025
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050026#undef CONFIG_WATCHDOG
wdenkbf9e3b32004-02-12 00:47:09 +000027#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
28
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050029#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000030
31/* Configuration for environment
32 * Environment is embedded in u-boot in the second sector of the flash
33 */
34#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020035#define CONFIG_ENV_OFFSET 0x4000
36#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020037#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000038#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020039#define CONFIG_ENV_ADDR 0xffe04000
40#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020041#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000042#endif
43
angelo@sysam.it5296cb12015-03-29 22:54:16 +020044#define LDS_BOARD_TEXT \
45 . = DEFINED(env_offset) ? env_offset : .; \
46 common/env_embedded.o (.text);
47
Jon Loeliger8353e132007-07-08 14:14:17 -050048/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050049 * BOOTP options
50 */
51#define CONFIG_BOOTP_BOOTFILESIZE
52#define CONFIG_BOOTP_BOOTPATH
53#define CONFIG_BOOTP_GATEWAY
54#define CONFIG_BOOTP_HOSTNAME
55
Jon Loeliger659e2f62007-07-10 09:10:49 -050056/*
Jon Loeliger8353e132007-07-08 14:14:17 -050057 * Command line configuration.
58 */
Jon Loeliger8353e132007-07-08 14:14:17 -050059
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050060#define CONFIG_MCFFEC
61#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050062# define CONFIG_MII 1
TsiChung Liewd53cf6a2008-08-19 00:37:13 +060063# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064# define CONFIG_SYS_DISCOVER_PHY
65# define CONFIG_SYS_RX_ETH_BUFFER 8
66# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068# define CONFIG_SYS_FEC0_PINMUX 0
69# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020070# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
72# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050073# define FECDUPLEX FULL
74# define FECSPEED _100BASET
75# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
77# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050078# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050080#endif
81
82#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050083# define CONFIG_IPADDR 192.162.1.2
84# define CONFIG_NETMASK 255.255.255.0
85# define CONFIG_SERVERIP 192.162.1.1
86# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050087#endif /* CONFIG_MCFFEC */
88
89#define CONFIG_HOSTNAME M5272C3
90#define CONFIG_EXTRA_ENV_SETTINGS \
91 "netdev=eth0\0" \
92 "loadaddr=10000\0" \
93 "u-boot=u-boot.bin\0" \
94 "load=tftp ${loadaddr) ${u-boot}\0" \
95 "upd=run load; run prog\0" \
96 "prog=prot off ffe00000 ffe3ffff;" \
97 "era ffe00000 ffe3ffff;" \
98 "cp.b ${loadaddr} ffe00000 ${filesize};"\
99 "save\0" \
100 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000103
Jon Loeliger8353e132007-07-08 14:14:17 -0500104#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000106#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000108#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113#define CONFIG_SYS_LOAD_ADDR 0x20000
114#define CONFIG_SYS_MEMTEST_START 0x400
115#define CONFIG_SYS_MEMTEST_END 0x380000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_CLK 66000000
wdenkbf9e3b32004-02-12 00:47:09 +0000117
118/*
119 * Low Level Configuration Settings
120 * (address mappings, register initial values, etc.)
121 * You should know what you are doing if you make changes here.
122 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
124#define CONFIG_SYS_SCR 0x0003
125#define CONFIG_SYS_SPR 0xffff
wdenkbf9e3b32004-02-12 00:47:09 +0000126
wdenkbf9e3b32004-02-12 00:47:09 +0000127/*-----------------------------------------------------------------------
128 * Definitions for initial stack pointer and data area (in DPRAM)
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200131#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200132#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000134
135/*-----------------------------------------------------------------------
136 * Start addresses for the final memory configuration
137 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_SDRAM_BASE 0x00000000
141#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
142#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkbf9e3b32004-02-12 00:47:09 +0000143
144#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000146#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkbf9e3b32004-02-12 00:47:09 +0000148#endif
149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MONITOR_LEN 0x20000
151#define CONFIG_SYS_MALLOC_LEN (256 << 10)
152#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000153
154/*
155 * For booting Linux, the board info and command line data
156 * have to be in the first 8 MB of memory, since this is
157 * the maximum mapped by the Linux kernel during initialization ??
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000160
TsiChung Liewb2028162008-10-21 14:19:26 +0000161/*
wdenkbf9e3b32004-02-12 00:47:09 +0000162 * FLASH organization
163 */
TsiChung Liewb2028162008-10-21 14:19:26 +0000164#define CONFIG_SYS_FLASH_CFI
165#ifdef CONFIG_SYS_FLASH_CFI
166# define CONFIG_FLASH_CFI_DRIVER 1
167# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
168# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
169# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
170# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
171# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
172#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000173
174/*-----------------------------------------------------------------------
175 * Cache Configuration
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000178
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600179#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200180 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600181#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200182 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600183#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
184#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
185 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
186 CF_ACR_EN | CF_ACR_SM_ALL)
187#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
188 CF_CACR_DISD | CF_CACR_INVI | \
189 CF_CACR_CEIB | CF_CACR_DCM | \
190 CF_CACR_EUSP)
191
wdenkbf9e3b32004-02-12 00:47:09 +0000192/*-----------------------------------------------------------------------
193 * Memory bank definitions
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
196#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
197#define CONFIG_SYS_BR1_PRELIM 0
198#define CONFIG_SYS_OR1_PRELIM 0
199#define CONFIG_SYS_BR2_PRELIM 0x30000001
200#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
201#define CONFIG_SYS_BR3_PRELIM 0
202#define CONFIG_SYS_OR3_PRELIM 0
203#define CONFIG_SYS_BR4_PRELIM 0
204#define CONFIG_SYS_OR4_PRELIM 0
205#define CONFIG_SYS_BR5_PRELIM 0
206#define CONFIG_SYS_OR5_PRELIM 0
207#define CONFIG_SYS_BR6_PRELIM 0
208#define CONFIG_SYS_OR6_PRELIM 0
209#define CONFIG_SYS_BR7_PRELIM 0x00000701
210#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
wdenkbf9e3b32004-02-12 00:47:09 +0000211
212/*-----------------------------------------------------------------------
213 * Port configuration
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_PACNT 0x00000000
216#define CONFIG_SYS_PADDR 0x0000
217#define CONFIG_SYS_PADAT 0x0000
218#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
219#define CONFIG_SYS_PBDDR 0x0000
220#define CONFIG_SYS_PBDAT 0x0000
221#define CONFIG_SYS_PDCNT 0x00000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500222#endif /* _M5272C3_H */